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Commit a2946a36 authored by Russell King's avatar Russell King
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Tidy up abort handler selection. Use new glue.h to select relevant 

handler to allow for better optimisation.
parent afa223c5
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Showing with 106 additions and 46 deletions
arch/arm/kernel/entry-armv.S
View file @ a2946a36
......@@ -16,6 +16,7 @@
#include <linux/config.h>
#include "entry-header.S"
#include <asm/thread_info.h>
#include <asm/glue.h>
#ifdef IOC_BASE
......@@ -681,12 +682,12 @@ __dabt_svc: sub sp, sp, #S_FRAME_SIZE
/*
* This routine must not corrupt r9
*/
#ifdef MULTI_CPU
#ifdef MULTI_ABORT
ldr r4, .LCprocfns @ pass r0, r3 to
mov lr, pc @ processor code
ldr pc, [r4] @ call processor specific code
#else
bl cpu_data_abort
bl CPU_ABORT_HANDLER
#endif
msr cpsr_c, r9
mov r2, sp
......@@ -799,7 +800,7 @@ __pabt_svc: sub sp, sp, #S_FRAME_SIZE
.LCirq: .word __temp_irq
.LCund: .word __temp_und
.LCabt: .word __temp_abt
#ifdef MULTI_CPU
#ifdef MULTI_ABORT
.LCprocfns: .word SYMBOL_NAME(processor)
#endif
.LCfp: .word SYMBOL_NAME(fp_enter)
......@@ -823,12 +824,12 @@ __dabt_usr: sub sp, sp, #S_FRAME_SIZE @ Allocate frame size in one go
alignment_trap r7, r7, __temp_abt
zero_fp
mov r0, r2 @ remove once everyones in sync
#ifdef MULTI_CPU
#ifdef MULTI_ABORT
ldr r4, .LCprocfns @ pass r0, r3 to
mov lr, pc @ processor code
ldr pc, [r4] @ call processor specific code
#else
bl cpu_data_abort
bl CPU_ABORT_HANDLER
#endif
set_cpsr_c r2, #MODE_SVC @ Enable interrupts
mov r2, sp
......
arch/arm/mm/abort-ev4.S
View file @ a2946a36
#include <linux/linkage.h>
#include <asm/assembler.h>
/*
* Function: armv4_early_abort
* Function: v4_early_abort
*
* Params : r2 = address of aborted instruction
* : r3 = saved SPSR
......@@ -18,7 +18,7 @@
* picture. Unfortunately, this does happen. We live with it.
*/
.align 5
ENTRY(armv4_early_abort)
ENTRY(v4_early_abort)
mrc p15, 0, r1, c5, c0, 0 @ get FSR
mrc p15, 0, r0, c6, c0, 0 @ get FAR
ldr r3, [r2] @ read aborted ARM instruction
......
arch/arm/mm/abort-ev4t.S
View file @ a2946a36
#include <linux/linkage.h>
#include <asm/assembler.h>
/*
* Function: armv4t_early_abort
* Function: v4t_early_abort
*
* Params : r2 = address of aborted instruction
* : r3 = saved SPSR
......@@ -18,7 +18,7 @@
* picture. Unfortunately, this does happen. We live with it.
*/
.align 5
ENTRY(armv4t_early_abort)
ENTRY(v4t_early_abort)
mrc p15, 0, r1, c5, c0, 0 @ get FSR
mrc p15, 0, r0, c6, c0, 0 @ get FAR
tst r3, #PSR_T_BIT
......
arch/arm/mm/abort-ev5ej.S
View file @ a2946a36
#include <linux/linkage.h>
#include <asm/assembler.h>
/*
* Function: armv5ej_early_abort
* Function: v5ej_early_abort
*
* Params : r2 = address of aborted instruction
* : r3 = saved SPSR
......@@ -18,7 +18,7 @@
* picture. Unfortunately, this does happen. We live with it.
*/
.align 5
ENTRY(armv5ej_early_abort)
ENTRY(v5ej_early_abort)
mrc p15, 0, r1, c5, c0, 0 @ get FSR
mrc p15, 0, r0, c6, c0, 0 @ get FAR
tst r3, #PSR_J_BIT
......
arch/arm/mm/abort-lv4t.S
View file @ a2946a36
#include <linux/linkage.h>
#include <asm/assembler.h>
/*
* Function: armv4t_late_abort
* Function: v4t_late_abort
*
* Params : r2 = address of aborted instruction
* : r3 = saved SPSR
......@@ -17,7 +17,7 @@
* abort here if the I-TLB and D-TLB aren't seeing the same
* picture. Unfortunately, this does happen. We live with it.
*/
ENTRY(armv4t_late_abort)
ENTRY(v4t_late_abort)
tst r3, #PSR_T_BIT @ check for thumb mode
mrc p15, 0, r1, c5, c0, 0 @ get FSR
mrc p15, 0, r0, c6, c0, 0 @ get FAR
......
arch/arm/mm/proc-arm1020.S
View file @ a2946a36
......@@ -608,7 +608,7 @@ __arm1020_setup:
*/
.type arm1020_processor_functions, #object
arm1020_processor_functions:
.word armv4t_early_abort
.word v4t_early_abort
.word cpu_arm1020_check_bugs
.word cpu_arm1020_proc_init
.word cpu_arm1020_proc_fin
......
arch/arm/mm/proc-arm720.S
View file @ a2946a36
......@@ -199,7 +199,7 @@ __arm720_setup: mov r0, #0
*/
.type arm720_processor_functions, #object
ENTRY(arm720_processor_functions)
.word armv4t_late_abort
.word v4t_late_abort
.word cpu_arm720_check_bugs
.word cpu_arm720_proc_init
.word cpu_arm720_proc_fin
......
arch/arm/mm/proc-arm920.S
View file @ a2946a36
......@@ -511,7 +511,7 @@ __arm920_setup:
*/
.type arm920_processor_functions, #object
arm920_processor_functions:
.word armv4t_early_abort
.word v4t_early_abort
.word cpu_arm920_check_bugs
.word cpu_arm920_proc_init
.word cpu_arm920_proc_fin
......
arch/arm/mm/proc-arm922.S
View file @ a2946a36
......@@ -512,7 +512,7 @@ __arm922_setup:
*/
.type arm922_processor_functions, #object
arm922_processor_functions:
.word armv4t_early_abort
.word v4t_early_abort
.word cpu_arm922_check_bugs
.word cpu_arm922_proc_init
.word cpu_arm922_proc_fin
......
arch/arm/mm/proc-arm926.S
View file @ a2946a36
......@@ -549,7 +549,7 @@ __arm926_setup:
*/
.type arm926_processor_functions, #object
arm926_processor_functions:
.word armv5ej_early_abort
.word v5ej_early_abort
.word cpu_arm926_check_bugs
.word cpu_arm926_proc_init
.word cpu_arm926_proc_fin
......
arch/arm/mm/proc-sa110.S
View file @ a2946a36
......@@ -538,7 +538,7 @@ __setup_common:
.type sa110_processor_functions, #object
ENTRY(sa110_processor_functions)
.word armv4_early_abort
.word v4_early_abort
.word cpu_sa110_check_bugs
.word cpu_sa110_proc_init
.word cpu_sa110_proc_fin
......
arch/arm/mm/proc-xscale.S
View file @ a2946a36
......@@ -695,7 +695,7 @@ __xscale_setup:
.type xscale_processor_functions, #object
ENTRY(xscale_processor_functions)
.word armv4t_early_abort
.word v4t_early_abort
.word cpu_xscale_check_bugs
.word cpu_xscale_proc_init
.word cpu_xscale_proc_fin
......
include/asm-arm/cpu-multi32.h
View file @ a2946a36
......@@ -118,7 +118,6 @@ extern const struct processor arm6_processor_functions;
extern const struct processor arm7_processor_functions;
extern const struct processor sa110_processor_functions;
#define cpu_data_abort(pc) processor._data_abort(pc)
#define cpu_check_bugs() processor._check_bugs()
#define cpu_proc_init() processor._proc_init()
#define cpu_proc_fin() processor._proc_fin()
......
include/asm-arm/cpu-single.h
View file @ a2946a36
......@@ -22,7 +22,6 @@
* function pointers for this lot. Otherwise, we can optimise the
* table away.
*/
#define cpu_data_abort __cpu_fn(CPU_ABRT,_abort)
#define cpu_check_bugs __cpu_fn(CPU_NAME,_check_bugs)
#define cpu_proc_init __cpu_fn(CPU_NAME,_proc_init)
#define cpu_proc_fin __cpu_fn(CPU_NAME,_proc_fin)
......
include/asm-arm/glue.h
View file @ a2946a36
......@@ -24,14 +24,21 @@
#endif
#define __glue(name,fn) ____glue(name,fn)
/*
* Select MMU TLB handling.
*/
/*
* ARMv3 MMU
* MMU TLB Model
* =============
*
* We have the following to choose from:
* v3 - ARMv3
* v4 - ARMv4 without write buffer
* v4wb - ARMv4 with write buffer without I TLB flush entry instruction
* v4wbi - ARMv4 with write buffer with I TLB flush entry instruction
*/
#undef _TLB
#undef MULTI_TLB
#if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
# ifdef _TLB
# define MULTI_TLB 1
......@@ -40,9 +47,6 @@
# endif
#endif
/*
* ARMv4 MMU without write buffer
*/
#if defined(CONFIG_CPU_ARM720T)
# ifdef _TLB
# define MULTI_TLB 1
......@@ -51,9 +55,6 @@
# endif
#endif
/*
* ARMv4 MMU with write buffer, with invalidate I TLB entry instruction
*/
#if defined(CONFIG_CPU_ARM920T) || defined(CONFIG_CPU_ARM922T) || \
defined(CONFIG_CPU_ARM926T) || defined(CONFIG_CPU_ARM1020) || \
defined(CONFIG_CPU_XSCALE)
......@@ -64,9 +65,6 @@
# endif
#endif
/*
* ARMv4 MMU with write buffer, without invalidate I TLB entry instruction
*/
#if defined(CONFIG_CPU_SA110) || defined(CONFIG_CPU_SA1100)
# ifdef _TLB
# define MULTI_TLB 1
......@@ -75,4 +73,78 @@
# endif
#endif
#ifndef _TLB
#error Unknown TLB model
#endif
/*
* Data Abort Model
* ================
*
* We have the following to choose from:
* arm6 - ARM6 style
* arm7 - ARM7 style
* v4_early - ARMv4 without Thumb early abort handler
* v4t_late - ARMv4 with Thumb late abort handler
* v4t_early - ARMv4 with Thumb early abort handler
* v5ej_early - ARMv5 with Thumb and Java early abort handler
*/
#undef CPU_ABORT_HANDLER
#undef MULTI_ABORT
#if defined(CONFIG_CPU_ARM610)
# ifdef CPU_ABORT_HANDLER
# define MULTI_ABORT 1
# else
# define CPU_ABORT_HANDLER cpu_arm6_data_abort
# endif
#endif
#if defined(CONFIG_CPU_ARM710)
# ifdef CPU_ABORT_HANDLER
# define MULTI_ABORT 1
# else
# define CPU_ABORT_HANDLER cpu_arm7_data_abort
# endif
#endif
#if defined(CONFIG_CPU_ARM720T)
# ifdef CPU_ABORT_HANDLER
# define MULTI_ABORT 1
# else
# define CPU_ABORT_HANDLER v4t_late_abort
# endif
#endif
#if defined(CONFIG_CPU_SA110) || defined(CONFIG_CPU_SA1100)
# ifdef CPU_ABORT_HANDLER
# define MULTI_ABORT 1
# else
# define CPU_ABORT_HANDLER v4_early_abort
# endif
#endif
#if defined(CONFIG_CPU_ARM920T) || defined(CONFIG_CPU_ARM922T) || \
defined(CONFIG_CPU_ARM1020) || defined(CONFIG_CPU_XSCALE)
# ifdef CPU_ABORT_HANDLER
# define MULTI_ABORT 1
# else
# define CPU_ABORT_HANDLER v4t_early_abort
# endif
#endif
#if defined(CONFIG_CPU_ARM926T)
# ifdef CPU_ABORT_HANDLER
# define MULTI_ABORT 1
# else
# define CPU_ABORT_HANDLER v5ej_early_abort
# endif
#endif
#ifndef CPU_ABORT_HANDLER
#error Unknown data abort handler type
#endif
#endif
include/asm-arm/proc-fns.h
View file @ a2946a36
......@@ -28,7 +28,6 @@
/*
* CPU_NAME - the prefix for CPU related functions
* CPU_ABRT - the prefix for the CPU abort decoding function
* MMU_ARCH - the prefix for copy_user_page/clear_user_page
*/
......@@ -40,7 +39,6 @@
# define MULTI_CPU
# else
# define CPU_NAME cpu_arm6
# define CPU_ABRT cpu_arm6
# define MMU_ARCH armv3
# endif
# endif
......@@ -50,7 +48,6 @@
# define MULTI_CPU
# else
# define CPU_NAME cpu_arm7
# define CPU_ABRT cpu_arm7
# define MMU_ARCH armv3
# endif
# endif
......@@ -60,7 +57,6 @@
# define MULTI_CPU
# else
# define CPU_NAME cpu_arm720
# define CPU_ABRT armv4t_late
# define MMU_ARCH armv4
# endif
# endif
......@@ -70,7 +66,6 @@
# define MULTI_CPU
# else
# define CPU_NAME cpu_arm920
# define CPU_ABRT armv4t_early
# define MMU_ARCH armv4
# endif
# endif
......@@ -80,7 +75,6 @@
# define MULTI_CPU
# else
# define CPU_NAME cpu_arm922
# define CPU_ABRT armv4t_early
# define MMU_ARCH armv4
# endif
# endif
......@@ -90,7 +84,6 @@
# define MULTI_CPU
# else
# define CPU_NAME cpu_arm926
# define CPU_ABRT armv5ej_early
# define MMU_ARCH armv4
# endif
# endif
......@@ -100,7 +93,6 @@
# define MULTI_CPU
# else
# define CPU_NAME cpu_sa110
# define CPU_ABRT armv4_early
# define MMU_ARCH armv4
# endif
# endif
......@@ -110,7 +102,6 @@
# define MULTI_CPU
# else
# define CPU_NAME cpu_sa1100
# define CPU_ABRT armv4_early
# define MMU_ARCH armv4_mc
# endif
# endif
......@@ -120,7 +111,6 @@
# define MULTI_CPU
# else
# define CPU_NAME cpu_arm1020
# define CPU_ABRT armv4t_early
# define MMU_ARCH armv4
# endif
# endif
......@@ -130,7 +120,6 @@
# define MULTI_CPU
# else
# define CPU_NAME cpu_xscale
# define CPU_ABRT armv4t_early
# define MMU_ARCH armv5te
# endif
# endif
......
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