[PATCH] ppc32: rework l2 cache code

This patch removes the code that tweaked the L1 cache when setting
up the L2 one. That was added a while ago in the intend of making
things more robust but ended up breaking earlier 750 CPU setup.

Also fix some crap in the L1 cache code that is only used for the
powermac sleep at this point.

arch/ppc/kernel/l2cr.S

@@ -130,11 +130,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
 	mtspr	HID0,r4			/* Disable DPM */
 	sync
 
-	/* Flush & disable L1 */
-	mr	r5,r3
-	bl	__flush_disable_L1
-	mr	r3,r5
-
 	/* Get the current enable bit of the L2CR into r4 */
 	mfspr	r4,L2CR
 
@@ -236,7 +231,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450)
 	sync
 
 4:
-	bl	__inval_enable_L1
 
 	/* Restore HID0[DPM] to whatever it was before */
 	sync
@@ -394,11 +388,10 @@ BEGIN_FTR_SECTION
 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
  	sync
 
-	/* Load counter to 0x1000 cache lines (128k) and
+	/* Load counter to 0x4000 cache lines (512k) and
 	 * load cache with datas
 	 */
-	lis	r3,0x0002
-//	li	r3,0x1000	/* 128kB / 32B */
+	li	r3,0x4000	/* 512kB / 32B */
 	mtctr	r3
 	li	r3, 0
 1:
@@ -409,8 +402,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
 	sync
 
 	/* Now flush those cache lines */
-	lis	r3,0x0002
-//	li	r3,0x1000	/* 128kB / 32B */
+	li	r3,0x4000	/* 512kB / 32B */
 	mtctr	r3
 	li	r3, 0
 1: