MIPS: Get rid of BCM1250_M3_WAR

BCM1250_M3_WAR is depending on CONFIG_CONFIG_SB1_PASS_2_WORKAROUNDS.
So using this option directly lets and remove define.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

arch/mips/include/asm/mach-cavium-octeon/war.h

@@ -9,8 +9,6 @@
 #ifndef __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
 #define __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
 
-#define BCM1250_M3_WAR			0
-
 #define CAVIUM_OCTEON_DCACHE_PREFETCH_WAR	\
 	OCTEON_IS_MODEL(OCTEON_CN6XXX)
 

arch/mips/include/asm/mach-generic/war.h

@@ -8,6 +8,4 @@
 #ifndef __ASM_MACH_GENERIC_WAR_H
 #define __ASM_MACH_GENERIC_WAR_H
 
-#define BCM1250_M3_WAR			0
-
 #endif /* __ASM_MACH_GENERIC_WAR_H */

arch/mips/include/asm/mach-ip22/war.h

@@ -8,6 +8,4 @@
 #ifndef __ASM_MIPS_MACH_IP22_WAR_H
 #define __ASM_MIPS_MACH_IP22_WAR_H
 
-#define BCM1250_M3_WAR			0
-
 #endif /* __ASM_MIPS_MACH_IP22_WAR_H */

arch/mips/include/asm/mach-ip27/war.h

@@ -8,6 +8,4 @@
 #ifndef __ASM_MIPS_MACH_IP27_WAR_H
 #define __ASM_MIPS_MACH_IP27_WAR_H
 
-#define BCM1250_M3_WAR			0
-
 #endif /* __ASM_MIPS_MACH_IP27_WAR_H */

arch/mips/include/asm/mach-ip28/war.h

@@ -8,6 +8,4 @@
 #ifndef __ASM_MIPS_MACH_IP28_WAR_H
 #define __ASM_MIPS_MACH_IP28_WAR_H
 
-#define BCM1250_M3_WAR			0
-
 #endif /* __ASM_MIPS_MACH_IP28_WAR_H */

arch/mips/include/asm/mach-ip30/war.h

@@ -5,6 +5,4 @@
 #ifndef __ASM_MIPS_MACH_IP30_WAR_H
 #define __ASM_MIPS_MACH_IP30_WAR_H
 
-#define BCM1250_M3_WAR			0
-
 #endif /* __ASM_MIPS_MACH_IP30_WAR_H */

arch/mips/include/asm/mach-ip32/war.h

@@ -8,6 +8,4 @@
 #ifndef __ASM_MIPS_MACH_IP32_WAR_H
 #define __ASM_MIPS_MACH_IP32_WAR_H
 
-#define BCM1250_M3_WAR			0
-
 #endif /* __ASM_MIPS_MACH_IP32_WAR_H */

arch/mips/include/asm/mach-malta/war.h

@@ -8,6 +8,4 @@
 #ifndef __ASM_MIPS_MACH_MIPS_WAR_H
 #define __ASM_MIPS_MACH_MIPS_WAR_H
 
-#define BCM1250_M3_WAR			0
-
 #endif /* __ASM_MIPS_MACH_MIPS_WAR_H */

arch/mips/include/asm/mach-rc32434/war.h

@@ -8,6 +8,4 @@
 #ifndef __ASM_MIPS_MACH_MIPS_WAR_H
 #define __ASM_MIPS_MACH_MIPS_WAR_H
 
-#define BCM1250_M3_WAR			0
-
 #endif /* __ASM_MIPS_MACH_MIPS_WAR_H */

arch/mips/include/asm/mach-rm/war.h

@@ -8,6 +8,4 @@
 #ifndef __ASM_MIPS_MACH_RM_WAR_H
 #define __ASM_MIPS_MACH_RM_WAR_H
 
-#define BCM1250_M3_WAR			0
-
 #endif /* __ASM_MIPS_MACH_RM_WAR_H */

arch/mips/include/asm/mach-sibyte/war.h

@@ -8,18 +8,4 @@
 #ifndef __ASM_MIPS_MACH_SIBYTE_WAR_H
 #define __ASM_MIPS_MACH_SIBYTE_WAR_H
 
-#if defined(CONFIG_SB1_PASS_2_WORKAROUNDS)
-
-#ifndef __ASSEMBLY__
-extern int sb1250_m3_workaround_needed(void);
-#endif
-
-#define BCM1250_M3_WAR	sb1250_m3_workaround_needed()
-
-#else
-
-#define BCM1250_M3_WAR	0
-
-#endif
-
 #endif /* __ASM_MIPS_MACH_SIBYTE_WAR_H */

arch/mips/include/asm/mach-tx49xx/war.h

@@ -8,6 +8,4 @@
 #ifndef __ASM_MIPS_MACH_TX49XX_WAR_H
 #define __ASM_MIPS_MACH_TX49XX_WAR_H
 
-#define BCM1250_M3_WAR			0
-
 #endif /* __ASM_MIPS_MACH_TX49XX_WAR_H */

arch/mips/include/asm/war.h

@@ -72,18 +72,4 @@
 #define DADDI_WAR 0
 #endif
 
-/*
- * Workaround for the Sibyte M3 errata the text of which can be found at
- *
- *   http://sibyte.broadcom.com/hw/bcm1250/docs/pass2errata.txt
- *
- * This will enable the use of a special TLB refill handler which does a
- * consistency check on the information in c0_badvaddr and c0_entryhi and
- * will just return and take the exception again if the information was
- * found to be inconsistent.
- */
-#ifndef BCM1250_M3_WAR
-#error Check setting of BCM1250_M3_WAR for your platform
-#endif
-
 #endif /* _ASM_WAR_H */

arch/mips/mm/tlbex.c

@@ -83,9 +83,13 @@ static inline int r4k_250MHZhwbug(void)
 	return 0;
 }
 
+extern int sb1250_m3_workaround_needed(void);
+
 static inline int __maybe_unused bcm1250_m3_war(void)
 {
-	return BCM1250_M3_WAR;
+	if (IS_ENABLED(CONFIG_SB1_PASS_2_WORKAROUNDS))
+		return sb1250_m3_workaround_needed();
+	return 0;
 }
 
 static inline int __maybe_unused r10000_llsc_war(void)