[PATCH] ppc __iomem annotations - gg2

gg2_pci_config_base is an iomem pointer.
Signed-off-by: Al Viro <viro@parcelfarce.linux.theplanet.co.uk>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

arch/ppc/platforms/chrp_pci.c

@@ -23,7 +23,7 @@
 #include <asm/open_pic.h>
 
 /* LongTrail */
-unsigned long gg2_pci_config_base;
+void __iomem *gg2_pci_config_base;
 
 /*
  * The VLSI Golden Gate II has only 512K of PCI configuration space, so we
@@ -253,9 +253,10 @@ chrp_find_bridges(void)
 			   || strncmp(model, "Motorola, Grackle", 17) == 0) {
 			setup_grackle(hose);
 		} else if (is_longtrail) {
+			void __iomem *p = ioremap(GG2_PCI_CONFIG_BASE, 0x80000);
 			hose->ops = &gg2_pci_ops;
-			hose->cfg_data = ioremap(GG2_PCI_CONFIG_BASE, 0x80000);
-			gg2_pci_config_base = (unsigned long) hose->cfg_data;
+			hose->cfg_data = p;
+			gg2_pci_config_base = p;
 		} else {
 			printk("No methods for %s (model %s), using RTAS\n",
 			       dev->full_name, model);

arch/ppc/platforms/chrp_setup.c

@@ -118,13 +118,12 @@ chrp_show_cpuinfo(struct seq_file *m)
 	if (!strncmp(model, "IBM,LongTrail", 13)) {
 		/* VLSI VAS96011/12 `Golden Gate 2' */
 		/* Memory banks */
-		sdramen = (in_le32((unsigned *)(gg2_pci_config_base+
-						GG2_PCI_DRAM_CTRL))
+		sdramen = (in_le32(gg2_pci_config_base + GG2_PCI_DRAM_CTRL)
 			   >>31) & 1;
 		for (i = 0; i < (sdramen ? 4 : 6); i++) {
-			t = in_le32((unsigned *)(gg2_pci_config_base+
+			t = in_le32(gg2_pci_config_base+
 						 GG2_PCI_DRAM_BANK0+
-						 i*4));
+						 i*4);
 			if (!(t & 1))
 				continue;
 			switch ((t>>8) & 0x1f) {
@@ -154,7 +153,7 @@ chrp_show_cpuinfo(struct seq_file *m)
 				   gg2_memtypes[sdramen ? 1 : ((t>>1) & 3)]);
 		}
 		/* L2 cache */
-		t = in_le32((unsigned *)(gg2_pci_config_base+GG2_PCI_CC_CTRL));
+		t = in_le32(gg2_pci_config_base+GG2_PCI_CC_CTRL);
 		seq_printf(m, "board l2\t: %s %s (%s)\n",
 			   gg2_cachesizes[(t>>7) & 3],
 			   gg2_cachetypes[(t>>2) & 3],

include/asm-ppc/gg2.h

@@ -34,7 +34,7 @@
      *  GG2 specific PCI Registers
      */
 
-extern unsigned long gg2_pci_config_base;	/* kernel virtual address */
+extern void __iomem *gg2_pci_config_base;	/* kernel virtual address */
 
 #define GG2_PCI_BUSNO		0x40	/* Bus number */
 #define GG2_PCI_SUBBUSNO	0x41	/* Subordinate bus number */