Commit b849aaa4 authored by Christian König's avatar Christian König Committed by Alex Deucher

drm/amdgpu: also reroute VMC and UMD to IH ring 1 on Vega 20

Same patch we alredy did for Vega10. Just re-route page faults to a separate
ring to avoid drowning in interrupts.
Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 516bc3d8
...@@ -33,6 +33,9 @@ ...@@ -33,6 +33,9 @@
#include "sdma0/sdma0_4_0_offset.h" #include "sdma0/sdma0_4_0_offset.h"
#include "nbio/nbio_7_4_offset.h" #include "nbio/nbio_7_4_offset.h"
#include "oss/osssys_4_0_offset.h"
#include "oss/osssys_4_0_sh_mask.h"
MODULE_FIRMWARE("amdgpu/vega20_sos.bin"); MODULE_FIRMWARE("amdgpu/vega20_sos.bin");
MODULE_FIRMWARE("amdgpu/vega20_asd.bin"); MODULE_FIRMWARE("amdgpu/vega20_asd.bin");
MODULE_FIRMWARE("amdgpu/vega20_ta.bin"); MODULE_FIRMWARE("amdgpu/vega20_ta.bin");
...@@ -217,6 +220,37 @@ static int psp_v11_0_bootloader_load_sos(struct psp_context *psp) ...@@ -217,6 +220,37 @@ static int psp_v11_0_bootloader_load_sos(struct psp_context *psp)
return ret; return ret;
} }
static void psp_v11_0_reroute_ih(struct psp_context *psp)
{
struct amdgpu_device *adev = psp->adev;
uint32_t tmp;
/* Change IH ring for VMC */
tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);
tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
mdelay(20);
psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
0x80000000, 0x8000FFFF, false);
/* Change IH ring for UMC */
tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
mdelay(20);
psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
0x80000000, 0x8000FFFF, false);
}
static int psp_v11_0_ring_init(struct psp_context *psp, static int psp_v11_0_ring_init(struct psp_context *psp,
enum psp_ring_type ring_type) enum psp_ring_type ring_type)
{ {
...@@ -224,6 +258,8 @@ static int psp_v11_0_ring_init(struct psp_context *psp, ...@@ -224,6 +258,8 @@ static int psp_v11_0_ring_init(struct psp_context *psp,
struct psp_ring *ring; struct psp_ring *ring;
struct amdgpu_device *adev = psp->adev; struct amdgpu_device *adev = psp->adev;
psp_v11_0_reroute_ih(psp);
ring = &psp->km_ring; ring = &psp->km_ring;
ring->ring_type = ring_type; ring->ring_type = ring_type;
......
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