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Commit bc33285e authored by David S. Miller's avatar David S. Miller
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[TG3]: Rewrite dma_rwctrl settings to handle PCIX/PCIE.

parent 8fd78857
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Showing with 58 additions and 82 deletions
drivers/net/tg3.c
View file @ bc33285e
......@@ -7709,50 +7709,9 @@ static int __devinit tg3_test_dma(struct tg3 *tp)
goto out_nofree;
}
if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) == 0) {
tp->dma_rwctrl =
(0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
(0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT) |
(0x7 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
(0x7 << DMA_RWCTRL_READ_WATER_SHIFT) |
(0x0f << DMA_RWCTRL_MIN_DMA_SHIFT);
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
tp->dma_rwctrl &= ~(DMA_RWCTRL_MIN_DMA
<< DMA_RWCTRL_MIN_DMA_SHIFT);
} else {
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
tp->dma_rwctrl =
(0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
(0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT) |
(0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
(0x7 << DMA_RWCTRL_READ_WATER_SHIFT) |
(0x00 << DMA_RWCTRL_MIN_DMA_SHIFT);
else
tp->dma_rwctrl =
(0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
(0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT) |
(0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
(0x3 << DMA_RWCTRL_READ_WATER_SHIFT) |
(0x0f << DMA_RWCTRL_MIN_DMA_SHIFT);
/* Wheee, some more chip bugs... */
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
(0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
if (ccval == 0x6 || ccval == 0x7)
tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
}
}
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
tp->dma_rwctrl &= ~(DMA_RWCTRL_MIN_DMA
<< DMA_RWCTRL_MIN_DMA_SHIFT);
/* We don't do this on x86 because it seems to hurt performace.
* It does help things on other platforms though.
*/
#ifndef CONFIG_X86
{
u8 byte;
......@@ -7764,55 +7723,63 @@ static int __devinit tg3_test_dma(struct tg3 *tp)
else
cacheline_size = (int) byte * 4;
tp->dma_rwctrl &= ~(DMA_RWCTRL_READ_BNDRY_MASK |
DMA_RWCTRL_WRITE_BNDRY_MASK);
switch (cacheline_size) {
case 16:
tp->dma_rwctrl |=
(DMA_RWCTRL_READ_BNDRY_16 |
DMA_RWCTRL_WRITE_BNDRY_16);
break;
case 32:
tp->dma_rwctrl |=
(DMA_RWCTRL_READ_BNDRY_32 |
DMA_RWCTRL_WRITE_BNDRY_32);
break;
case 64:
tp->dma_rwctrl |=
(DMA_RWCTRL_READ_BNDRY_64 |
DMA_RWCTRL_WRITE_BNDRY_64);
break;
case 128:
tp->dma_rwctrl |=
(DMA_RWCTRL_READ_BNDRY_128 |
DMA_RWCTRL_WRITE_BNDRY_128);
break;
if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
tp->dma_rwctrl |=
DMA_RWCTRL_WRITE_BNDRY_384_PCIX;
break;
} else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
tp->dma_rwctrl &=
~(DMA_RWCTRL_PCI_WRITE_CMD);
tp->dma_rwctrl |=
DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
break;
}
/* fallthrough */
case 256:
tp->dma_rwctrl |=
(DMA_RWCTRL_READ_BNDRY_256 |
DMA_RWCTRL_WRITE_BNDRY_256);
break;
case 512:
tp->dma_rwctrl |=
(DMA_RWCTRL_READ_BNDRY_512 |
DMA_RWCTRL_WRITE_BNDRY_512);
break;
case 1024:
tp->dma_rwctrl |=
(DMA_RWCTRL_READ_BNDRY_1024 |
DMA_RWCTRL_WRITE_BNDRY_1024);
break;
if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
tp->dma_rwctrl |=
DMA_RWCTRL_WRITE_BNDRY_256;
else if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
tp->dma_rwctrl |=
DMA_RWCTRL_WRITE_BNDRY_256_PCIX;
};
}
#endif
if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
tp->dma_rwctrl |= 0x001f0000;
} else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
tp->dma_rwctrl |= 0x003f0000;
else
tp->dma_rwctrl |= 0x003f000f;
} else {
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
if (ccval == 0x6 || ccval == 0x7)
tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
/* Set bit 23 to renable PCIX hw bug fix */
tp->dma_rwctrl |= 0x009f0000;
} else {
tp->dma_rwctrl |= 0x001b000f;
}
}
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
tp->dma_rwctrl &= 0xfffffff0;
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
/* Remove this if it causes problems for some boards. */
......
drivers/net/tg3.h
View file @ bc33285e
......@@ -149,8 +149,11 @@
#define DMA_RWCTRL_READ_BNDRY_MASK 0x00000700
#define DMA_RWCTRL_READ_BNDRY_DISAB 0x00000000
#define DMA_RWCTRL_READ_BNDRY_16 0x00000100
#define DMA_RWCTRL_READ_BNDRY_128_PCIX 0x00000100
#define DMA_RWCTRL_READ_BNDRY_32 0x00000200
#define DMA_RWCTRL_READ_BNDRY_256_PCIX 0x00000200
#define DMA_RWCTRL_READ_BNDRY_64 0x00000300
#define DMA_RWCTRL_READ_BNDRY_384_PCIX 0x00000300
#define DMA_RWCTRL_READ_BNDRY_128 0x00000400
#define DMA_RWCTRL_READ_BNDRY_256 0x00000500
#define DMA_RWCTRL_READ_BNDRY_512 0x00000600
......@@ -158,8 +161,11 @@
#define DMA_RWCTRL_WRITE_BNDRY_MASK 0x00003800
#define DMA_RWCTRL_WRITE_BNDRY_DISAB 0x00000000
#define DMA_RWCTRL_WRITE_BNDRY_16 0x00000800
#define DMA_RWCTRL_WRITE_BNDRY_128_PCIX 0x00000800
#define DMA_RWCTRL_WRITE_BNDRY_32 0x00001000
#define DMA_RWCTRL_WRITE_BNDRY_256_PCIX 0x00001000
#define DMA_RWCTRL_WRITE_BNDRY_64 0x00001800
#define DMA_RWCTRL_WRITE_BNDRY_384_PCIX 0x00001800
#define DMA_RWCTRL_WRITE_BNDRY_128 0x00002000
#define DMA_RWCTRL_WRITE_BNDRY_256 0x00002800
#define DMA_RWCTRL_WRITE_BNDRY_512 0x00003000
......@@ -175,6 +181,9 @@
#define DMA_RWCTRL_PCI_READ_CMD_SHIFT 24
#define DMA_RWCTRL_PCI_WRITE_CMD 0xf0000000
#define DMA_RWCTRL_PCI_WRITE_CMD_SHIFT 28
#define DMA_RWCTRL_WRITE_BNDRY_64_PCIE 0x10000000
#define DMA_RWCTRL_WRITE_BNDRY_128_PCIE 0x30000000
#define DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE 0x70000000
#define TG3PCI_PCISTATE 0x00000070
#define PCISTATE_FORCE_RESET 0x00000001
#define PCISTATE_INT_NOT_ACTIVE 0x00000002
......
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