Commit bcb86e0a authored by Paul Mundt's avatar Paul Mundt

Merge branches 'sh/wdt' and 'sh/rsk-updates' into sh-latest

Conflicts:
	arch/sh/Kconfig
Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
...@@ -295,6 +295,13 @@ config CPU_SUBTYPE_SH7264 ...@@ -295,6 +295,13 @@ config CPU_SUBTYPE_SH7264
select SYS_SUPPORTS_CMT select SYS_SUPPORTS_CMT
select SYS_SUPPORTS_MTU2 select SYS_SUPPORTS_MTU2
config CPU_SUBTYPE_SH7269
bool "Support SH7269 processor"
select CPU_SH2A
select CPU_HAS_FPU
select SYS_SUPPORTS_CMT
select SYS_SUPPORTS_MTU2
config CPU_SUBTYPE_MXG config CPU_SUBTYPE_MXG
bool "Support MX-G processor" bool "Support MX-G processor"
select CPU_SH2A select CPU_SH2A
...@@ -602,7 +609,8 @@ config SH_CLK_CPG_LEGACY ...@@ -602,7 +609,8 @@ config SH_CLK_CPG_LEGACY
depends on SH_CLK_CPG depends on SH_CLK_CPG
def_bool y if !CPU_SUBTYPE_SH7785 && !ARCH_SHMOBILE && \ def_bool y if !CPU_SUBTYPE_SH7785 && !ARCH_SHMOBILE && \
!CPU_SHX3 && !CPU_SUBTYPE_SH7757 && \ !CPU_SHX3 && !CPU_SUBTYPE_SH7757 && \
!CPU_SUBTYPE_SH7734 && !CPU_SUBTYPE_SH7264 !CPU_SUBTYPE_SH7734 && !CPU_SUBTYPE_SH7264 && \
!CPU_SUBTYPE_SH7269
source "kernel/time/Kconfig" source "kernel/time/Kconfig"
......
...@@ -133,7 +133,8 @@ config SH_RTS7751R2D ...@@ -133,7 +133,8 @@ config SH_RTS7751R2D
config SH_RSK config SH_RSK
bool "Renesas Starter Kit" bool "Renesas Starter Kit"
depends on CPU_SUBTYPE_SH7201 || CPU_SUBTYPE_SH7203 || CPU_SUBTYPE_SH7264 depends on CPU_SUBTYPE_SH7201 || CPU_SUBTYPE_SH7203 || \
CPU_SUBTYPE_SH7264 || CPU_SUBTYPE_SH7269
help help
Select this option if configuring for any of the RSK+ MCU Select this option if configuring for any of the RSK+ MCU
evaluation platforms. evaluation platforms.
......
...@@ -18,6 +18,11 @@ config SH_RSK7264 ...@@ -18,6 +18,11 @@ config SH_RSK7264
select ARCH_REQUIRE_GPIOLIB select ARCH_REQUIRE_GPIOLIB
depends on CPU_SUBTYPE_SH7264 depends on CPU_SUBTYPE_SH7264
config SH_RSK7269
bool "RSK2+SH7269"
select ARCH_REQUIRE_GPIOLIB
depends on CPU_SUBTYPE_SH7269
endchoice endchoice
endif endif
obj-y := setup.o obj-y := setup.o
obj-$(CONFIG_SH_RSK7203) += devices-rsk7203.o obj-$(CONFIG_SH_RSK7203) += devices-rsk7203.o
obj-$(CONFIG_SH_RSK7264) += devices-rsk7264.o obj-$(CONFIG_SH_RSK7264) += devices-rsk7264.o
obj-$(CONFIG_SH_RSK7269) += devices-rsk7269.o
/*
* RSK+SH7269 Support
*
* Copyright (C) 2012 Renesas Electronics Europe Ltd
* Copyright (C) 2012 Phil Edworthy
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/init.h>
#include <linux/types.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/input.h>
#include <linux/smsc911x.h>
#include <linux/gpio.h>
#include <asm/machvec.h>
#include <asm/io.h>
static struct smsc911x_platform_config smsc911x_config = {
.phy_interface = PHY_INTERFACE_MODE_MII,
.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
.flags = SMSC911X_USE_16BIT | SMSC911X_SWAP_FIFO,
};
static struct resource smsc911x_resources[] = {
[0] = {
.start = 0x24000000,
.end = 0x240000ff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = 85,
.end = 85,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device smsc911x_device = {
.name = "smsc911x",
.id = -1,
.num_resources = ARRAY_SIZE(smsc911x_resources),
.resource = smsc911x_resources,
.dev = {
.platform_data = &smsc911x_config,
},
};
static struct platform_device *rsk7269_devices[] __initdata = {
&smsc911x_device,
};
static int __init rsk7269_devices_setup(void)
{
return platform_add_devices(rsk7269_devices,
ARRAY_SIZE(rsk7269_devices));
}
device_initcall(rsk7269_devices_setup);
CONFIG_LOG_BUF_SHIFT=14
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_EMBEDDED=y
# CONFIG_VM_EVENT_COUNTERS is not set
CONFIG_SLAB=y
# CONFIG_LBDAF is not set
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_SWAP_IO_SPACE=y
CONFIG_CPU_SUBTYPE_SH7269=y
CONFIG_MEMORY_START=0x0c000000
CONFIG_MEMORY_SIZE=0x02000000
CONFIG_FLATMEM_MANUAL=y
CONFIG_CPU_BIG_ENDIAN=y
CONFIG_SH_RSK=y
# CONFIG_SH_TIMER_MTU2 is not set
CONFIG_SH_PCLK_FREQ=66700000
CONFIG_BINFMT_FLAT=y
CONFIG_NET=y
CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
# CONFIG_INET_DIAG is not set
# CONFIG_IPV6 is not set
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
# CONFIG_FW_LOADER is not set
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_NETDEVICES=y
CONFIG_SMSC911X=y
CONFIG_SMSC_PHY=y
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
CONFIG_SERIAL_SH_SCI=y
CONFIG_SERIAL_SH_SCI_NR_UARTS=8
CONFIG_SERIAL_SH_SCI_CONSOLE=y
# CONFIG_HWMON is not set
CONFIG_USB=y
CONFIG_USB_DEBUG=y
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
# CONFIG_USB_DEVICE_CLASS is not set
CONFIG_USB_R8A66597_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_USB_STORAGE_DEBUG=y
CONFIG_USB_LIBUSUAL=y
CONFIG_EXT2_FS=y
CONFIG_EXT3_FS=y
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
CONFIG_VFAT_FS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
CONFIG_ROOT_NFS=y
CONFIG_PARTITION_ADVANCED=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_SYSCTL_SYSCALL_CHECK=y
# CONFIG_FTRACE is not set
...@@ -18,7 +18,8 @@ enum cpu_type { ...@@ -18,7 +18,8 @@ enum cpu_type {
CPU_SH7619, CPU_SH7619,
/* SH-2A types */ /* SH-2A types */
CPU_SH7201, CPU_SH7203, CPU_SH7206, CPU_SH7263, CPU_SH7264, CPU_MXG, CPU_SH7201, CPU_SH7203, CPU_SH7206, CPU_SH7263, CPU_SH7264, CPU_SH7269,
CPU_MXG,
/* SH-3 types */ /* SH-3 types */
CPU_SH7705, CPU_SH7706, CPU_SH7707, CPU_SH7705, CPU_SH7706, CPU_SH7707,
......
#ifndef __ASM_SH7269_H__
#define __ASM_SH7269_H__
enum {
/* Port A */
GPIO_PA1, GPIO_PA0,
/* Port B */
GPIO_PB22, GPIO_PB21, GPIO_PB20,
GPIO_PB19, GPIO_PB18, GPIO_PB17, GPIO_PB16,
GPIO_PB15, GPIO_PB14, GPIO_PB13, GPIO_PB12,
GPIO_PB11, GPIO_PB10, GPIO_PB9, GPIO_PB8,
GPIO_PB7, GPIO_PB6, GPIO_PB5, GPIO_PB4,
GPIO_PB3, GPIO_PB2, GPIO_PB1,
/* Port C */
GPIO_PC8,
GPIO_PC7, GPIO_PC6, GPIO_PC5, GPIO_PC4,
GPIO_PC3, GPIO_PC2, GPIO_PC1, GPIO_PC0,
/* Port D */
GPIO_PD15, GPIO_PD14, GPIO_PD13, GPIO_PD12,
GPIO_PD11, GPIO_PD10, GPIO_PD9, GPIO_PD8,
GPIO_PD7, GPIO_PD6, GPIO_PD5, GPIO_PD4,
GPIO_PD3, GPIO_PD2, GPIO_PD1, GPIO_PD0,
/* Port E */
GPIO_PE7, GPIO_PE6, GPIO_PE5, GPIO_PE4,
GPIO_PE3, GPIO_PE2, GPIO_PE1, GPIO_PE0,
/* Port F */
GPIO_PF23, GPIO_PF22, GPIO_PF21, GPIO_PF20,
GPIO_PF19, GPIO_PF18, GPIO_PF17, GPIO_PF16,
GPIO_PF15, GPIO_PF14, GPIO_PF13, GPIO_PF12,
GPIO_PF11, GPIO_PF10, GPIO_PF9, GPIO_PF8,
GPIO_PF7, GPIO_PF6, GPIO_PF5, GPIO_PF4,
GPIO_PF3, GPIO_PF2, GPIO_PF1, GPIO_PF0,
/* Port G */
GPIO_PG27, GPIO_PG26, GPIO_PG25, GPIO_PG24,
GPIO_PG23, GPIO_PG22, GPIO_PG21, GPIO_PG20,
GPIO_PG19, GPIO_PG18, GPIO_PG17, GPIO_PG16,
GPIO_PG15, GPIO_PG14, GPIO_PG13, GPIO_PG12,
GPIO_PG11, GPIO_PG10, GPIO_PG9, GPIO_PG8,
GPIO_PG7, GPIO_PG6, GPIO_PG5, GPIO_PG4,
GPIO_PG3, GPIO_PG2, GPIO_PG1, GPIO_PG0,
/* Port H */
GPIO_PH7, GPIO_PH6, GPIO_PH5, GPIO_PH4,
GPIO_PH3, GPIO_PH2, GPIO_PH1, GPIO_PH0,
/* Port I - not on device */
/* Port J */
GPIO_PJ31, GPIO_PJ30, GPIO_PJ29, GPIO_PJ28,
GPIO_PJ27, GPIO_PJ26, GPIO_PJ25, GPIO_PJ24,
GPIO_PJ23, GPIO_PJ22, GPIO_PJ21, GPIO_PJ20,
GPIO_PJ19, GPIO_PJ18, GPIO_PJ17, GPIO_PJ16,
GPIO_PJ15, GPIO_PJ14, GPIO_PJ13, GPIO_PJ12,
GPIO_PJ11, GPIO_PJ10, GPIO_PJ9, GPIO_PJ8,
GPIO_PJ7, GPIO_PJ6, GPIO_PJ5, GPIO_PJ4,
GPIO_PJ3, GPIO_PJ2, GPIO_PJ1, GPIO_PJ0,
/* INTC: IRQ and PINT */
GPIO_FN_IRQ7_PG, GPIO_FN_IRQ6_PG, GPIO_FN_IRQ5_PG, GPIO_FN_IRQ4_PG,
GPIO_FN_IRQ3_PG, GPIO_FN_IRQ2_PG, GPIO_FN_IRQ1_PG, GPIO_FN_IRQ0_PG,
GPIO_FN_IRQ7_PF, GPIO_FN_IRQ6_PF, GPIO_FN_IRQ5_PF, GPIO_FN_IRQ4_PF,
GPIO_FN_IRQ3_PJ, GPIO_FN_IRQ2_PJ, GPIO_FN_IRQ1_PJ, GPIO_FN_IRQ0_PJ,
GPIO_FN_IRQ1_PC, GPIO_FN_IRQ0_PC,
GPIO_FN_PINT7_PG, GPIO_FN_PINT6_PG, GPIO_FN_PINT5_PG, GPIO_FN_PINT4_PG,
GPIO_FN_PINT3_PG, GPIO_FN_PINT2_PG, GPIO_FN_PINT1_PG, GPIO_FN_PINT0_PG,
GPIO_FN_PINT7_PH, GPIO_FN_PINT6_PH, GPIO_FN_PINT5_PH, GPIO_FN_PINT4_PH,
GPIO_FN_PINT3_PH, GPIO_FN_PINT2_PH, GPIO_FN_PINT1_PH, GPIO_FN_PINT0_PH,
GPIO_FN_PINT7_PJ, GPIO_FN_PINT6_PJ, GPIO_FN_PINT5_PJ, GPIO_FN_PINT4_PJ,
GPIO_FN_PINT3_PJ, GPIO_FN_PINT2_PJ, GPIO_FN_PINT1_PJ, GPIO_FN_PINT0_PJ,
/* WDT */
GPIO_FN_WDTOVF,
/* CAN */
GPIO_FN_CTX1, GPIO_FN_CRX1, GPIO_FN_CTX0, GPIO_FN_CTX0_CTX1,
GPIO_FN_CRX0, GPIO_FN_CRX0_CRX1, GPIO_FN_CRX0_CRX1_CRX2,
/* DMAC */
GPIO_FN_TEND0, GPIO_FN_DACK0, GPIO_FN_DREQ0,
GPIO_FN_TEND1, GPIO_FN_DACK1, GPIO_FN_DREQ1,
/* ADC */
GPIO_FN_ADTRG,
/* BSC */
GPIO_FN_A25, GPIO_FN_A24,
GPIO_FN_A23, GPIO_FN_A22, GPIO_FN_A21, GPIO_FN_A20,
GPIO_FN_A19, GPIO_FN_A18, GPIO_FN_A17, GPIO_FN_A16,
GPIO_FN_A15, GPIO_FN_A14, GPIO_FN_A13, GPIO_FN_A12,
GPIO_FN_A11, GPIO_FN_A10, GPIO_FN_A9, GPIO_FN_A8,
GPIO_FN_A7, GPIO_FN_A6, GPIO_FN_A5, GPIO_FN_A4,
GPIO_FN_A3, GPIO_FN_A2, GPIO_FN_A1, GPIO_FN_A0,
GPIO_FN_D15, GPIO_FN_D14, GPIO_FN_D13, GPIO_FN_D12,
GPIO_FN_D11, GPIO_FN_D10, GPIO_FN_D9, GPIO_FN_D8,
GPIO_FN_D7, GPIO_FN_D6, GPIO_FN_D5, GPIO_FN_D4,
GPIO_FN_D3, GPIO_FN_D2, GPIO_FN_D1, GPIO_FN_D0,
GPIO_FN_BS,
GPIO_FN_CS4, GPIO_FN_CS3, GPIO_FN_CS2, GPIO_FN_CS1, GPIO_FN_CS0,
GPIO_FN_CS5CE1A,
GPIO_FN_CE2A, GPIO_FN_CE2B,
GPIO_FN_RD, GPIO_FN_RDWR,
GPIO_FN_WE3ICIOWRAHDQMUU, GPIO_FN_WE2ICIORDDQMUL,
GPIO_FN_WE1DQMUWE, GPIO_FN_WE0DQML,
GPIO_FN_RAS, GPIO_FN_CAS, GPIO_FN_CKE,
GPIO_FN_WAIT, GPIO_FN_BREQ, GPIO_FN_BACK,
GPIO_FN_IOIS16,
/* TMU */
GPIO_FN_TIOC4D, GPIO_FN_TIOC4C, GPIO_FN_TIOC4B, GPIO_FN_TIOC4A,
GPIO_FN_TIOC3D, GPIO_FN_TIOC3C, GPIO_FN_TIOC3B, GPIO_FN_TIOC3A,
GPIO_FN_TIOC2B, GPIO_FN_TIOC1B, GPIO_FN_TIOC2A, GPIO_FN_TIOC1A,
GPIO_FN_TIOC0D, GPIO_FN_TIOC0C, GPIO_FN_TIOC0B, GPIO_FN_TIOC0A,
GPIO_FN_TCLKD, GPIO_FN_TCLKC, GPIO_FN_TCLKB, GPIO_FN_TCLKA,
/* SSU */
GPIO_FN_SCS0_PD, GPIO_FN_SSO0_PD, GPIO_FN_SSI0_PD, GPIO_FN_SSCK0_PD,
GPIO_FN_SCS0_PF, GPIO_FN_SSO0_PF, GPIO_FN_SSI0_PF, GPIO_FN_SSCK0_PF,
GPIO_FN_SCS1_PD, GPIO_FN_SSO1_PD, GPIO_FN_SSI1_PD, GPIO_FN_SSCK1_PD,
GPIO_FN_SCS1_PF, GPIO_FN_SSO1_PF, GPIO_FN_SSI1_PF, GPIO_FN_SSCK1_PF,
/* SCIF */
GPIO_FN_SCK0, GPIO_FN_RXD0, GPIO_FN_TXD0,
GPIO_FN_SCK1, GPIO_FN_RXD1, GPIO_FN_TXD1, GPIO_FN_RTS1, GPIO_FN_CTS1,
GPIO_FN_SCK2, GPIO_FN_RXD2, GPIO_FN_TXD2,
GPIO_FN_SCK3, GPIO_FN_RXD3, GPIO_FN_TXD3,
GPIO_FN_SCK4, GPIO_FN_RXD4, GPIO_FN_TXD4,
GPIO_FN_SCK5, GPIO_FN_RXD5, GPIO_FN_TXD5, GPIO_FN_RTS5, GPIO_FN_CTS5,
GPIO_FN_SCK6, GPIO_FN_RXD6, GPIO_FN_TXD6,
GPIO_FN_SCK7, GPIO_FN_RXD7, GPIO_FN_TXD7, GPIO_FN_RTS7, GPIO_FN_CTS7,
/* RSPI */
GPIO_FN_MISO0_PJ19, GPIO_FN_MISO0_PB20,
GPIO_FN_MOSI0_PJ18, GPIO_FN_MOSI0_PB19,
GPIO_FN_SSL00_PJ17, GPIO_FN_SSL00_PB18,
GPIO_FN_RSPCK0_PJ16, GPIO_FN_RSPCK0_PB17,
GPIO_FN_RSPCK1, GPIO_FN_MOSI1,
GPIO_FN_MISO1, GPIO_FN_SSL10,
/* IIC3 */
GPIO_FN_SCL0, GPIO_FN_SCL1, GPIO_FN_SCL2,
GPIO_FN_SDA2, GPIO_FN_SDA1, GPIO_FN_SDA0,
/* SSI */
GPIO_FN_SSISCK0, GPIO_FN_SSIWS0, GPIO_FN_SSITXD0, GPIO_FN_SSIRXD0,
GPIO_FN_SSIWS1, GPIO_FN_SSIWS2, GPIO_FN_SSIWS3,
GPIO_FN_SSISCK1, GPIO_FN_SSISCK2, GPIO_FN_SSISCK3,
GPIO_FN_SSIDATA1, GPIO_FN_SSIDATA2, GPIO_FN_SSIDATA3,
GPIO_FN_AUDIO_CLK,
GPIO_FN_AUDIO_XOUT,
/* SIOF */
GPIO_FN_SIOFTXD, GPIO_FN_SIOFRXD, GPIO_FN_SIOFSYNC, GPIO_FN_SIOFSCK,
/* SPDIF */
GPIO_FN_SPDIF_IN,
GPIO_FN_SPDIF_OUT,
/* NANDFMC */ /* NOTE Controller is not available in boot mode 0 */
GPIO_FN_FCE,
GPIO_FN_FRB,
/* VDC */
GPIO_FN_DV_CLK, GPIO_FN_DV_VSYNC, GPIO_FN_DV_HSYNC,
GPIO_FN_DV_DATA23, GPIO_FN_DV_DATA22,
GPIO_FN_DV_DATA21, GPIO_FN_DV_DATA20,
GPIO_FN_DV_DATA19, GPIO_FN_DV_DATA18,
GPIO_FN_DV_DATA17, GPIO_FN_DV_DATA16,
GPIO_FN_DV_DATA15, GPIO_FN_DV_DATA14,
GPIO_FN_DV_DATA13, GPIO_FN_DV_DATA12,
GPIO_FN_DV_DATA11, GPIO_FN_DV_DATA10,
GPIO_FN_DV_DATA9, GPIO_FN_DV_DATA8,
GPIO_FN_DV_DATA7, GPIO_FN_DV_DATA6,
GPIO_FN_DV_DATA5, GPIO_FN_DV_DATA4,
GPIO_FN_DV_DATA3, GPIO_FN_DV_DATA2,
GPIO_FN_DV_DATA1, GPIO_FN_DV_DATA0,
GPIO_FN_LCD_CLK, GPIO_FN_LCD_EXTCLK,
GPIO_FN_LCD_VSYNC, GPIO_FN_LCD_HSYNC, GPIO_FN_LCD_DE,
GPIO_FN_LCD_DATA23, GPIO_FN_LCD_DATA22,
GPIO_FN_LCD_DATA21, GPIO_FN_LCD_DATA20,
GPIO_FN_LCD_DATA19, GPIO_FN_LCD_DATA18,
GPIO_FN_LCD_DATA17, GPIO_FN_LCD_DATA16,
GPIO_FN_LCD_DATA15, GPIO_FN_LCD_DATA14,
GPIO_FN_LCD_DATA13, GPIO_FN_LCD_DATA12,
GPIO_FN_LCD_DATA11, GPIO_FN_LCD_DATA10,
GPIO_FN_LCD_DATA9, GPIO_FN_LCD_DATA8,
GPIO_FN_LCD_DATA7, GPIO_FN_LCD_DATA6,
GPIO_FN_LCD_DATA5, GPIO_FN_LCD_DATA4,
GPIO_FN_LCD_DATA3, GPIO_FN_LCD_DATA2,
GPIO_FN_LCD_DATA1, GPIO_FN_LCD_DATA0,
GPIO_FN_LCD_M_DISP,
};
#endif /* __ASM_SH7269_H__ */
...@@ -7,7 +7,7 @@ ...@@ -7,7 +7,7 @@
static const char *cpu_name[] = { static const char *cpu_name[] = {
[CPU_SH7201] = "SH7201", [CPU_SH7201] = "SH7201",
[CPU_SH7203] = "SH7203", [CPU_SH7263] = "SH7263", [CPU_SH7203] = "SH7203", [CPU_SH7263] = "SH7263",
[CPU_SH7264] = "SH7264", [CPU_SH7264] = "SH7264", [CPU_SH7269] = "SH7269",
[CPU_SH7206] = "SH7206", [CPU_SH7619] = "SH7619", [CPU_SH7206] = "SH7206", [CPU_SH7619] = "SH7619",
[CPU_SH7705] = "SH7705", [CPU_SH7706] = "SH7706", [CPU_SH7705] = "SH7705", [CPU_SH7706] = "SH7706",
[CPU_SH7707] = "SH7707", [CPU_SH7708] = "SH7708", [CPU_SH7707] = "SH7707", [CPU_SH7708] = "SH7708",
......
...@@ -13,10 +13,12 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7203) += setup-sh7203.o clock-sh7203.o ...@@ -13,10 +13,12 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7203) += setup-sh7203.o clock-sh7203.o
obj-$(CONFIG_CPU_SUBTYPE_SH7263) += setup-sh7203.o clock-sh7203.o obj-$(CONFIG_CPU_SUBTYPE_SH7263) += setup-sh7203.o clock-sh7203.o
obj-$(CONFIG_CPU_SUBTYPE_SH7264) += setup-sh7264.o clock-sh7264.o obj-$(CONFIG_CPU_SUBTYPE_SH7264) += setup-sh7264.o clock-sh7264.o
obj-$(CONFIG_CPU_SUBTYPE_SH7206) += setup-sh7206.o clock-sh7206.o obj-$(CONFIG_CPU_SUBTYPE_SH7206) += setup-sh7206.o clock-sh7206.o
obj-$(CONFIG_CPU_SUBTYPE_SH7269) += setup-sh7269.o clock-sh7269.o
obj-$(CONFIG_CPU_SUBTYPE_MXG) += setup-mxg.o clock-sh7206.o obj-$(CONFIG_CPU_SUBTYPE_MXG) += setup-mxg.o clock-sh7206.o
# Pinmux setup # Pinmux setup
pinmux-$(CONFIG_CPU_SUBTYPE_SH7203) := pinmux-sh7203.o pinmux-$(CONFIG_CPU_SUBTYPE_SH7203) := pinmux-sh7203.o
pinmux-$(CONFIG_CPU_SUBTYPE_SH7264) := pinmux-sh7264.o pinmux-$(CONFIG_CPU_SUBTYPE_SH7264) := pinmux-sh7264.o
pinmux-$(CONFIG_CPU_SUBTYPE_SH7269) := pinmux-sh7269.o
obj-$(CONFIG_GENERIC_GPIO) += $(pinmux-y) obj-$(CONFIG_GENERIC_GPIO) += $(pinmux-y)
/*
* arch/sh/kernel/cpu/sh2a/clock-sh7269.c
*
* SH7269 clock framework support
*
* Copyright (C) 2012 Phil Edworthy
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/clkdev.h>
#include <asm/clock.h>
/* SH7269 registers */
#define FRQCR 0xfffe0010
#define STBCR3 0xfffe0408
#define STBCR4 0xfffe040c
#define STBCR5 0xfffe0410
#define STBCR6 0xfffe0414
#define STBCR7 0xfffe0418
#define PLL_RATE 20
/* Fixed 32 KHz root clock for RTC */
static struct clk r_clk = {
.rate = 32768,
};
/*
* Default rate for the root input clock, reset this with clk_set_rate()
* from the platform code.
*/
static struct clk extal_clk = {
.rate = 13340000,
};
static unsigned long pll_recalc(struct clk *clk)
{
return clk->parent->rate * PLL_RATE;
}
static struct sh_clk_ops pll_clk_ops = {
.recalc = pll_recalc,
};
static struct clk pll_clk = {
.ops = &pll_clk_ops,
.parent = &extal_clk,
.flags = CLK_ENABLE_ON_INIT,
};
static unsigned long peripheral0_recalc(struct clk *clk)
{
return clk->parent->rate / 8;
}
static struct sh_clk_ops peripheral0_clk_ops = {
.recalc = peripheral0_recalc,
};
static struct clk peripheral0_clk = {
.ops = &peripheral0_clk_ops,
.parent = &pll_clk,
.flags = CLK_ENABLE_ON_INIT,
};
static unsigned long peripheral1_recalc(struct clk *clk)
{
return clk->parent->rate / 4;
}
static struct sh_clk_ops peripheral1_clk_ops = {
.recalc = peripheral1_recalc,
};
static struct clk peripheral1_clk = {
.ops = &peripheral1_clk_ops,
.parent = &pll_clk,
.flags = CLK_ENABLE_ON_INIT,
};
struct clk *main_clks[] = {
&r_clk,
&extal_clk,
&pll_clk,
&peripheral0_clk,
&peripheral1_clk,
};
static int div2[] = { 1, 2, 0, 4 };
static struct clk_div_mult_table div4_div_mult_table = {
.divisors = div2,
.nr_divisors = ARRAY_SIZE(div2),
};
static struct clk_div4_table div4_table = {
.div_mult_table = &div4_div_mult_table,
};
enum { DIV4_I, DIV4_B,
DIV4_NR };
#define DIV4(_reg, _bit, _mask, _flags) \
SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
/* The mask field specifies the div2 entries that are valid */
struct clk div4_clks[DIV4_NR] = {
[DIV4_I] = DIV4(FRQCR, 8, 0xB, CLK_ENABLE_REG_16BIT
| CLK_ENABLE_ON_INIT),
[DIV4_B] = DIV4(FRQCR, 4, 0xA, CLK_ENABLE_REG_16BIT
| CLK_ENABLE_ON_INIT),
};
enum { MSTP72,
MSTP60,
MSTP47, MSTP46, MSTP45, MSTP44, MSTP43, MSTP42, MSTP41, MSTP40,
MSTP35, MSTP32, MSTP30,
MSTP_NR };
static struct clk mstp_clks[MSTP_NR] = {
[MSTP72] = SH_CLK_MSTP8(&peripheral0_clk, STBCR7, 2, 0), /* CMT */
[MSTP60] = SH_CLK_MSTP8(&peripheral1_clk, STBCR6, 0, 0), /* USB */
[MSTP47] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 7, 0), /* SCIF0 */
[MSTP46] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 6, 0), /* SCIF1 */
[MSTP45] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 5, 0), /* SCIF2 */
[MSTP44] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 4, 0), /* SCIF3 */
[MSTP43] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 3, 0), /* SCIF4 */
[MSTP42] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 2, 0), /* SCIF5 */
[MSTP41] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 1, 0), /* SCIF6 */
[MSTP40] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 0, 0), /* SCIF7 */
[MSTP35] = SH_CLK_MSTP8(&peripheral0_clk, STBCR3, 5, 0), /* MTU2 */
[MSTP32] = SH_CLK_MSTP8(&peripheral1_clk, STBCR3, 2, 0), /* ADC */
[MSTP30] = SH_CLK_MSTP8(&r_clk, STBCR3, 0, 0), /* RTC */
};
static struct clk_lookup lookups[] = {
/* main clocks */
CLKDEV_CON_ID("rclk", &r_clk),
CLKDEV_CON_ID("extal", &extal_clk),
CLKDEV_CON_ID("pll_clk", &pll_clk),
CLKDEV_CON_ID("peripheral_clk", &peripheral1_clk),
/* DIV4 clocks */
CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
/* MSTP clocks */
CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP47]),
CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP46]),
CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP45]),
CLKDEV_ICK_ID("sci_fck", "sh-sci.3", &mstp_clks[MSTP44]),
CLKDEV_ICK_ID("sci_fck", "sh-sci.4", &mstp_clks[MSTP43]),
CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[MSTP42]),
CLKDEV_ICK_ID("sci_fck", "sh-sci.6", &mstp_clks[MSTP41]),
CLKDEV_ICK_ID("sci_fck", "sh-sci.7", &mstp_clks[MSTP40]),
CLKDEV_CON_ID("cmt_fck", &mstp_clks[MSTP72]),
CLKDEV_CON_ID("usb0", &mstp_clks[MSTP60]),
CLKDEV_CON_ID("mtu2_fck", &mstp_clks[MSTP35]),
CLKDEV_CON_ID("adc0", &mstp_clks[MSTP32]),
CLKDEV_CON_ID("rtc0", &mstp_clks[MSTP30]),
};
int __init arch_clk_init(void)
{
int k, ret = 0;
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
ret = clk_register(main_clks[k]);
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
if (!ret)
ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
if (!ret)
ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
return ret;
}
This diff is collapsed.
...@@ -32,6 +32,9 @@ void __cpuinit cpu_probe(void) ...@@ -32,6 +32,9 @@ void __cpuinit cpu_probe(void)
#elif defined(CONFIG_CPU_SUBTYPE_SH7264) #elif defined(CONFIG_CPU_SUBTYPE_SH7264)
boot_cpu_data.type = CPU_SH7264; boot_cpu_data.type = CPU_SH7264;
boot_cpu_data.flags |= CPU_HAS_FPU; boot_cpu_data.flags |= CPU_HAS_FPU;
#elif defined(CONFIG_CPU_SUBTYPE_SH7269)
boot_cpu_data.type = CPU_SH7269;
boot_cpu_data.flags |= CPU_HAS_FPU;
#elif defined(CONFIG_CPU_SUBTYPE_SH7206) #elif defined(CONFIG_CPU_SUBTYPE_SH7206)
boot_cpu_data.type = CPU_SH7206; boot_cpu_data.type = CPU_SH7206;
boot_cpu_data.flags |= CPU_HAS_DSP; boot_cpu_data.flags |= CPU_HAS_DSP;
......
This diff is collapsed.
...@@ -52,6 +52,7 @@ MIGOR SH_MIGOR ...@@ -52,6 +52,7 @@ MIGOR SH_MIGOR
RSK7201 SH_RSK7201 RSK7201 SH_RSK7201
RSK7203 SH_RSK7203 RSK7203 SH_RSK7203
RSK7264 SH_RSK7264 RSK7264 SH_RSK7264
RSK7269 SH_RSK7269
AP325RXA SH_AP325RXA AP325RXA SH_AP325RXA
SH2007 SH_SH2007 SH2007 SH_SH2007
SH7757LCR SH_SH7757LCR SH7757LCR SH_SH7757LCR
......
...@@ -1138,6 +1138,7 @@ config ZVM_WATCHDOG ...@@ -1138,6 +1138,7 @@ config ZVM_WATCHDOG
config SH_WDT config SH_WDT
tristate "SuperH Watchdog" tristate "SuperH Watchdog"
depends on SUPERH && (CPU_SH3 || CPU_SH4) depends on SUPERH && (CPU_SH3 || CPU_SH4)
select WATCHDOG_CORE
help help
This driver adds watchdog support for the integrated watchdog in the This driver adds watchdog support for the integrated watchdog in the
SuperH processors. If you have one of these processors and wish SuperH processors. If you have one of these processors and wish
......
This diff is collapsed.
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