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Commit bef964e5 authored by Franck Bui-Huu's avatar Franck Bui-Huu Committed by Ralf Baechle
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[MIPS] Remove Momenco Jaguar ATX support 

It has some hackish code and it odd DMA results in the need to support
old features in kernel code.
Signed-off-by: default avatarFranck Bui-Huu <fbuihuu@gmail.com>
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 1e54f778
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arch/mips/Kconfig
View file @ bef964e5
......@@ -369,28 +369,6 @@ config MIPS_SIM
This option enables support for MIPS Technologies MIPSsim software
emulator.
config MOMENCO_JAGUAR_ATX
bool "Momentum Jaguar board"
select BOOT_ELF32
select DMA_NONCOHERENT
select HW_HAS_PCI
select IRQ_CPU
select IRQ_CPU_RM7K
select IRQ_MV64340
select LIMITED_DMA
select PCI_MARVELL
select RM7000_CPU_SCACHE
select SWAP_IO_SPACE
select SYS_HAS_CPU_RM9000
select SYS_HAS_EARLY_PRINTK
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_KGDB
help
The Jaguar ATX is a MIPS-based Single Board Computer (SBC) made by
Momentum Computer <http://www.momenco.com/>.
config MOMENCO_OCELOT
bool "Momentum Ocelot board"
select DMA_NONCOHERENT
......@@ -806,7 +784,6 @@ source "arch/mips/ddb5xxx/Kconfig"
source "arch/mips/gt64120/ev64120/Kconfig"
source "arch/mips/jazz/Kconfig"
source "arch/mips/lasat/Kconfig"
source "arch/mips/momentum/Kconfig"
source "arch/mips/pmc-sierra/Kconfig"
source "arch/mips/sgi-ip27/Kconfig"
source "arch/mips/sibyte/Kconfig"
......
arch/mips/Makefile
View file @ bef964e5
......@@ -378,17 +378,6 @@ core-$(CONFIG_BASLER_EXCITE) += arch/mips/basler/excite/
cflags-$(CONFIG_BASLER_EXCITE) += -Iinclude/asm-mips/mach-excite
load-$(CONFIG_BASLER_EXCITE) += 0x80100000
#
# Momentum Jaguar ATX
#
core-$(CONFIG_MOMENCO_JAGUAR_ATX) += arch/mips/momentum/jaguar_atx/
cflags-$(CONFIG_MOMENCO_JAGUAR_ATX) += -Iinclude/asm-mips/mach-ja
#ifdef CONFIG_JAGUAR_DMALOW
#load-$(CONFIG_MOMENCO_JAGUAR_ATX) += 0xffffffff88000000
#else
load-$(CONFIG_MOMENCO_JAGUAR_ATX) += 0xffffffff80100000
#endif
#
# NEC DDB
#
......
arch/mips/configs/jaguar-atx_defconfig deleted 100644 → 0
View file @ 1e54f778
This diff is collapsed.
arch/mips/momentum/Kconfig deleted 100644 → 0
View file @ 1e54f778
config JAGUAR_DMALOW
bool "Low DMA Mode"
depends on MOMENCO_JAGUAR_ATX
help
Select to Y if jump JP5 is set on your board, N otherwise. Normally
the jumper is set, so if you feel unsafe, just say Y.
arch/mips/momentum/jaguar_atx/Makefile deleted 100644 → 0
View file @ 1e54f778
#
# Makefile for Momentum Computer's Jaguar-ATX board.
#
# Note! Dependencies are done automagically by 'make dep', which also
# removes any old dependencies. DON'T put your own dependencies here
# unless it's something special (ie not a .c file).
#
obj-y += irq.o platform.o prom.o reset.o setup.o
obj-$(CONFIG_SERIAL_8250_CONSOLE) += ja-console.o
obj-$(CONFIG_REMOTE_DEBUG) += dbg_io.o
arch/mips/momentum/jaguar_atx/dbg_io.c deleted 100644 → 0
View file @ 1e54f778
#if defined(CONFIG_REMOTE_DEBUG)
#include <asm/serial.h> /* For the serial port location and base baud */
/* --- CONFIG --- */
typedef unsigned char uint8;
typedef unsigned int uint32;
/* --- END OF CONFIG --- */
#define UART16550_BAUD_2400 2400
#define UART16550_BAUD_4800 4800
#define UART16550_BAUD_9600 9600
#define UART16550_BAUD_19200 19200
#define UART16550_BAUD_38400 38400
#define UART16550_BAUD_57600 57600
#define UART16550_BAUD_115200 115200
#define UART16550_PARITY_NONE 0
#define UART16550_PARITY_ODD 0x08
#define UART16550_PARITY_EVEN 0x18
#define UART16550_PARITY_MARK 0x28
#define UART16550_PARITY_SPACE 0x38
#define UART16550_DATA_5BIT 0x0
#define UART16550_DATA_6BIT 0x1
#define UART16550_DATA_7BIT 0x2
#define UART16550_DATA_8BIT 0x3
#define UART16550_STOP_1BIT 0x0
#define UART16550_STOP_2BIT 0x4
/* ----------------------------------------------------- */
/* === CONFIG === */
/* [jsun] we use the second serial port for kdb */
#define BASE OCELOT_SERIAL1_BASE
#define MAX_BAUD OCELOT_BASE_BAUD
/* === END OF CONFIG === */
#define REG_OFFSET 4
/* register offset */
#define OFS_RCV_BUFFER 0
#define OFS_TRANS_HOLD 0
#define OFS_SEND_BUFFER 0
#define OFS_INTR_ENABLE (1*REG_OFFSET)
#define OFS_INTR_ID (2*REG_OFFSET)
#define OFS_DATA_FORMAT (3*REG_OFFSET)
#define OFS_LINE_CONTROL (3*REG_OFFSET)
#define OFS_MODEM_CONTROL (4*REG_OFFSET)
#define OFS_RS232_OUTPUT (4*REG_OFFSET)
#define OFS_LINE_STATUS (5*REG_OFFSET)
#define OFS_MODEM_STATUS (6*REG_OFFSET)
#define OFS_RS232_INPUT (6*REG_OFFSET)
#define OFS_SCRATCH_PAD (7*REG_OFFSET)
#define OFS_DIVISOR_LSB (0*REG_OFFSET)
#define OFS_DIVISOR_MSB (1*REG_OFFSET)
/* memory-mapped read/write of the port */
#define UART16550_READ(y) (*((volatile uint8*)(BASE + y)))
#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z)
void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
{
/* disable interrupts */
UART16550_WRITE(OFS_INTR_ENABLE, 0);
/* set up baud rate */
{
uint32 divisor;
/* set DIAB bit */
UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
/* set divisor */
divisor = MAX_BAUD / baud;
UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
/* clear DIAB bit */
UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
}
/* set data format */
UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
}
static int remoteDebugInitialized = 0;
uint8 getDebugChar(void)
{
if (!remoteDebugInitialized) {
remoteDebugInitialized = 1;
debugInit(UART16550_BAUD_38400,
UART16550_DATA_8BIT,
UART16550_PARITY_NONE, UART16550_STOP_1BIT);
}
while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
return UART16550_READ(OFS_RCV_BUFFER);
}
int putDebugChar(uint8 byte)
{
if (!remoteDebugInitialized) {
remoteDebugInitialized = 1;
debugInit(UART16550_BAUD_38400,
UART16550_DATA_8BIT,
UART16550_PARITY_NONE, UART16550_STOP_1BIT);
}
while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
UART16550_WRITE(OFS_SEND_BUFFER, byte);
return 1;
}
#endif
arch/mips/momentum/jaguar_atx/irq.c deleted 100644 → 0
View file @ 1e54f778
/*
* Copyright (C) 2002 Momentum Computer, Inc.
* Author: Matthew Dharm, mdharm@momenco.com
*
* Based on work by:
* Copyright (C) 2000 RidgeRun, Inc.
* Author: RidgeRun, Inc.
* glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
*
* Copyright 2001 MontaVista Software Inc.
* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
*
* Copyright (C) 2000, 01, 06 Ralf Baechle (ralf@linux-mips.org)
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/signal.h>
#include <linux/types.h>
#include <asm/irq_cpu.h>
#include <asm/mipsregs.h>
#include <asm/time.h>
asmlinkage void plat_irq_dispatch(void)
{
unsigned int pending = read_c0_cause() & read_c0_status();
if (pending & STATUSF_IP0)
do_IRQ(0);
else if (pending & STATUSF_IP1)
do_IRQ(1);
else if (pending & STATUSF_IP2)
do_IRQ(2);
else if (pending & STATUSF_IP3)
do_IRQ(3);
else if (pending & STATUSF_IP4)
do_IRQ(4);
else if (pending & STATUSF_IP5)
do_IRQ(5);
else if (pending & STATUSF_IP6)
do_IRQ(6);
else if (pending & STATUSF_IP7)
ll_timer_interrupt(7);
else {
/*
* Now look at the extended interrupts
*/
pending = (read_c0_cause() & (read_c0_intcontrol() << 8)) >> 16;
if (pending & STATUSF_IP8)
ll_mv64340_irq();
}
}
static struct irqaction cascade_mv64340 = {
no_action, IRQF_DISABLED, CPU_MASK_NONE, "MV64340-Cascade", NULL, NULL
};
void __init arch_init_irq(void)
{
/*
* Clear all of the interrupts while we change the able around a bit.
* int-handler is not on bootstrap
*/
clear_c0_status(ST0_IM);
mips_cpu_irq_init();
rm7k_cpu_irq_init();
/* set up the cascading interrupts */
setup_irq(8, &cascade_mv64340);
mv64340_irq_init(16);
set_c0_status(ST0_IM);
}
arch/mips/momentum/jaguar_atx/ja-console.c deleted 100644 → 0
View file @ 1e54f778
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2001, 2002, 2004 Ralf Baechle
*/
#include <linux/init.h>
#include <linux/console.h>
#include <linux/kdev_t.h>
#include <linux/major.h>
#include <linux/termios.h>
#include <linux/sched.h>
#include <linux/tty.h>
#include <linux/serial.h>
#include <linux/serial_core.h>
#include <asm/serial.h>
/* SUPERIO uart register map */
struct ja_uartregs {
union {
volatile u8 pad0[3];
volatile u8 rbr; /* read only, DLAB == 0 */
volatile u8 pad1[3];
volatile u8 thr; /* write only, DLAB == 0 */
volatile u8 pad2[3];
volatile u8 dll; /* DLAB == 1 */
} u1;
union {
volatile u8 pad0[3];
volatile u8 ier; /* DLAB == 0 */
volatile u8 pad1[3];
volatile u8 dlm; /* DLAB == 1 */
} u2;
union {
volatile u8 pad0[3];
volatile u8 iir; /* read only */
volatile u8 pad1[3];
volatile u8 fcr; /* write only */
} u3;
volatile u8 pad0[3];
volatile u8 iu_lcr;
volatile u8 pad1[3];
volatile u8 iu_mcr;
volatile u8 pad2[3];
volatile u8 iu_lsr;
volatile u8 pad3[3];
volatile u8 iu_msr;
volatile u8 pad4[3];
volatile u8 iu_scr;
} ja_uregs_t;
#define iu_rbr u1.rbr
#define iu_thr u1.thr
#define iu_dll u1.dll
#define iu_ier u2.ier
#define iu_dlm u2.dlm
#define iu_iir u3.iir
#define iu_fcr u3.fcr
extern unsigned long uart_base;
static inline struct ja_uartregs *console_uart(void)
{
return (struct ja_uartregs *) (uart_base + 0x23UL);
}
void prom_putchar(char c)
{
struct ja_uartregs *uart = console_uart();
while ((uart->iu_lsr & 0x20) == 0);
uart->iu_thr = c;
}
static void inline ja_console_probe(void)
{
struct uart_port up;
/*
* Register to interrupt zero because we share the interrupt with
* the serial driver which we don't properly support yet.
*/
memset(&up, 0, sizeof(up));
up.membase = (unsigned char *) uart_base + 0x23UL;
up.irq = JAGUAR_ATX_SERIAL1_IRQ;
up.uartclk = JAGUAR_ATX_UART_CLK;
up.regshift = 2;
up.iotype = UPIO_MEM;
up.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
up.line = 0;
if (early_serial_setup(&up))
printk(KERN_ERR "Early serial init of port 0 failed\n");
}
__init void ja_setup_console(void)
{
ja_console_probe();
}
arch/mips/momentum/jaguar_atx/jaguar_atx_fpga.h deleted 100644 → 0
View file @ 1e54f778
/*
* Jaguar-ATX Board Register Definitions
*
* (C) 2002 Momentum Computer Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __JAGUAR_ATX_FPGA_H__
#define __JAGUAR_ATX_FPGA_H__
#define JAGUAR_ATX_REG_BOARDREV 0x0
#define JAGUAR_ATX_REG_FPGA_REV 0x1
#define JAGUAR_ATX_REG_FPGA_TYPE 0x2
#define JAGUAR_ATX_REG_RESET_STATUS 0x3
#define JAGUAR_ATX_REG_BOARD_STATUS 0x4
#define JAGUAR_ATX_REG_RESERVED1 0x5
#define JAGUAR_ATX_REG_SET 0x6
#define JAGUAR_ATX_REG_CLR 0x7
#define JAGUAR_ATX_REG_EEPROM_MODE 0x9
#define JAGUAR_ATX_REG_RESERVED2 0xa
#define JAGUAR_ATX_REG_RESERVED3 0xb
#define JAGUAR_ATX_REG_RESERVED4 0xc
#define JAGUAR_ATX_REG_PHY_INTSTAT 0xd
#define JAGUAR_ATX_REG_RESERVED5 0xe
#define JAGUAR_ATX_REG_RESERVED6 0xf
#define JAGUAR_ATX_CS0_ADDR 0xfc000000L
extern unsigned long ja_fpga_base;
#define __FPGA_REG_TO_ADDR(reg) \
((void *) ja_fpga_base + JAGUAR_ATX_REG_##reg)
#define JAGUAR_FPGA_WRITE(x, reg) writeb(x, __FPGA_REG_TO_ADDR(reg))
#define JAGUAR_FPGA_READ(reg) readb(__FPGA_REG_TO_ADDR(reg))
#endif
arch/mips/momentum/jaguar_atx/platform.c deleted 100644 → 0
View file @ 1e54f778
#include <linux/delay.h>
#include <linux/if_ether.h>
#include <linux/ioport.h>
#include <linux/mv643xx.h>
#include <linux/platform_device.h>
#include "jaguar_atx_fpga.h"
#if defined(CONFIG_MV643XX_ETH) || defined(CONFIG_MV643XX_ETH_MODULE)
static struct resource mv643xx_eth_shared_resources[] = {
[0] = {
.name = "ethernet shared base",
.start = 0xf1000000 + MV643XX_ETH_SHARED_REGS,
.end = 0xf1000000 + MV643XX_ETH_SHARED_REGS +
MV643XX_ETH_SHARED_REGS_SIZE - 1,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device mv643xx_eth_shared_device = {
.name = MV643XX_ETH_SHARED_NAME,
.id = 0,
.num_resources = ARRAY_SIZE(mv643xx_eth_shared_resources),
.resource = mv643xx_eth_shared_resources,
};
#define MV_SRAM_BASE 0xfe000000UL
#define MV_SRAM_SIZE (256 * 1024)
#define MV_SRAM_RXRING_SIZE (MV_SRAM_SIZE / 4)
#define MV_SRAM_TXRING_SIZE (MV_SRAM_SIZE / 4)
#define MV_SRAM_BASE_ETH0 MV_SRAM_BASE
#define MV_SRAM_BASE_ETH1 (MV_SRAM_BASE + (MV_SRAM_SIZE / 2))
#define MV64x60_IRQ_ETH_0 48
#define MV64x60_IRQ_ETH_1 49
#define MV64x60_IRQ_ETH_2 50
static struct resource mv64x60_eth0_resources[] = {
[0] = {
.name = "eth0 irq",
.start = MV64x60_IRQ_ETH_0,
.end = MV64x60_IRQ_ETH_0,
.flags = IORESOURCE_IRQ,
},
};
static struct mv643xx_eth_platform_data eth0_pd = {
.port_number = 0,
.tx_sram_addr = MV_SRAM_BASE_ETH0,
.tx_sram_size = MV_SRAM_TXRING_SIZE,
.tx_queue_size = MV_SRAM_TXRING_SIZE / 16,
.rx_sram_addr = MV_SRAM_BASE_ETH0 + MV_SRAM_TXRING_SIZE,
.rx_sram_size = MV_SRAM_RXRING_SIZE,
.rx_queue_size = MV_SRAM_RXRING_SIZE / 16,
};
static struct platform_device eth0_device = {
.name = MV643XX_ETH_NAME,
.id = 0,
.num_resources = ARRAY_SIZE(mv64x60_eth0_resources),
.resource = mv64x60_eth0_resources,
.dev = {
.platform_data = &eth0_pd,
},
};
static struct resource mv64x60_eth1_resources[] = {
[0] = {
.name = "eth1 irq",
.start = MV64x60_IRQ_ETH_1,
.end = MV64x60_IRQ_ETH_1,
.flags = IORESOURCE_IRQ,
},
};
static struct mv643xx_eth_platform_data eth1_pd = {
.port_number = 1,
.tx_sram_addr = MV_SRAM_BASE_ETH1,
.tx_sram_size = MV_SRAM_TXRING_SIZE,
.tx_queue_size = MV_SRAM_TXRING_SIZE / 16,
.rx_sram_addr = MV_SRAM_BASE_ETH1 + MV_SRAM_TXRING_SIZE,
.rx_sram_size = MV_SRAM_RXRING_SIZE,
.rx_queue_size = MV_SRAM_RXRING_SIZE / 16,
};
static struct platform_device eth1_device = {
.name = MV643XX_ETH_NAME,
.id = 1,
.num_resources = ARRAY_SIZE(mv64x60_eth1_resources),
.resource = mv64x60_eth1_resources,
.dev = {
.platform_data = &eth1_pd,
},
};
static struct resource mv64x60_eth2_resources[] = {
[0] = {
.name = "eth2 irq",
.start = MV64x60_IRQ_ETH_2,
.end = MV64x60_IRQ_ETH_2,
.flags = IORESOURCE_IRQ,
},
};
static struct mv643xx_eth_platform_data eth2_pd = {
.port_number = 2,
};
static struct platform_device eth2_device = {
.name = MV643XX_ETH_NAME,
.id = 2,
.num_resources = ARRAY_SIZE(mv64x60_eth2_resources),
.resource = mv64x60_eth2_resources,
.dev = {
.platform_data = &eth2_pd,
},
};
static struct platform_device *mv643xx_eth_pd_devs[] __initdata = {
&mv643xx_eth_shared_device,
&eth0_device,
&eth1_device,
&eth2_device,
};
static u8 __init exchange_bit(u8 val, u8 cs)
{
/* place the data */
JAGUAR_FPGA_WRITE((val << 2) | cs, EEPROM_MODE);
udelay(1);
/* turn the clock on */
JAGUAR_FPGA_WRITE((val << 2) | cs | 0x2, EEPROM_MODE);
udelay(1);
/* turn the clock off and read-strobe */
JAGUAR_FPGA_WRITE((val << 2) | cs | 0x10, EEPROM_MODE);
/* return the data */
return (JAGUAR_FPGA_READ(EEPROM_MODE) >> 3) & 0x1;
}
static void __init get_mac(char dest[6])
{
u8 read_opcode[12] = {1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
int i,j;
for (i = 0; i < 12; i++)
exchange_bit(read_opcode[i], 1);
for (j = 0; j < 6; j++) {
dest[j] = 0;
for (i = 0; i < 8; i++) {
dest[j] <<= 1;
dest[j] |= exchange_bit(0, 1);
}
}
/* turn off CS */
exchange_bit(0,0);
}
/*
* Copy and increment ethernet MAC address by a small value.
*
* This is useful for systems where the only one MAC address is stored in
* non-volatile memory for multiple ports.
*/
static inline void eth_mac_add(unsigned char *dst, unsigned char *src,
unsigned int add)
{
int i;
BUG_ON(add >= 256);
for (i = ETH_ALEN; i >= 0; i--) {
dst[i] = src[i] + add;
add = dst[i] < src[i]; /* compute carry */
}
WARN_ON(add);
}
static int __init mv643xx_eth_add_pds(void)
{
unsigned char mac[ETH_ALEN];
int ret;
get_mac(mac);
eth_mac_add(eth0_pd.mac_addr, mac, 0);
eth_mac_add(eth1_pd.mac_addr, mac, 1);
eth_mac_add(eth2_pd.mac_addr, mac, 2);
ret = platform_add_devices(mv643xx_eth_pd_devs,
ARRAY_SIZE(mv643xx_eth_pd_devs));
return ret;
}
device_initcall(mv643xx_eth_add_pds);
#endif /* defined(CONFIG_MV643XX_ETH) || defined(CONFIG_MV643XX_ETH_MODULE) */
arch/mips/momentum/jaguar_atx/prom.c deleted 100644 → 0
View file @ 1e54f778
/*
* Copyright 2002 Momentum Computer Inc.
* Author: Matthew Dharm <mdharm@momenco.com>
*
* Louis Hamilton, Red Hat, Inc.
* hamilton@redhat.com [MIPS64 modifications]
*
* Based on Ocelot Linux port, which is
* Copyright 2001 MontaVista Software Inc.
* Author: jsun@mvista.com or jsun@junsun.net
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* Added changes for SMP - Manish Lachwani (lachwani@pmc-sierra.com)
*/
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/sched.h>
#include <linux/bootmem.h>
#include <linux/mv643xx.h>
#include <asm/addrspace.h>
#include <asm/bootinfo.h>
#include <asm/pmon.h>
#include "jaguar_atx_fpga.h"
extern void ja_setup_console(void);
struct callvectors *debug_vectors;
extern unsigned long cpu_clock;
const char *get_system_type(void)
{
return "Momentum Jaguar-ATX";
}
#ifdef CONFIG_64BIT
unsigned long signext(unsigned long addr)
{
addr &= 0xffffffff;
return (unsigned long)((int)addr);
}
void *get_arg(unsigned long args, int arc)
{
unsigned long ul;
unsigned char *puc, uc;
args += (arc * 4);
ul = (unsigned long)signext(args);
puc = (unsigned char *)ul;
if (puc == 0)
return (void *)0;
#ifdef CONFIG_CPU_LITTLE_ENDIAN
uc = *puc++;
l = (unsigned long)uc;
uc = *puc++;
ul |= (((unsigned long)uc) << 8);
uc = *puc++;
ul |= (((unsigned long)uc) << 16);
uc = *puc++;
ul |= (((unsigned long)uc) << 24);
#else
uc = *puc++;
ul = ((unsigned long)uc) << 24;
uc = *puc++;
ul |= (((unsigned long)uc) << 16);
uc = *puc++;
ul |= (((unsigned long)uc) << 8);
uc = *puc++;
ul |= ((unsigned long)uc);
#endif
ul = signext(ul);
return (void *)ul;
}
char *arg64(unsigned long addrin, int arg_index)
{
unsigned long args;
char *p;
args = signext(addrin);
p = (char *)get_arg(args, arg_index);
return p;
}
#endif /* CONFIG_64BIT */
/* PMON passes arguments in C main() style */
void __init prom_init(void)
{
int argc = fw_arg0;
char **arg = (char **) fw_arg1;
char **env = (char **) fw_arg2;
struct callvectors *cv = (struct callvectors *) fw_arg3;
int i;
#ifdef CONFIG_SERIAL_8250_CONSOLE
// ja_setup_console(); /* The very first thing. */
#endif
#ifdef CONFIG_64BIT
char *ptr;
printk("Mips64 Jaguar-ATX\n");
/* save the PROM vectors for debugging use */
debug_vectors = (struct callvectors *)signext((unsigned long)cv);
/* arg[0] is "g", the rest is boot parameters */
arcs_cmdline[0] = '\0';
for (i = 1; i < argc; i++) {
ptr = (char *)arg64((unsigned long)arg, i);
if ((strlen(arcs_cmdline) + strlen(ptr) + 1) >=
sizeof(arcs_cmdline))
break;
strcat(arcs_cmdline, ptr);
strcat(arcs_cmdline, " ");
}
i = 0;
while (1) {
ptr = (char *)arg64((unsigned long)env, i);
if (! ptr)
break;
if (strncmp("gtbase", ptr, strlen("gtbase")) == 0) {
marvell_base = simple_strtol(ptr + strlen("gtbase="),
NULL, 16);
if ((marvell_base & 0xffffffff00000000) == 0)
marvell_base |= 0xffffffff00000000;
printk("marvell_base set to 0x%016lx\n", marvell_base);
}
if (strncmp("cpuclock", ptr, strlen("cpuclock")) == 0) {
cpu_clock = simple_strtol(ptr + strlen("cpuclock="),
NULL, 10);
printk("cpu_clock set to %d\n", cpu_clock);
}
i++;
}
printk("arcs_cmdline: %s\n", arcs_cmdline);
#else /* CONFIG_64BIT */
/* save the PROM vectors for debugging use */
debug_vectors = cv;
/* arg[0] is "g", the rest is boot parameters */
arcs_cmdline[0] = '\0';
for (i = 1; i < argc; i++) {
if (strlen(arcs_cmdline) + strlen(arg[i] + 1)
>= sizeof(arcs_cmdline))
break;
strcat(arcs_cmdline, arg[i]);
strcat(arcs_cmdline, " ");
}
while (*env) {
if (strncmp("gtbase", *env, strlen("gtbase")) == 0) {
marvell_base = simple_strtol(*env + strlen("gtbase="),
NULL, 16);
}
if (strncmp("cpuclock", *env, strlen("cpuclock")) == 0) {
cpu_clock = simple_strtol(*env + strlen("cpuclock="),
NULL, 10);
}
env++;
}
#endif /* CONFIG_64BIT */
mips_machgroup = MACH_GROUP_MOMENCO;
mips_machtype = MACH_MOMENCO_JAGUAR_ATX;
}
void __init prom_free_prom_memory(void)
{
}
void __init prom_fixup_mem_map(unsigned long start, unsigned long end)
{
}
int prom_boot_secondary(int cpu, unsigned long sp, unsigned long gp)
{
/* Clear the semaphore */
*(volatile uint32_t *)(0xbb000a68) = 0x80000000;
return 1;
}
void prom_init_secondary(void)
{
clear_c0_config(CONF_CM_CMASK);
set_c0_config(0x2);
clear_c0_status(ST0_IM);
set_c0_status(0x1ffff);
}
void prom_smp_finish(void)
{
}
arch/mips/momentum/jaguar_atx/reset.c deleted 100644 → 0
View file @ 1e54f778
/*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* Copyright (C) 1997, 2001 Ralf Baechle
* Copyright 2001 MontaVista Software Inc.
* Author: jsun@mvista.com or jsun@junsun.net
*
* Copyright (C) 2002 Momentum Computer Inc.
* Author: Matthew Dharm <mdharm@momenco.com>
*
* Louis Hamilton, Red Hat, Inc.
* hamilton@redhat.com [MIPS64 modifications]
*/
#include <linux/sched.h>
#include <linux/mm.h>
#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/processor.h>
#include <asm/reboot.h>
#include <asm/system.h>
#include <linux/delay.h>
void momenco_jaguar_restart(char *command)
{
/* base address of timekeeper portion of part */
#ifdef CONFIG_64BIT
void *nvram = (void*) 0xfffffffffc807000;
#else
void *nvram = (void*) 0xfc807000;
#endif
/* Ask the NVRAM/RTC/watchdog chip to assert reset in 1/16 second */
writeb(0x84, nvram + 0xff7);
/* wait for the watchdog to go off */
mdelay(100+(1000/16));
/* if the watchdog fails for some reason, let people know */
printk(KERN_NOTICE "Watchdog reset failed\n");
}
void momenco_jaguar_halt(void)
{
printk(KERN_NOTICE "\n** You can safely turn off the power\n");
while (1)
__asm__(".set\tmips3\n\t"
"wait\n\t"
".set\tmips0");
}
void momenco_jaguar_power_off(void)
{
momenco_jaguar_halt();
}
arch/mips/momentum/jaguar_atx/setup.c deleted 100644 → 0
View file @ 1e54f778
This diff is collapsed.
arch/mips/pci/Makefile
View file @ bef964e5
......@@ -30,7 +30,6 @@ obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o
obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o
obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o
obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o
obj-$(CONFIG_MOMENCO_JAGUAR_ATX)+= fixup-jaguar.o
obj-$(CONFIG_MOMENCO_OCELOT) += fixup-ocelot.o pci-ocelot.o
obj-$(CONFIG_MOMENCO_OCELOT_3) += fixup-ocelot3.o
obj-$(CONFIG_MOMENCO_OCELOT_C) += fixup-ocelot-c.o pci-ocelot-c.o
......
arch/mips/pci/fixup-jaguar.c deleted 100644 → 0
View file @ 1e54f778
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Marvell MV64340 interrupt fixup code.
*
* Marvell wants an NDA for their docs so this was written without
* documentation. You've been warned.
*
* Copyright (C) 2004 Ralf Baechle (ralf@linux-mips.org)
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <asm/mipsregs.h>
/*
* WARNING: Example of how _NOT_ to do it.
*/
int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
int bus = dev->bus->number;
if (bus == 0 && slot == 1)
return 3; /* PCI-X A */
if (bus == 0 && slot == 2)
return 4; /* PCI-X B */
if (bus == 1 && slot == 1)
return 5; /* PCI A */
if (bus == 1 && slot == 2)
return 6; /* PCI B */
return 0;
panic("Whooops in pcibios_map_irq");
}
/* Do platform specific device initialization at pci_enable_device() time */
int pcibios_plat_dev_init(struct pci_dev *dev)
{
return 0;
}
include/asm-mips/bootinfo.h
View file @ bef964e5
......@@ -121,7 +121,7 @@
#define MACH_MOMENCO_OCELOT 0
#define MACH_MOMENCO_OCELOT_G 1 /* no more supported (may 2007) */
#define MACH_MOMENCO_OCELOT_C 2
#define MACH_MOMENCO_JAGUAR_ATX 3
#define MACH_MOMENCO_JAGUAR_ATX 3 /* no more supported (may 2007) */
#define MACH_MOMENCO_OCELOT_3 4
/*
......
include/asm-mips/mach-ja/cpu-feature-overrides.h deleted 100644 → 0
View file @ 1e54f778
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2003, 2004 Ralf Baechle
*/
#ifndef __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H
#define __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H
/*
* Momentum Jaguar ATX always has the RM9000 processor.
*/
#define cpu_has_watch 1
#define cpu_has_mips16 0
#define cpu_has_divec 0
#define cpu_has_vce 0
#define cpu_has_cache_cdex_p 0
#define cpu_has_cache_cdex_s 0
#define cpu_has_prefetch 1
#define cpu_has_mcheck 0
#define cpu_has_ejtag 0
#define cpu_has_llsc 1
#define cpu_has_vtag_icache 0
#define cpu_has_dc_aliases 0
#define cpu_has_ic_fills_f_dc 0
#define cpu_has_dsp 0
#define cpu_icache_snoops_remote_store 0
#define cpu_has_nofpuex 0
#define cpu_has_64bits 1
#define cpu_has_inclusive_pcaches 0
#define cpu_dcache_line_size() 32
#define cpu_icache_line_size() 32
#define cpu_scache_line_size() 32
#define cpu_has_mips32r1 0
#define cpu_has_mips32r2 0
#define cpu_has_mips64r1 0
#define cpu_has_mips64r2 0
#endif /* __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H */
include/asm-mips/mach-ja/spaces.h deleted 100644 → 0
View file @ 1e54f778
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle
* Copyright (C) 2000, 2002 Maciej W. Rozycki
* Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc.
*/
#ifndef __ASM_MACH_JA_SPACES_H
#define __ASM_MACH_JA_SPACES_H
/*
* Memory above this physical address will be considered highmem.
*/
#define HIGHMEM_START 0x08000000UL
#include_next <spaces.h>
#endif /* __ASM_MACH_JA_SPACES_H */
include/asm-mips/serial.h
View file @ bef964e5
......@@ -81,25 +81,6 @@
#define STD_SERIAL_PORT_DEFNS
#endif /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */
#ifdef CONFIG_MOMENCO_JAGUAR_ATX
/* Ordinary NS16552 duart with a 20MHz crystal. */
#define JAGUAR_ATX_UART_CLK 20000000
#define JAGUAR_ATX_BASE_BAUD (JAGUAR_ATX_UART_CLK / 16)
#define JAGUAR_ATX_SERIAL1_IRQ 6
#define JAGUAR_ATX_SERIAL1_BASE 0xfd000023L
#define _JAGUAR_ATX_SERIAL_INIT(int, base) \
{ .baud_base = JAGUAR_ATX_BASE_BAUD, irq: int, \
.flags = (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
.iomem_base = (u8 *) base, iomem_reg_shift: 2, \
io_type: SERIAL_IO_MEM }
#define MOMENCO_JAGUAR_ATX_SERIAL_PORT_DEFNS \
_JAGUAR_ATX_SERIAL_INIT(JAGUAR_ATX_SERIAL1_IRQ, JAGUAR_ATX_SERIAL1_BASE)
#else
#define MOMENCO_JAGUAR_ATX_SERIAL_PORT_DEFNS
#endif
#ifdef CONFIG_MOMENCO_OCELOT_3
#define OCELOT_3_BASE_BAUD ( 20000000 / 16 )
#define OCELOT_3_SERIAL_IRQ 6
......
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