Commit c209d25e authored by Arnd Bergmann's avatar Arnd Bergmann

Merge tag 'omap-for-v4.16/fixes-signed' of...

Merge tag 'omap-for-v4.16/fixes-signed' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes

Fixes for omaps for v4.16-rc cycle

This is mostly SoC related fixes for clocks, interconnect, and PM with few
board specifc dts related fixes:

- Fix quirk handling for ti-sysc to check all quirk flags instead of just
  the first one

- Fix LogicPD boards for i2c1 muxing to avoid intermittent PMIC errors

- Fix debounce-interval use for omap5-uevm

- Fix debugfs_create_*() usage for omap1

- Fix sar_base initialization for HS omaps

- Fix omap3 prm wake interrupt for resume

- Fix kmemleak for omap_get_timer_dt()

- Enable optional clocks before main clock to prevent interconnect target
  module from being stuck in transition

* tag 'omap-for-v4.16/fixes-signed' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  bus: ti-sysc: Fix checking of no-reset-on-init quirk
  ARM: dts: LogicPD SOM-LV: Fix I2C1 pinmux
  ARM: dts: LogicPD Torpedo: Fix I2C1 pinmux
  ARM: dts: OMAP5: uevm: Fix "debounce-interval" property misspelling
  ARM: OMAP1: clock: Fix debugfs_create_*() usage
  ARM: OMAP2+: Fix sar_base inititalization for HS omaps
  ARM: OMAP3: Fix prm wake interrupt for resume
  ARM: OMAP2+: timer: fix a kmemleak caused in omap_get_timer_dt
  ARM: OMAP2+: hwmod_core: enable optional clocks before main clock
parents ac07b9aa d39b6ea4
......@@ -71,6 +71,8 @@ nand@0,0 {
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
clock-frequency = <2600000>;
twl: twl@48 {
......@@ -189,7 +191,12 @@ OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */
>;
};
i2c1_pins: pinmux_i2c1_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
>;
};
};
&omap3_pmx_wkup {
......
......@@ -66,6 +66,8 @@ nand@0,0 {
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
clock-frequency = <2600000>;
twl: twl@48 {
......@@ -136,6 +138,12 @@ OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT | MUX_MODE0) /* hsusb0_data6.hsusb0_data6 */
OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT | MUX_MODE0) /* hsusb0_data7.hsusb0_data7 */
>;
};
i2c1_pins: pinmux_i2c1_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */
OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */
>;
};
};
&uart2 {
......
......@@ -47,7 +47,7 @@ btn1 {
gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; /* gpio3_83 */
wakeup-source;
autorepeat;
debounce_interval = <50>;
debounce-interval = <50>;
};
};
......
......@@ -1011,17 +1011,17 @@ static int clk_debugfs_register_one(struct clk *c)
return -ENOMEM;
c->dent = d;
d = debugfs_create_u8("usecount", S_IRUGO, c->dent, (u8 *)&c->usecount);
d = debugfs_create_u8("usecount", S_IRUGO, c->dent, &c->usecount);
if (!d) {
err = -ENOMEM;
goto err_out;
}
d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate);
d = debugfs_create_ulong("rate", S_IRUGO, c->dent, &c->rate);
if (!d) {
err = -ENOMEM;
goto err_out;
}
d = debugfs_create_x32("flags", S_IRUGO, c->dent, (u32 *)&c->flags);
d = debugfs_create_x8("flags", S_IRUGO, c->dent, &c->flags);
if (!d) {
err = -ENOMEM;
goto err_out;
......
......@@ -299,8 +299,6 @@ static void irq_save_context(void)
if (soc_is_dra7xx())
return;
if (!sar_base)
sar_base = omap4_get_sar_ram_base();
if (wakeupgen_ops && wakeupgen_ops->save_context)
wakeupgen_ops->save_context();
}
......@@ -598,6 +596,8 @@ static int __init wakeupgen_init(struct device_node *node,
irq_hotplug_init();
irq_pm_init();
sar_base = omap4_get_sar_ram_base();
return 0;
}
IRQCHIP_DECLARE(ti_wakeupgen, "ti,omap4-wugen-mpu", wakeupgen_init);
......@@ -977,6 +977,9 @@ static int _enable_clocks(struct omap_hwmod *oh)
pr_debug("omap_hwmod: %s: enabling clocks\n", oh->name);
if (oh->flags & HWMOD_OPT_CLKS_NEEDED)
_enable_optional_clocks(oh);
if (oh->_clk)
clk_enable(oh->_clk);
......@@ -985,9 +988,6 @@ static int _enable_clocks(struct omap_hwmod *oh)
clk_enable(os->_clk);
}
if (oh->flags & HWMOD_OPT_CLKS_NEEDED)
_enable_optional_clocks(oh);
/* The opt clocks are controlled by the device driver. */
return 0;
......
......@@ -186,7 +186,7 @@ static void omap_pm_end(void)
cpu_idle_poll_ctrl(false);
}
static void omap_pm_finish(void)
static void omap_pm_wake(void)
{
if (soc_is_omap34xx())
omap_prcm_irq_complete();
......@@ -196,7 +196,7 @@ static const struct platform_suspend_ops omap_pm_ops = {
.begin = omap_pm_begin,
.end = omap_pm_end,
.enter = omap_pm_enter,
.finish = omap_pm_finish,
.wake = omap_pm_wake,
.valid = suspend_valid_only_mem,
};
......
......@@ -156,12 +156,6 @@ static struct clock_event_device clockevent_gpt = {
.tick_resume = omap2_gp_timer_shutdown,
};
static struct property device_disabled = {
.name = "status",
.length = sizeof("disabled"),
.value = "disabled",
};
static const struct of_device_id omap_timer_match[] __initconst = {
{ .compatible = "ti,omap2420-timer", },
{ .compatible = "ti,omap3430-timer", },
......@@ -203,8 +197,17 @@ static struct device_node * __init omap_get_timer_dt(const struct of_device_id *
of_get_property(np, "ti,timer-secure", NULL)))
continue;
if (!of_device_is_compatible(np, "ti,omap-counter32k"))
of_add_property(np, &device_disabled);
if (!of_device_is_compatible(np, "ti,omap-counter32k")) {
struct property *prop;
prop = kzalloc(sizeof(*prop), GFP_KERNEL);
if (!prop)
return NULL;
prop->name = "status";
prop->value = "disabled";
prop->length = strlen(prop->value);
of_add_property(np, prop);
}
return np;
}
......
......@@ -630,7 +630,7 @@ static int sysc_init_dts_quirks(struct sysc *ddata)
for (i = 0; i < ARRAY_SIZE(sysc_dts_quirks); i++) {
prop = of_get_property(np, sysc_dts_quirks[i].name, &len);
if (!prop)
break;
continue;
ddata->cfg.quirks |= sysc_dts_quirks[i].mask;
}
......
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