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Commit c33b1e8c authored by Ben Skeggs's avatar Ben Skeggs
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drm/gf100-/gr: tidy reg/ctx initval lists, mostly by giving them names 

Unit names come from the Android GK20A driver.
Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 64e4886b
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Showing with 1854 additions and 2063 deletions
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.h 0 → 100644
View file @ c33b1e8c
#ifndef __NVKM_GRCTX_NVC0_H__
#define __NVKM_GRCTX_NVC0_H__
#include "nvc0.h"
struct nvc0_grctx {
struct nvc0_graph_priv *priv;
struct nvc0_graph_data *data;
struct nvc0_graph_mmio *mmio;
int buffer_nr;
u64 buffer[4];
u64 addr;
};
struct nvc0_grctx_oclass {
struct nouveau_oclass base;
/* main context generation function */
void (*main)(struct nvc0_graph_priv *, struct nvc0_grctx *);
/* context-specific modify-on-first-load list generation function */
void (*mods)(struct nvc0_graph_priv *, struct nvc0_grctx *);
void (*unkn)(struct nvc0_graph_priv *);
/* mmio context data */
const struct nvc0_graph_pack *hub;
const struct nvc0_graph_pack *gpc;
const struct nvc0_graph_pack *zcull;
const struct nvc0_graph_pack *tpc;
const struct nvc0_graph_pack *ppc;
/* indirect context data, generated with icmds/mthds */
const struct nvc0_graph_pack *icmd;
const struct nvc0_graph_pack *mthd;
};
#define mmio_data(s,a,p) do { \
info->buffer[info->buffer_nr] = round_up(info->addr, (a)); \
info->addr = info->buffer[info->buffer_nr++] + (s); \
info->data->size = (s); \
info->data->align = (a); \
info->data->access = (p); \
info->data++; \
} while(0)
#define mmio_list(r,d,s,b) do { \
info->mmio->addr = (r); \
info->mmio->data = (d); \
info->mmio->shift = (s); \
info->mmio->buffer = (b); \
info->mmio++; \
nv_wr32(priv, (r), (d) | ((s) ? (info->buffer[(b)] >> (s)) : 0)); \
} while(0)
extern struct nouveau_oclass *nvc0_grctx_oclass;
int nvc0_grctx_generate(struct nvc0_graph_priv *);
void nvc0_grctx_generate_main(struct nvc0_graph_priv *, struct nvc0_grctx *);
void nvc0_grctx_generate_mods(struct nvc0_graph_priv *, struct nvc0_grctx *);
void nvc0_grctx_generate_unkn(struct nvc0_graph_priv *);
void nvc0_grctx_generate_tpcid(struct nvc0_graph_priv *);
void nvc0_grctx_generate_r406028(struct nvc0_graph_priv *);
void nvc0_grctx_generate_r4060a8(struct nvc0_graph_priv *);
void nvc0_grctx_generate_r418bb8(struct nvc0_graph_priv *);
void nvc0_grctx_generate_r406800(struct nvc0_graph_priv *);
extern struct nouveau_oclass *nvc1_grctx_oclass;
void nvc1_grctx_generate_mods(struct nvc0_graph_priv *, struct nvc0_grctx *);
void nvc1_grctx_generate_unkn(struct nvc0_graph_priv *);
extern struct nouveau_oclass *nvc4_grctx_oclass;
extern struct nouveau_oclass *nvc8_grctx_oclass;
extern struct nouveau_oclass *nvd7_grctx_oclass;
extern struct nouveau_oclass *nvd9_grctx_oclass;
extern struct nouveau_oclass *nve4_grctx_oclass;
void nve4_grctx_generate_main(struct nvc0_graph_priv *, struct nvc0_grctx *);
void nve4_grctx_generate_unkn(struct nvc0_graph_priv *);
void nve4_grctx_generate_r418bb8(struct nvc0_graph_priv *);
extern struct nouveau_oclass *nvf0_grctx_oclass;
extern struct nouveau_oclass *nv108_grctx_oclass;
/* context init value lists */
extern const struct nvc0_graph_pack nvc0_grctx_pack_icmd[];
extern const struct nvc0_graph_pack nvc0_grctx_pack_mthd[];
extern const struct nvc0_graph_init nvc0_grctx_init_902d_0[];
extern const struct nvc0_graph_init nvc0_grctx_init_9039_0[];
extern const struct nvc0_graph_init nvc0_grctx_init_90c0_0[];
extern const struct nvc0_graph_pack nvc0_grctx_pack_hub[];
extern const struct nvc0_graph_init nvc0_grctx_init_main_0[];
extern const struct nvc0_graph_init nvc0_grctx_init_fe_0[];
extern const struct nvc0_graph_init nvc0_grctx_init_pri_0[];
extern const struct nvc0_graph_init nvc0_grctx_init_memfmt_0[];
extern const struct nvc0_graph_init nvc0_grctx_init_rstr2d_0[];
extern const struct nvc0_graph_init nvc0_grctx_init_scc_0[];
extern const struct nvc0_graph_pack nvc0_grctx_pack_gpc[];
extern const struct nvc0_graph_pack nvc0_grctx_pack_zcull[];
extern const struct nvc0_graph_pack nvc0_grctx_pack_tpc[];
extern const struct nvc0_graph_init nvc1_grctx_init_9097_0[];
extern const struct nvc0_graph_init nvc8_grctx_init_9197_0[];
extern const struct nvc0_graph_init nvc8_grctx_init_9297_0[];
extern const struct nvc0_graph_pack nvd9_grctx_pack_icmd[];
extern const struct nvc0_graph_pack nvd9_grctx_pack_mthd[];
extern const struct nvc0_graph_init nvd9_grctx_init_fe_0[];
extern const struct nvc0_graph_init nvd9_grctx_init_be_0[];
extern const struct nvc0_graph_init nve4_grctx_init_memfmt_0[];
extern const struct nvc0_graph_init nve4_grctx_init_ds_0[];
extern const struct nvc0_graph_init nve4_grctx_init_scc_0[];
extern const struct nvc0_graph_pack nvf0_grctx_pack_mthd[];
extern const struct nvc0_graph_init nvf0_grctx_init_pri_0[];
extern const struct nvc0_graph_init nvf0_grctx_init_cwd_0[];
#endif
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc1.c
View file @ c33b1e8c
......@@ -22,10 +22,14 @@
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#include "nvc0.h"
#include "ctxnvc0.h"
static struct nvc0_graph_init
nvc1_grctx_init_icmd[] = {
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
static const struct nvc0_graph_init
nvc1_grctx_init_icmd_0[] = {
{ 0x001000, 1, 0x01, 0x00000004 },
{ 0x0000a9, 1, 0x01, 0x0000ffff },
{ 0x000038, 1, 0x01, 0x0fac6881 },
......@@ -141,8 +145,7 @@ nvc1_grctx_init_icmd[] = {
{ 0x000586, 1, 0x01, 0x00000040 },
{ 0x000582, 2, 0x01, 0x00000080 },
{ 0x0005c2, 1, 0x01, 0x00000001 },
{ 0x000638, 1, 0x01, 0x00000001 },
{ 0x000639, 1, 0x01, 0x00000001 },
{ 0x000638, 2, 0x01, 0x00000001 },
{ 0x00063a, 1, 0x01, 0x00000002 },
{ 0x00063b, 2, 0x01, 0x00000001 },
{ 0x00063d, 1, 0x01, 0x00000002 },
......@@ -202,15 +205,13 @@ nvc1_grctx_init_icmd[] = {
{ 0x000787, 1, 0x01, 0x000000cf },
{ 0x00078c, 1, 0x01, 0x00000008 },
{ 0x000792, 1, 0x01, 0x00000001 },
{ 0x000794, 1, 0x01, 0x00000001 },
{ 0x000795, 2, 0x01, 0x00000001 },
{ 0x000794, 3, 0x01, 0x00000001 },
{ 0x000797, 1, 0x01, 0x000000cf },
{ 0x000836, 1, 0x01, 0x00000001 },
{ 0x00079a, 1, 0x01, 0x00000002 },
{ 0x000833, 1, 0x01, 0x04444480 },
{ 0x0007a1, 1, 0x01, 0x00000001 },
{ 0x0007a3, 1, 0x01, 0x00000001 },
{ 0x0007a4, 2, 0x01, 0x00000001 },
{ 0x0007a3, 3, 0x01, 0x00000001 },
{ 0x000831, 1, 0x01, 0x00000004 },
{ 0x00080c, 1, 0x01, 0x00000002 },
{ 0x00080d, 2, 0x01, 0x00000100 },
......@@ -236,14 +237,12 @@ nvc1_grctx_init_icmd[] = {
{ 0x0006b1, 1, 0x01, 0x00000011 },
{ 0x00078c, 1, 0x01, 0x00000008 },
{ 0x000792, 1, 0x01, 0x00000001 },
{ 0x000794, 1, 0x01, 0x00000001 },
{ 0x000795, 2, 0x01, 0x00000001 },
{ 0x000794, 3, 0x01, 0x00000001 },
{ 0x000797, 1, 0x01, 0x000000cf },
{ 0x00079a, 1, 0x01, 0x00000002 },
{ 0x000833, 1, 0x01, 0x04444480 },
{ 0x0007a1, 1, 0x01, 0x00000001 },
{ 0x0007a3, 1, 0x01, 0x00000001 },
{ 0x0007a4, 2, 0x01, 0x00000001 },
{ 0x0007a3, 3, 0x01, 0x00000001 },
{ 0x000831, 1, 0x01, 0x00000004 },
{ 0x01e100, 1, 0x01, 0x00000001 },
{ 0x001000, 1, 0x01, 0x00000014 },
......@@ -268,8 +267,14 @@ nvc1_grctx_init_icmd[] = {
{}
};
struct nvc0_graph_init
nvc1_grctx_init_9097[] = {
static const struct nvc0_graph_pack
nvc1_grctx_pack_icmd[] = {
{ nvc1_grctx_init_icmd_0 },
{}
};
const struct nvc0_graph_init
nvc1_grctx_init_9097_0[] = {
{ 0x000800, 8, 0x40, 0x00000000 },
{ 0x000804, 8, 0x40, 0x00000000 },
{ 0x000808, 8, 0x40, 0x00000400 },
......@@ -516,8 +521,7 @@ nvc1_grctx_init_9097[] = {
{ 0x001350, 1, 0x04, 0x00000002 },
{ 0x001358, 1, 0x04, 0x00000001 },
{ 0x0012e4, 1, 0x04, 0x00000000 },
{ 0x00131c, 1, 0x04, 0x00000000 },
{ 0x001320, 3, 0x04, 0x00000000 },
{ 0x00131c, 4, 0x04, 0x00000000 },
{ 0x0019c0, 1, 0x04, 0x00000000 },
{ 0x001140, 1, 0x04, 0x00000000 },
{ 0x0019c4, 1, 0x04, 0x00000000 },
......@@ -571,15 +575,25 @@ nvc1_grctx_init_9097[] = {
{}
};
static struct nvc0_graph_init
nvc1_grctx_init_9197[] = {
static const struct nvc0_graph_init
nvc1_grctx_init_9197_0[] = {
{ 0x003400, 128, 0x04, 0x00000000 },
{ 0x0002e4, 1, 0x04, 0x0000b001 },
{}
};
static struct nvc0_graph_init
nvc1_grctx_init_unk58xx[] = {
static const struct nvc0_graph_pack
nvc1_grctx_pack_mthd[] = {
{ nvc1_grctx_init_9097_0, 0x9097 },
{ nvc1_grctx_init_9197_0, 0x9197 },
{ nvc0_grctx_init_902d_0, 0x902d },
{ nvc0_grctx_init_9039_0, 0x9039 },
{ nvc0_grctx_init_90c0_0, 0x90c0 },
{}
};
static const struct nvc0_graph_init
nvc1_grctx_init_ds_0[] = {
{ 0x405800, 1, 0x04, 0x0f8000bf },
{ 0x405830, 1, 0x04, 0x02180218 },
{ 0x405834, 2, 0x04, 0x00000000 },
......@@ -590,8 +604,20 @@ nvc1_grctx_init_unk58xx[] = {
{}
};
static struct nvc0_graph_init
nvc1_grctx_init_rop[] = {
static const struct nvc0_graph_init
nvc1_grctx_init_pd_0[] = {
{ 0x406020, 1, 0x04, 0x000103c1 },
{ 0x406028, 4, 0x04, 0x00000001 },
{ 0x4064a8, 1, 0x04, 0x00000000 },
{ 0x4064ac, 1, 0x04, 0x00003fff },
{ 0x4064b4, 2, 0x04, 0x00000000 },
{ 0x4064c0, 1, 0x04, 0x80140078 },
{ 0x4064c4, 1, 0x04, 0x0086ffff },
{}
};
static const struct nvc0_graph_init
nvc1_grctx_init_be_0[] = {
{ 0x408800, 1, 0x04, 0x02802a3c },
{ 0x408804, 1, 0x04, 0x00000040 },
{ 0x408808, 1, 0x04, 0x1003e005 },
......@@ -602,7 +628,21 @@ nvc1_grctx_init_rop[] = {
{}
};
static struct nvc0_graph_init
static const struct nvc0_graph_pack
nvc1_grctx_pack_hub[] = {
{ nvc0_grctx_init_main_0 },
{ nvc0_grctx_init_fe_0 },
{ nvc0_grctx_init_pri_0 },
{ nvc0_grctx_init_memfmt_0 },
{ nvc1_grctx_init_ds_0 },
{ nvc1_grctx_init_pd_0 },
{ nvc0_grctx_init_rstr2d_0 },
{ nvc0_grctx_init_scc_0 },
{ nvc1_grctx_init_be_0 },
{}
};
static const struct nvc0_graph_init
nvc1_grctx_init_gpc_0[] = {
{ 0x418380, 1, 0x04, 0x00000016 },
{ 0x418400, 1, 0x04, 0x38004e00 },
......@@ -633,30 +673,6 @@ nvc1_grctx_init_gpc_0[] = {
{ 0x418924, 1, 0x04, 0x00000000 },
{ 0x418928, 1, 0x04, 0x00ffff00 },
{ 0x41892c, 1, 0x04, 0x0000ff00 },
{ 0x418a00, 3, 0x04, 0x00000000 },
{ 0x418a0c, 1, 0x04, 0x00010000 },
{ 0x418a10, 3, 0x04, 0x00000000 },
{ 0x418a20, 3, 0x04, 0x00000000 },
{ 0x418a2c, 1, 0x04, 0x00010000 },
{ 0x418a30, 3, 0x04, 0x00000000 },
{ 0x418a40, 3, 0x04, 0x00000000 },
{ 0x418a4c, 1, 0x04, 0x00010000 },
{ 0x418a50, 3, 0x04, 0x00000000 },
{ 0x418a60, 3, 0x04, 0x00000000 },
{ 0x418a6c, 1, 0x04, 0x00010000 },
{ 0x418a70, 3, 0x04, 0x00000000 },
{ 0x418a80, 3, 0x04, 0x00000000 },
{ 0x418a8c, 1, 0x04, 0x00010000 },
{ 0x418a90, 3, 0x04, 0x00000000 },
{ 0x418aa0, 3, 0x04, 0x00000000 },
{ 0x418aac, 1, 0x04, 0x00010000 },
{ 0x418ab0, 3, 0x04, 0x00000000 },
{ 0x418ac0, 3, 0x04, 0x00000000 },
{ 0x418acc, 1, 0x04, 0x00010000 },
{ 0x418ad0, 3, 0x04, 0x00000000 },
{ 0x418ae0, 3, 0x04, 0x00000000 },
{ 0x418aec, 1, 0x04, 0x00010000 },
{ 0x418af0, 3, 0x04, 0x00000000 },
{ 0x418b00, 1, 0x04, 0x00000000 },
{ 0x418b08, 1, 0x04, 0x0a418820 },
{ 0x418b0c, 1, 0x04, 0x062080e6 },
......@@ -676,8 +692,14 @@ nvc1_grctx_init_gpc_0[] = {
{}
};
static struct nvc0_graph_init
nvc1_grctx_init_tpc[] = {
static const struct nvc0_graph_pack
nvc1_grctx_pack_gpc[] = {
{ nvc1_grctx_init_gpc_0 },
{}
};
static const struct nvc0_graph_init
nvc1_grctx_init_tpc_0[] = {
{ 0x419818, 1, 0x04, 0x00000000 },
{ 0x41983c, 1, 0x04, 0x00038bc7 },
{ 0x419848, 1, 0x04, 0x00000000 },
......@@ -723,6 +745,16 @@ nvc1_grctx_init_tpc[] = {
{}
};
static const struct nvc0_graph_pack
nvc1_grctx_pack_tpc[] = {
{ nvc1_grctx_init_tpc_0 },
{}
};
/*******************************************************************************
* PGRAPH context implementation
******************************************************************************/
void
nvc1_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
{
......@@ -771,41 +803,6 @@ nvc1_grctx_generate_unkn(struct nvc0_graph_priv *priv)
nv_mask(priv, 0x419c00, 0x00000008, 0x00000008);
}
static struct nvc0_graph_init *
nvc1_grctx_init_hub[] = {
nvc0_grctx_init_base,
nvc0_grctx_init_unk40xx,
nvc0_grctx_init_unk44xx,
nvc0_grctx_init_unk46xx,
nvc0_grctx_init_unk47xx,
nvc1_grctx_init_unk58xx,
nvc0_grctx_init_unk60xx,
nvc0_grctx_init_unk64xx,
nvc0_grctx_init_unk78xx,
nvc0_grctx_init_unk80xx,
nvc1_grctx_init_rop,
NULL
};
struct nvc0_graph_init *
nvc1_grctx_init_gpc[] = {
nvc1_grctx_init_gpc_0,
nvc0_grctx_init_gpc_1,
nvc1_grctx_init_tpc,
NULL
};
static struct nvc0_graph_mthd
nvc1_grctx_init_mthd[] = {
{ 0x9097, nvc1_grctx_init_9097, },
{ 0x9197, nvc1_grctx_init_9197, },
{ 0x902d, nvc0_grctx_init_902d, },
{ 0x9039, nvc0_grctx_init_9039, },
{ 0x90c0, nvc0_grctx_init_90c0, },
{ 0x902d, nvc0_grctx_init_mthd_magic, },
{}
};
struct nouveau_oclass *
nvc1_grctx_oclass = &(struct nvc0_grctx_oclass) {
.base.handle = NV_ENGCTX(GR, 0xc1),
......@@ -817,11 +814,13 @@ nvc1_grctx_oclass = &(struct nvc0_grctx_oclass) {
.rd32 = _nouveau_graph_context_rd32,
.wr32 = _nouveau_graph_context_wr32,
},
.main = nvc0_grctx_generate_main,
.mods = nvc1_grctx_generate_mods,
.unkn = nvc1_grctx_generate_unkn,
.hub = nvc1_grctx_init_hub,
.gpc = nvc1_grctx_init_gpc,
.icmd = nvc1_grctx_init_icmd,
.mthd = nvc1_grctx_init_mthd,
.main = nvc0_grctx_generate_main,
.mods = nvc1_grctx_generate_mods,
.unkn = nvc1_grctx_generate_unkn,
.hub = nvc1_grctx_pack_hub,
.gpc = nvc1_grctx_pack_gpc,
.zcull = nvc0_grctx_pack_zcull,
.tpc = nvc1_grctx_pack_tpc,
.icmd = nvc1_grctx_pack_icmd,
.mthd = nvc1_grctx_pack_mthd,
}.base;
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc4.c
View file @ c33b1e8c
......@@ -22,10 +22,14 @@
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#include "nvc0.h"
#include "ctxnvc0.h"
static struct nvc0_graph_init
nvc4_grctx_init_tpc[] = {
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
static const struct nvc0_graph_init
nvc4_grctx_init_tpc_0[] = {
{ 0x419818, 1, 0x04, 0x00000000 },
{ 0x41983c, 1, 0x04, 0x00038bc7 },
{ 0x419848, 1, 0x04, 0x00000000 },
......@@ -70,14 +74,16 @@ nvc4_grctx_init_tpc[] = {
{}
};
struct nvc0_graph_init *
nvc4_grctx_init_gpc[] = {
nvc0_grctx_init_gpc_0,
nvc0_grctx_init_gpc_1,
nvc4_grctx_init_tpc,
NULL
static const struct nvc0_graph_pack
nvc4_grctx_pack_tpc[] = {
{ nvc4_grctx_init_tpc_0 },
{}
};
/*******************************************************************************
* PGRAPH context implementation
******************************************************************************/
struct nouveau_oclass *
nvc4_grctx_oclass = &(struct nvc0_grctx_oclass) {
.base.handle = NV_ENGCTX(GR, 0xc3),
......@@ -89,11 +95,13 @@ nvc4_grctx_oclass = &(struct nvc0_grctx_oclass) {
.rd32 = _nouveau_graph_context_rd32,
.wr32 = _nouveau_graph_context_wr32,
},
.main = nvc0_grctx_generate_main,
.mods = nvc0_grctx_generate_mods,
.unkn = nvc0_grctx_generate_unkn,
.hub = nvc0_grctx_init_hub,
.gpc = nvc4_grctx_init_gpc,
.icmd = nvc0_grctx_init_icmd,
.mthd = nvc0_grctx_init_mthd,
.main = nvc0_grctx_generate_main,
.mods = nvc0_grctx_generate_mods,
.unkn = nvc0_grctx_generate_unkn,
.hub = nvc0_grctx_pack_hub,
.gpc = nvc0_grctx_pack_gpc,
.zcull = nvc0_grctx_pack_zcull,
.tpc = nvc4_grctx_pack_tpc,
.icmd = nvc0_grctx_pack_icmd,
.mthd = nvc0_grctx_pack_mthd,
}.base;
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc8.c
View file @ c33b1e8c
......@@ -22,10 +22,14 @@
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#include "nvc0.h"
#include "ctxnvc0.h"
static struct nvc0_graph_init
nvc8_grctx_init_icmd[] = {
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
static const struct nvc0_graph_init
nvc8_grctx_init_icmd_0[] = {
{ 0x001000, 1, 0x01, 0x00000004 },
{ 0x0000a9, 1, 0x01, 0x0000ffff },
{ 0x000038, 1, 0x01, 0x0fac6881 },
......@@ -141,8 +145,7 @@ nvc8_grctx_init_icmd[] = {
{ 0x000586, 1, 0x01, 0x00000040 },
{ 0x000582, 2, 0x01, 0x00000080 },
{ 0x0005c2, 1, 0x01, 0x00000001 },
{ 0x000638, 1, 0x01, 0x00000001 },
{ 0x000639, 1, 0x01, 0x00000001 },
{ 0x000638, 2, 0x01, 0x00000001 },
{ 0x00063a, 1, 0x01, 0x00000002 },
{ 0x00063b, 2, 0x01, 0x00000001 },
{ 0x00063d, 1, 0x01, 0x00000002 },
......@@ -203,15 +206,13 @@ nvc8_grctx_init_icmd[] = {
{ 0x000787, 1, 0x01, 0x000000cf },
{ 0x00078c, 1, 0x01, 0x00000008 },
{ 0x000792, 1, 0x01, 0x00000001 },
{ 0x000794, 1, 0x01, 0x00000001 },
{ 0x000795, 2, 0x01, 0x00000001 },
{ 0x000794, 3, 0x01, 0x00000001 },
{ 0x000797, 1, 0x01, 0x000000cf },
{ 0x000836, 1, 0x01, 0x00000001 },
{ 0x00079a, 1, 0x01, 0x00000002 },
{ 0x000833, 1, 0x01, 0x04444480 },
{ 0x0007a1, 1, 0x01, 0x00000001 },
{ 0x0007a3, 1, 0x01, 0x00000001 },
{ 0x0007a4, 2, 0x01, 0x00000001 },
{ 0x0007a3, 3, 0x01, 0x00000001 },
{ 0x000831, 1, 0x01, 0x00000004 },
{ 0x00080c, 1, 0x01, 0x00000002 },
{ 0x00080d, 2, 0x01, 0x00000100 },
......@@ -237,14 +238,12 @@ nvc8_grctx_init_icmd[] = {
{ 0x0006b1, 1, 0x01, 0x00000011 },
{ 0x00078c, 1, 0x01, 0x00000008 },
{ 0x000792, 1, 0x01, 0x00000001 },
{ 0x000794, 1, 0x01, 0x00000001 },
{ 0x000795, 2, 0x01, 0x00000001 },
{ 0x000794, 3, 0x01, 0x00000001 },
{ 0x000797, 1, 0x01, 0x000000cf },
{ 0x00079a, 1, 0x01, 0x00000002 },
{ 0x000833, 1, 0x01, 0x04444480 },
{ 0x0007a1, 1, 0x01, 0x00000001 },
{ 0x0007a3, 1, 0x01, 0x00000001 },
{ 0x0007a4, 2, 0x01, 0x00000001 },
{ 0x0007a3, 3, 0x01, 0x00000001 },
{ 0x000831, 1, 0x01, 0x00000004 },
{ 0x01e100, 1, 0x01, 0x00000001 },
{ 0x001000, 1, 0x01, 0x00000014 },
......@@ -269,7 +268,40 @@ nvc8_grctx_init_icmd[] = {
{}
};
static struct nvc0_graph_init
static const struct nvc0_graph_pack
nvc8_grctx_pack_icmd[] = {
{ nvc8_grctx_init_icmd_0 },
{}
};
const struct nvc0_graph_init
nvc8_grctx_init_9197_0[] = {
{ 0x0002e4, 1, 0x04, 0x0000b001 },
{}
};
const struct nvc0_graph_init
nvc8_grctx_init_9297_0[] = {
{ 0x003400, 128, 0x04, 0x00000000 },
{ 0x00036c, 2, 0x04, 0x00000000 },
{ 0x0007a4, 2, 0x04, 0x00000000 },
{ 0x000374, 1, 0x04, 0x00000000 },
{ 0x000378, 1, 0x04, 0x00000020 },
{}
};
static const struct nvc0_graph_pack
nvc8_grctx_pack_mthd[] = {
{ nvc1_grctx_init_9097_0, 0x9097 },
{ nvc8_grctx_init_9197_0, 0x9197 },
{ nvc8_grctx_init_9297_0, 0x9297 },
{ nvc0_grctx_init_902d_0, 0x902d },
{ nvc0_grctx_init_9039_0, 0x9039 },
{ nvc0_grctx_init_90c0_0, 0x90c0 },
{}
};
static const struct nvc0_graph_init
nvc8_grctx_init_gpc_0[] = {
{ 0x418380, 1, 0x04, 0x00000016 },
{ 0x418400, 1, 0x04, 0x38004e00 },
......@@ -318,41 +350,15 @@ nvc8_grctx_init_gpc_0[] = {
{}
};
struct nvc0_graph_init
nvc8_grctx_init_9197[] = {
{ 0x0002e4, 1, 0x04, 0x0000b001 },
{}
};
struct nvc0_graph_init
nvc8_grctx_init_9297[] = {
{ 0x003400, 128, 0x04, 0x00000000 },
{ 0x00036c, 2, 0x04, 0x00000000 },
{ 0x0007a4, 2, 0x04, 0x00000000 },
{ 0x000374, 1, 0x04, 0x00000000 },
{ 0x000378, 1, 0x04, 0x00000020 },
{}
};
static struct nvc0_graph_mthd
nvc8_grctx_init_mthd[] = {
{ 0x9097, nvc1_grctx_init_9097, },
{ 0x9197, nvc8_grctx_init_9197, },
{ 0x9297, nvc8_grctx_init_9297, },
{ 0x902d, nvc0_grctx_init_902d, },
{ 0x9039, nvc0_grctx_init_9039, },
{ 0x90c0, nvc0_grctx_init_90c0, },
{ 0x902d, nvc0_grctx_init_mthd_magic, },
static const struct nvc0_graph_pack
nvc8_grctx_pack_gpc[] = {
{ nvc8_grctx_init_gpc_0 },
{}
};
static struct nvc0_graph_init *
nvc8_grctx_init_gpc[] = {
nvc8_grctx_init_gpc_0,
nvc0_grctx_init_gpc_1,
nvc0_grctx_init_tpc,
NULL
};
/*******************************************************************************
* PGRAPH context implementation
******************************************************************************/
struct nouveau_oclass *
nvc8_grctx_oclass = &(struct nvc0_grctx_oclass) {
......@@ -365,11 +371,13 @@ nvc8_grctx_oclass = &(struct nvc0_grctx_oclass) {
.rd32 = _nouveau_graph_context_rd32,
.wr32 = _nouveau_graph_context_wr32,
},
.main = nvc0_grctx_generate_main,
.mods = nvc0_grctx_generate_mods,
.unkn = nvc0_grctx_generate_unkn,
.hub = nvc0_grctx_init_hub,
.gpc = nvc8_grctx_init_gpc,
.icmd = nvc8_grctx_init_icmd,
.mthd = nvc8_grctx_init_mthd,
.main = nvc0_grctx_generate_main,
.mods = nvc0_grctx_generate_mods,
.unkn = nvc0_grctx_generate_unkn,
.hub = nvc0_grctx_pack_hub,
.gpc = nvc8_grctx_pack_gpc,
.zcull = nvc0_grctx_pack_zcull,
.tpc = nvc0_grctx_pack_tpc,
.icmd = nvc8_grctx_pack_icmd,
.mthd = nvc8_grctx_pack_mthd,
}.base;
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd7.c
View file @ c33b1e8c
......@@ -22,33 +22,14 @@
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#include "nvc0.h"
#include "ctxnvc0.h"
struct nvc0_graph_init
nvd7_grctx_init_unk40xx[] = {
{ 0x404004, 10, 0x04, 0x00000000 },
{ 0x404044, 1, 0x04, 0x00000000 },
{ 0x404094, 1, 0x04, 0x00000000 },
{ 0x404098, 12, 0x04, 0x00000000 },
{ 0x4040c8, 1, 0x04, 0xf0000087 },
{ 0x4040d0, 6, 0x04, 0x00000000 },
{ 0x4040e8, 1, 0x04, 0x00001000 },
{ 0x4040f8, 1, 0x04, 0x00000000 },
{ 0x404130, 1, 0x04, 0x00000000 },
{ 0x404134, 1, 0x04, 0x00000000 },
{ 0x404138, 1, 0x04, 0x20000040 },
{ 0x404150, 1, 0x04, 0x0000002e },
{ 0x404154, 1, 0x04, 0x00000400 },
{ 0x404158, 1, 0x04, 0x00000200 },
{ 0x404164, 1, 0x04, 0x00000055 },
{ 0x404168, 1, 0x04, 0x00000000 },
{ 0x404178, 2, 0x04, 0x00000000 },
{ 0x404200, 8, 0x04, 0x00000000 },
{}
};
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
static struct nvc0_graph_init
nvd7_grctx_init_unk58xx[] = {
static const struct nvc0_graph_init
nvd7_grctx_init_ds_0[] = {
{ 0x405800, 1, 0x04, 0x0f8000bf },
{ 0x405830, 1, 0x04, 0x02180324 },
{ 0x405834, 1, 0x04, 0x08000000 },
......@@ -60,8 +41,10 @@ nvd7_grctx_init_unk58xx[] = {
{}
};
static struct nvc0_graph_init
nvd7_grctx_init_unk64xx[] = {
static const struct nvc0_graph_init
nvd7_grctx_init_pd_0[] = {
{ 0x406020, 1, 0x04, 0x000103c1 },
{ 0x406028, 4, 0x04, 0x00000001 },
{ 0x4064a8, 1, 0x04, 0x00000000 },
{ 0x4064ac, 1, 0x04, 0x00003fff },
{ 0x4064b4, 3, 0x04, 0x00000000 },
......@@ -71,7 +54,21 @@ nvd7_grctx_init_unk64xx[] = {
{}
};
static struct nvc0_graph_init
static const struct nvc0_graph_pack
nvd7_grctx_pack_hub[] = {
{ nvc0_grctx_init_main_0 },
{ nvd9_grctx_init_fe_0 },
{ nvc0_grctx_init_pri_0 },
{ nvc0_grctx_init_memfmt_0 },
{ nvd7_grctx_init_ds_0 },
{ nvd7_grctx_init_pd_0 },
{ nvc0_grctx_init_rstr2d_0 },
{ nvc0_grctx_init_scc_0 },
{ nvd9_grctx_init_be_0 },
{}
};
static const struct nvc0_graph_init
nvd7_grctx_init_gpc_0[] = {
{ 0x418380, 1, 0x04, 0x00000016 },
{ 0x418400, 1, 0x04, 0x38004e00 },
......@@ -118,8 +115,14 @@ nvd7_grctx_init_gpc_0[] = {
{}
};
static struct nvc0_graph_init
nvd7_grctx_init_tpc[] = {
static const struct nvc0_graph_pack
nvd7_grctx_pack_gpc[] = {
{ nvd7_grctx_init_gpc_0 },
{}
};
static const struct nvc0_graph_init
nvd7_grctx_init_tpc_0[] = {
{ 0x419848, 1, 0x04, 0x00000000 },
{ 0x419864, 1, 0x04, 0x00000129 },
{ 0x419888, 1, 0x04, 0x00000000 },
......@@ -153,8 +156,14 @@ nvd7_grctx_init_tpc[] = {
{}
};
static struct nvc0_graph_init
nvd7_grctx_init_unk[] = {
static const struct nvc0_graph_pack
nvd7_grctx_pack_tpc[] = {
{ nvd7_grctx_init_tpc_0 },
{}
};
static const struct nvc0_graph_init
nvd7_grctx_init_ppc_0[] = {
{ 0x41be24, 1, 0x04, 0x00000002 },
{ 0x41bec0, 1, 0x04, 0x12180000 },
{ 0x41bec4, 1, 0x04, 0x00003fff },
......@@ -171,6 +180,16 @@ nvd7_grctx_init_unk[] = {
{}
};
static const struct nvc0_graph_pack
nvd7_grctx_pack_ppc[] = {
{ nvd7_grctx_init_ppc_0 },
{}
};
/*******************************************************************************
* PGRAPH context implementation
******************************************************************************/
static void
nvd7_grctx_generate_mods(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
{
......@@ -219,10 +238,11 @@ nvd7_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
nv_mask(priv, 0x000260, 0x00000001, 0x00000000);
for (i = 0; oclass->hub[i]; i++)
nvc0_graph_mmio(priv, oclass->hub[i]);
for (i = 0; oclass->gpc[i]; i++)
nvc0_graph_mmio(priv, oclass->gpc[i]);
nvc0_graph_mmio(priv, oclass->hub);
nvc0_graph_mmio(priv, oclass->gpc);
nvc0_graph_mmio(priv, oclass->zcull);
nvc0_graph_mmio(priv, oclass->tpc);
nvc0_graph_mmio(priv, oclass->ppc);
nv_wr32(priv, 0x404154, 0x00000000);
......@@ -244,32 +264,6 @@ nvd7_grctx_generate_main(struct nvc0_graph_priv *priv, struct nvc0_grctx *info)
nv_mask(priv, 0x000260, 0x00000001, 0x00000001);
}
static struct nvc0_graph_init *
nvd7_grctx_init_hub[] = {
nvc0_grctx_init_base,
nvd7_grctx_init_unk40xx,
nvc0_grctx_init_unk44xx,
nvc0_grctx_init_unk46xx,
nvc0_grctx_init_unk47xx,
nvd7_grctx_init_unk58xx,
nvc0_grctx_init_unk60xx,
nvd7_grctx_init_unk64xx,
nvc0_grctx_init_unk78xx,
nvc0_grctx_init_unk80xx,
nvd9_grctx_init_rop,
NULL
};
struct nvc0_graph_init *
nvd7_grctx_init_gpc[] = {
nvd7_grctx_init_gpc_0,
nvc0_grctx_init_gpc_1,
nvd7_grctx_init_tpc,
nvd7_grctx_init_unk,
NULL
};
struct nouveau_oclass *
nvd7_grctx_oclass = &(struct nvc0_grctx_oclass) {
.base.handle = NV_ENGCTX(GR, 0xd7),
......@@ -281,11 +275,14 @@ nvd7_grctx_oclass = &(struct nvc0_grctx_oclass) {
.rd32 = _nouveau_graph_context_rd32,
.wr32 = _nouveau_graph_context_wr32,
},
.main = nvd7_grctx_generate_main,
.mods = nvd7_grctx_generate_mods,
.unkn = nve4_grctx_generate_unkn,
.hub = nvd7_grctx_init_hub,
.gpc = nvd7_grctx_init_gpc,
.icmd = nvd9_grctx_init_icmd,
.mthd = nvd9_grctx_init_mthd,
.main = nvd7_grctx_generate_main,
.mods = nvd7_grctx_generate_mods,
.unkn = nve4_grctx_generate_unkn,
.hub = nvd7_grctx_pack_hub,
.gpc = nvd7_grctx_pack_gpc,
.zcull = nvc0_grctx_pack_zcull,
.tpc = nvd7_grctx_pack_tpc,
.ppc = nvd7_grctx_pack_ppc,
.icmd = nvd9_grctx_pack_icmd,
.mthd = nvd9_grctx_pack_mthd,
}.base;
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd9.c
View file @ c33b1e8c
......@@ -22,38 +22,14 @@
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#include "nvc0.h"
#include "ctxnvc0.h"
struct nvc0_graph_init
nvd9_grctx_init_90c0[] = {
{ 0x002700, 4, 0x40, 0x00000000 },
{ 0x002720, 4, 0x40, 0x00000000 },
{ 0x002704, 4, 0x40, 0x00000000 },
{ 0x002724, 4, 0x40, 0x00000000 },
{ 0x002708, 4, 0x40, 0x00000000 },
{ 0x002728, 4, 0x40, 0x00000000 },
{ 0x00270c, 8, 0x20, 0x00000000 },
{ 0x002710, 4, 0x40, 0x00014000 },
{ 0x002730, 4, 0x40, 0x00014000 },
{ 0x002714, 4, 0x40, 0x00000040 },
{ 0x002734, 4, 0x40, 0x00000040 },
{ 0x00030c, 1, 0x04, 0x00000001 },
{ 0x001944, 1, 0x04, 0x00000000 },
{ 0x000758, 1, 0x04, 0x00000100 },
{ 0x0002c4, 1, 0x04, 0x00000000 },
{ 0x000790, 5, 0x04, 0x00000000 },
{ 0x00077c, 1, 0x04, 0x00000000 },
{ 0x000204, 3, 0x04, 0x00000000 },
{ 0x000214, 1, 0x04, 0x00000000 },
{ 0x00024c, 1, 0x04, 0x00000000 },
{ 0x000d94, 1, 0x04, 0x00000001 },
{ 0x001608, 2, 0x04, 0x00000000 },
{ 0x001664, 1, 0x04, 0x00000000 },
{}
};
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
struct nvc0_graph_init
nvd9_grctx_init_icmd[] = {
static const struct nvc0_graph_init
nvd9_grctx_init_icmd_0[] = {
{ 0x001000, 1, 0x01, 0x00000004 },
{ 0x0000a9, 1, 0x01, 0x0000ffff },
{ 0x000038, 1, 0x01, 0x0fac6881 },
......@@ -171,8 +147,7 @@ nvd9_grctx_init_icmd[] = {
{ 0x000586, 1, 0x01, 0x00000040 },
{ 0x000582, 2, 0x01, 0x00000080 },
{ 0x0005c2, 1, 0x01, 0x00000001 },
{ 0x000638, 1, 0x01, 0x00000001 },
{ 0x000639, 1, 0x01, 0x00000001 },
{ 0x000638, 2, 0x01, 0x00000001 },
{ 0x00063a, 1, 0x01, 0x00000002 },
{ 0x00063b, 2, 0x01, 0x00000001 },
{ 0x00063d, 1, 0x01, 0x00000002 },
......@@ -233,15 +208,13 @@ nvd9_grctx_init_icmd[] = {
{ 0x000787, 1, 0x01, 0x000000cf },
{ 0x00078c, 1, 0x01, 0x00000008 },
{ 0x000792, 1, 0x01, 0x00000001 },
{ 0x000794, 1, 0x01, 0x00000001 },
{ 0x000795, 2, 0x01, 0x00000001 },
{ 0x000794, 3, 0x01, 0x00000001 },
{ 0x000797, 1, 0x01, 0x000000cf },
{ 0x000836, 1, 0x01, 0x00000001 },
{ 0x00079a, 1, 0x01, 0x00000002 },
{ 0x000833, 1, 0x01, 0x04444480 },
{ 0x0007a1, 1, 0x01, 0x00000001 },
{ 0x0007a3, 1, 0x01, 0x00000001 },
{ 0x0007a4, 2, 0x01, 0x00000001 },
{ 0x0007a3, 3, 0x01, 0x00000001 },
{ 0x000831, 1, 0x01, 0x00000004 },
{ 0x00080c, 1, 0x01, 0x00000002 },
{ 0x00080d, 2, 0x01, 0x00000100 },
......@@ -267,14 +240,12 @@ nvd9_grctx_init_icmd[] = {
{ 0x0006b1, 1, 0x01, 0x00000011 },
{ 0x00078c, 1, 0x01, 0x00000008 },
{ 0x000792, 1, 0x01, 0x00000001 },
{ 0x000794, 1, 0x01, 0x00000001 },
{ 0x000795, 2, 0x01, 0x00000001 },
{ 0x000794, 3, 0x01, 0x00000001 },
{ 0x000797, 1, 0x01, 0x000000cf },
{ 0x00079a, 1, 0x01, 0x00000002 },
{ 0x000833, 1, 0x01, 0x04444480 },
{ 0x0007a1, 1, 0x01, 0x00000001 },
{ 0x0007a3, 1, 0x01, 0x00000001 },
{ 0x0007a4, 2, 0x01, 0x00000001 },
{ 0x0007a3, 3, 0x01, 0x00000001 },
{ 0x000831, 1, 0x01, 0x00000004 },
{ 0x01e100, 1, 0x01, 0x00000001 },
{ 0x001000, 1, 0x01, 0x00000014 },
......@@ -299,18 +270,56 @@ nvd9_grctx_init_icmd[] = {
{}
};
struct nvc0_graph_init
nvd9_grctx_init_unk40xx[] = {
{ 0x404004, 11, 0x04, 0x00000000 },
const struct nvc0_graph_pack
nvd9_grctx_pack_icmd[] = {
{ nvd9_grctx_init_icmd_0 },
{}
};
static const struct nvc0_graph_init
nvd9_grctx_init_90c0_0[] = {
{ 0x002700, 8, 0x20, 0x00000000 },
{ 0x002704, 8, 0x20, 0x00000000 },
{ 0x002708, 8, 0x20, 0x00000000 },
{ 0x00270c, 8, 0x20, 0x00000000 },
{ 0x002710, 8, 0x20, 0x00014000 },
{ 0x002714, 8, 0x20, 0x00000040 },
{ 0x00030c, 1, 0x04, 0x00000001 },
{ 0x001944, 1, 0x04, 0x00000000 },
{ 0x000758, 1, 0x04, 0x00000100 },
{ 0x0002c4, 1, 0x04, 0x00000000 },
{ 0x000790, 5, 0x04, 0x00000000 },
{ 0x00077c, 1, 0x04, 0x00000000 },
{ 0x000204, 3, 0x04, 0x00000000 },
{ 0x000214, 1, 0x04, 0x00000000 },
{ 0x00024c, 1, 0x04, 0x00000000 },
{ 0x000d94, 1, 0x04, 0x00000001 },
{ 0x001608, 2, 0x04, 0x00000000 },
{ 0x001664, 1, 0x04, 0x00000000 },
{}
};
const struct nvc0_graph_pack
nvd9_grctx_pack_mthd[] = {
{ nvc1_grctx_init_9097_0, 0x9097 },
{ nvc8_grctx_init_9197_0, 0x9197 },
{ nvc8_grctx_init_9297_0, 0x9297 },
{ nvc0_grctx_init_902d_0, 0x902d },
{ nvc0_grctx_init_9039_0, 0x9039 },
{ nvd9_grctx_init_90c0_0, 0x90c0 },
{}
};
const struct nvc0_graph_init
nvd9_grctx_init_fe_0[] = {
{ 0x404004, 10, 0x04, 0x00000000 },
{ 0x404044, 1, 0x04, 0x00000000 },
{ 0x404094, 1, 0x04, 0x00000000 },
{ 0x404098, 12, 0x04, 0x00000000 },
{ 0x404094, 13, 0x04, 0x00000000 },
{ 0x4040c8, 1, 0x04, 0xf0000087 },
{ 0x4040d0, 6, 0x04, 0x00000000 },
{ 0x4040e8, 1, 0x04, 0x00001000 },
{ 0x4040f8, 1, 0x04, 0x00000000 },
{ 0x404130, 1, 0x04, 0x00000000 },
{ 0x404134, 1, 0x04, 0x00000000 },
{ 0x404130, 2, 0x04, 0x00000000 },
{ 0x404138, 1, 0x04, 0x20000040 },
{ 0x404150, 1, 0x04, 0x0000002e },
{ 0x404154, 1, 0x04, 0x00000400 },
......@@ -322,8 +331,8 @@ nvd9_grctx_init_unk40xx[] = {
{}
};
static struct nvc0_graph_init
nvd9_grctx_init_unk58xx[] = {
static const struct nvc0_graph_init
nvd9_grctx_init_ds_0[] = {
{ 0x405800, 1, 0x04, 0x0f8000bf },
{ 0x405830, 1, 0x04, 0x02180218 },
{ 0x405834, 1, 0x04, 0x08000000 },
......@@ -335,8 +344,10 @@ nvd9_grctx_init_unk58xx[] = {
{}
};
static struct nvc0_graph_init
nvd9_grctx_init_unk64xx[] = {
static const struct nvc0_graph_init
nvd9_grctx_init_pd_0[] = {
{ 0x406020, 1, 0x04, 0x000103c1 },
{ 0x406028, 4, 0x04, 0x00000001 },
{ 0x4064a8, 1, 0x04, 0x00000000 },
{ 0x4064ac, 1, 0x04, 0x00003fff },
{ 0x4064b4, 3, 0x04, 0x00000000 },
......@@ -345,8 +356,8 @@ nvd9_grctx_init_unk64xx[] = {
{}
};
struct nvc0_graph_init
nvd9_grctx_init_rop[] = {
const struct nvc0_graph_init
nvd9_grctx_init_be_0[] = {
{ 0x408800, 1, 0x04, 0x02802a3c },
{ 0x408804, 1, 0x04, 0x00000040 },
{ 0x408808, 1, 0x04, 0x1043e005 },
......@@ -357,7 +368,21 @@ nvd9_grctx_init_rop[] = {
{}
};
static struct nvc0_graph_init
static const struct nvc0_graph_pack
nvd9_grctx_pack_hub[] = {
{ nvc0_grctx_init_main_0 },
{ nvd9_grctx_init_fe_0 },
{ nvc0_grctx_init_pri_0 },
{ nvc0_grctx_init_memfmt_0 },
{ nvd9_grctx_init_ds_0 },
{ nvd9_grctx_init_pd_0 },
{ nvc0_grctx_init_rstr2d_0 },
{ nvc0_grctx_init_scc_0 },
{ nvd9_grctx_init_be_0 },
{}
};
static const struct nvc0_graph_init
nvd9_grctx_init_gpc_0[] = {
{ 0x418380, 1, 0x04, 0x00000016 },
{ 0x418400, 1, 0x04, 0x38004e00 },
......@@ -404,8 +429,14 @@ nvd9_grctx_init_gpc_0[] = {
{}
};
static struct nvc0_graph_init
nvd9_grctx_init_tpc[] = {
static const struct nvc0_graph_pack
nvd9_grctx_pack_gpc[] = {
{ nvd9_grctx_init_gpc_0 },
{}
};
static const struct nvc0_graph_init
nvd9_grctx_init_tpc_0[] = {
{ 0x419818, 1, 0x04, 0x00000000 },
{ 0x41983c, 1, 0x04, 0x00038bc7 },
{ 0x419848, 1, 0x04, 0x00000000 },
......@@ -453,47 +484,15 @@ nvd9_grctx_init_tpc[] = {
{}
};
static struct nvc0_graph_init *
nvd9_grctx_init_hub[] = {
nvc0_grctx_init_base,
nvd9_grctx_init_unk40xx,
nvc0_grctx_init_unk44xx,
nvc0_grctx_init_unk46xx,
nvc0_grctx_init_unk47xx,
nvd9_grctx_init_unk58xx,
nvc0_grctx_init_unk60xx,
nvd9_grctx_init_unk64xx,
nvc0_grctx_init_unk78xx,
nvc0_grctx_init_unk80xx,
nvd9_grctx_init_rop,
NULL
};
struct nvc0_graph_init *
nvd9_grctx_init_gpc[] = {
nvd9_grctx_init_gpc_0,
nvc0_grctx_init_gpc_1,
nvd9_grctx_init_tpc,
NULL
};
struct nvc0_graph_init
nvd9_grctx_init_mthd_magic[] = {
{ 0x3410, 1, 0x04, 0x80002006 },
static const struct nvc0_graph_pack
nvd9_grctx_pack_tpc[] = {
{ nvd9_grctx_init_tpc_0 },
{}
};
struct nvc0_graph_mthd
nvd9_grctx_init_mthd[] = {
{ 0x9097, nvc1_grctx_init_9097, },
{ 0x9197, nvc8_grctx_init_9197, },
{ 0x9297, nvc8_grctx_init_9297, },
{ 0x902d, nvc0_grctx_init_902d, },
{ 0x9039, nvc0_grctx_init_9039, },
{ 0x90c0, nvd9_grctx_init_90c0, },
{ 0x902d, nvd9_grctx_init_mthd_magic, },
{}
};
/*******************************************************************************
* PGRAPH context implementation
******************************************************************************/
struct nouveau_oclass *
nvd9_grctx_oclass = &(struct nvc0_grctx_oclass) {
......@@ -506,11 +505,13 @@ nvd9_grctx_oclass = &(struct nvc0_grctx_oclass) {
.rd32 = _nouveau_graph_context_rd32,
.wr32 = _nouveau_graph_context_wr32,
},
.main = nvc0_grctx_generate_main,
.mods = nvc1_grctx_generate_mods,
.unkn = nvc1_grctx_generate_unkn,
.hub = nvd9_grctx_init_hub,
.gpc = nvd9_grctx_init_gpc,
.icmd = nvd9_grctx_init_icmd,
.mthd = nvd9_grctx_init_mthd,
.main = nvc0_grctx_generate_main,
.mods = nvc1_grctx_generate_mods,
.unkn = nvc1_grctx_generate_unkn,
.hub = nvd9_grctx_pack_hub,
.gpc = nvd9_grctx_pack_gpc,
.zcull = nvc0_grctx_pack_zcull,
.tpc = nvd9_grctx_pack_tpc,
.icmd = nvd9_grctx_pack_icmd,
.mthd = nvd9_grctx_pack_mthd,
}.base;
drivers/gpu/drm/nouveau/core/engine/graph/nv108.c
View file @ c33b1e8c
......@@ -23,6 +23,7 @@
*/
#include "nvc0.h"
#include "ctxnvc0.h"
/*******************************************************************************
* Graphics object classes
......@@ -38,11 +39,11 @@ nv108_graph_sclass[] = {
};
/*******************************************************************************
* PGRAPH engine/subdev functions
* PGRAPH register lists
******************************************************************************/
static struct nvc0_graph_init
nv108_graph_init_regs[] = {
static const struct nvc0_graph_init
nv108_graph_init_main_0[] = {
{ 0x400080, 1, 0x04, 0x003083c2 },
{ 0x400088, 1, 0x04, 0x0001bfe7 },
{ 0x40008c, 1, 0x04, 0x00000000 },
......@@ -57,19 +58,18 @@ nv108_graph_init_regs[] = {
{}
};
struct nvc0_graph_init
nv108_graph_init_unk58xx[] = {
static const struct nvc0_graph_init
nv108_graph_init_ds_0[] = {
{ 0x405844, 1, 0x04, 0x00ffffff },
{ 0x405850, 1, 0x04, 0x00000000 },
{ 0x405900, 1, 0x04, 0x00000000 },
{ 0x405908, 1, 0x04, 0x00000000 },
{ 0x405928, 1, 0x04, 0x00000000 },
{ 0x40592c, 1, 0x04, 0x00000000 },
{ 0x405928, 2, 0x04, 0x00000000 },
{}
};
static struct nvc0_graph_init
nv108_graph_init_gpc[] = {
static const struct nvc0_graph_init
nv108_graph_init_gpc_0[] = {
{ 0x418408, 1, 0x04, 0x00000000 },
{ 0x4184a0, 3, 0x04, 0x00000000 },
{ 0x418604, 1, 0x04, 0x00000000 },
......@@ -103,8 +103,8 @@ nv108_graph_init_gpc[] = {
{}
};
static struct nvc0_graph_init
nv108_graph_init_tpc[] = {
static const struct nvc0_graph_init
nv108_graph_init_tpc_0[] = {
{ 0x419d0c, 1, 0x04, 0x00000000 },
{ 0x419d10, 1, 0x04, 0x00000014 },
{ 0x419ab0, 1, 0x04, 0x00000000 },
......@@ -143,6 +143,29 @@ nv108_graph_init_tpc[] = {
{}
};
static const struct nvc0_graph_pack
nv108_graph_pack_mmio[] = {
{ nv108_graph_init_main_0 },
{ nvf0_graph_init_fe_0 },
{ nvc0_graph_init_pri_0 },
{ nvc0_graph_init_rstr2d_0 },
{ nvd9_graph_init_pd_0 },
{ nv108_graph_init_ds_0 },
{ nvc0_graph_init_scc_0 },
{ nvf0_graph_init_sked_0 },
{ nvf0_graph_init_cwd_0 },
{ nv108_graph_init_gpc_0 },
{ nv108_graph_init_tpc_0 },
{ nvd7_graph_init_ppc_0 },
{ nve4_graph_init_be_0 },
{ nvc0_graph_init_fe_1 },
{}
};
/*******************************************************************************
* PGRAPH engine/subdev functions
******************************************************************************/
static int
nv108_graph_fini(struct nouveau_object *object, bool suspend)
{
......@@ -180,25 +203,6 @@ nv108_graph_fini(struct nouveau_object *object, bool suspend)
return nouveau_graph_fini(&priv->base, suspend);
}
static struct nvc0_graph_init *
nv108_graph_init_mmio[] = {
nv108_graph_init_regs,
nvf0_graph_init_unk40xx,
nvc0_graph_init_unk44xx,
nvc0_graph_init_unk78xx,
nvc0_graph_init_unk60xx,
nvd9_graph_init_unk64xx,
nv108_graph_init_unk58xx,
nvc0_graph_init_unk80xx,
nvf0_graph_init_unk70xx,
nvf0_graph_init_unk5bxx,
nv108_graph_init_gpc,
nv108_graph_init_tpc,
nve4_graph_init_unk,
nve4_graph_init_unk88xx,
NULL
};
#include "fuc/hubnv108.fuc5.h"
static struct nvc0_graph_ucode
......@@ -230,7 +234,7 @@ nv108_graph_oclass = &(struct nvc0_graph_oclass) {
},
.cclass = &nv108_grctx_oclass,
.sclass = nv108_graph_sclass,
.mmio = nv108_graph_init_mmio,
.mmio = nv108_graph_pack_mmio,
.fecs.ucode = &nv108_graph_fecs_ucode,
.gpccs.ucode = &nv108_graph_gpccs_ucode,
}.base;
drivers/gpu/drm/nouveau/core/engine/graph/nvc0.h
View file @ c33b1e8c
......@@ -102,8 +102,6 @@ struct nvc0_graph_chan {
} data[4];
};
int nvc0_grctx_generate(struct nvc0_graph_priv *);
int nvc0_graph_context_ctor(struct nouveau_object *, struct nouveau_object *,
struct nouveau_oclass *, void *, u32,
struct nouveau_object **);
......@@ -130,34 +128,14 @@ struct nvc0_graph_init {
u32 data;
};
struct nvc0_graph_mthd {
u16 oclass;
struct nvc0_graph_init *init;
};
struct nvc0_grctx {
struct nvc0_graph_priv *priv;
struct nvc0_graph_data *data;
struct nvc0_graph_mmio *mmio;
int buffer_nr;
u64 buffer[4];
u64 addr;
struct nvc0_graph_pack {
const struct nvc0_graph_init *init;
u32 type;
};
struct nvc0_grctx_oclass {
struct nouveau_oclass base;
/* main context generation function */
void (*main)(struct nvc0_graph_priv *, struct nvc0_grctx *);
/* context-specific modify-on-first-load list generation function */
void (*mods)(struct nvc0_graph_priv *, struct nvc0_grctx *);
void (*unkn)(struct nvc0_graph_priv *);
/* mmio context data */
struct nvc0_graph_init **hub;
struct nvc0_graph_init **gpc;
/* indirect context data, generated with icmds/mthds */
struct nvc0_graph_init *icmd;
struct nvc0_graph_mthd *mthd;
};
#define pack_for_each_init(init, pack, head) \
for (pack = head; pack && pack->init; pack++) \
for (init = pack->init; init && init->count; init++)
struct nvc0_graph_ucode {
struct nvc0_graph_fuc code;
......@@ -171,7 +149,7 @@ struct nvc0_graph_oclass {
struct nouveau_oclass base;
struct nouveau_oclass **cclass;
struct nouveau_oclass *sclass;
struct nvc0_graph_init **mmio;
const struct nvc0_graph_pack *mmio;
struct {
struct nvc0_graph_ucode *ucode;
} fecs;
......@@ -180,119 +158,40 @@ struct nvc0_graph_oclass {
} gpccs;
};
void nvc0_graph_mmio(struct nvc0_graph_priv *, struct nvc0_graph_init *);
void nvc0_graph_icmd(struct nvc0_graph_priv *, struct nvc0_graph_init *);
void nvc0_graph_mthd(struct nvc0_graph_priv *, struct nvc0_graph_mthd *);
void nvc0_graph_mmio(struct nvc0_graph_priv *, const struct nvc0_graph_pack *);
void nvc0_graph_icmd(struct nvc0_graph_priv *, const struct nvc0_graph_pack *);
void nvc0_graph_mthd(struct nvc0_graph_priv *, const struct nvc0_graph_pack *);
int nvc0_graph_init_ctxctl(struct nvc0_graph_priv *);
extern struct nvc0_graph_init nvc0_graph_init_regs[];
extern struct nvc0_graph_init nvc0_graph_init_unk40xx[];
extern struct nvc0_graph_init nvc0_graph_init_unk44xx[];
extern struct nvc0_graph_init nvc0_graph_init_unk78xx[];
extern struct nvc0_graph_init nvc0_graph_init_unk60xx[];
extern struct nvc0_graph_init nvc0_graph_init_unk58xx[];
extern struct nvc0_graph_init nvc0_graph_init_unk80xx[];
extern struct nvc0_graph_init nvc0_graph_init_gpc[];
extern struct nvc0_graph_init nvc0_graph_init_unk88xx[];
extern struct nvc0_graph_init nvc0_graph_tpc_0[];
extern struct nvc0_graph_init nvc4_graph_init_unk58xx[];
extern struct nvc0_graph_init nvd9_graph_init_unk58xx[];
extern struct nvc0_graph_init nvd9_graph_init_unk64xx[];
extern struct nvc0_graph_init nve4_graph_init_regs[];
extern struct nvc0_graph_init nve4_graph_init_unk[];
extern struct nvc0_graph_init nve4_graph_init_unk88xx[];
extern struct nvc0_graph_init nvf0_graph_init_unk40xx[];
extern struct nvc0_graph_init nvf0_graph_init_unk70xx[];
extern struct nvc0_graph_init nvf0_graph_init_unk5bxx[];
extern struct nvc0_graph_init nvf0_graph_init_tpc[];
int nvc0_grctx_generate(struct nvc0_graph_priv *);
void nvc0_grctx_generate_main(struct nvc0_graph_priv *, struct nvc0_grctx *);
void nvc0_grctx_generate_mods(struct nvc0_graph_priv *, struct nvc0_grctx *);
void nvc0_grctx_generate_unkn(struct nvc0_graph_priv *);
void nvc0_grctx_generate_tpcid(struct nvc0_graph_priv *);
void nvc0_grctx_generate_r406028(struct nvc0_graph_priv *);
void nvc0_grctx_generate_r4060a8(struct nvc0_graph_priv *);
void nvc0_grctx_generate_r418bb8(struct nvc0_graph_priv *);
void nve4_grctx_generate_r418bb8(struct nvc0_graph_priv *);
void nvc0_grctx_generate_r406800(struct nvc0_graph_priv *);
extern struct nouveau_oclass *nvc0_grctx_oclass;
extern struct nvc0_graph_init *nvc0_grctx_init_hub[];
extern struct nvc0_graph_init nvc0_grctx_init_base[];
extern struct nvc0_graph_init nvc0_grctx_init_unk40xx[];
extern struct nvc0_graph_init nvc0_grctx_init_unk44xx[];
extern struct nvc0_graph_init nvc0_grctx_init_unk46xx[];
extern struct nvc0_graph_init nvc0_grctx_init_unk47xx[];
extern struct nvc0_graph_init nvc0_grctx_init_unk60xx[];
extern struct nvc0_graph_init nvc0_grctx_init_unk64xx[];
extern struct nvc0_graph_init nvc0_grctx_init_unk78xx[];
extern struct nvc0_graph_init nvc0_grctx_init_unk80xx[];
extern struct nvc0_graph_init nvc0_grctx_init_gpc_0[];
extern struct nvc0_graph_init nvc0_grctx_init_gpc_1[];
extern struct nvc0_graph_init nvc0_grctx_init_tpc[];
extern struct nvc0_graph_init nvc0_grctx_init_icmd[];
extern struct nvc0_graph_init nvd9_grctx_init_icmd[]; //
extern struct nvc0_graph_mthd nvc0_grctx_init_mthd[];
extern struct nvc0_graph_init nvc0_grctx_init_902d[];
extern struct nvc0_graph_init nvc0_grctx_init_9039[];
extern struct nvc0_graph_init nvc0_grctx_init_90c0[];
extern struct nvc0_graph_init nvc0_grctx_init_mthd_magic[];
void nvc1_grctx_generate_mods(struct nvc0_graph_priv *, struct nvc0_grctx *);
void nvc1_grctx_generate_unkn(struct nvc0_graph_priv *);
extern struct nouveau_oclass *nvc1_grctx_oclass;
extern struct nvc0_graph_init nvc1_grctx_init_9097[];
extern struct nouveau_oclass *nvc4_grctx_oclass;
extern struct nouveau_oclass *nvc8_grctx_oclass;
extern struct nvc0_graph_init nvc8_grctx_init_9197[];
extern struct nvc0_graph_init nvc8_grctx_init_9297[];
extern struct nouveau_oclass *nvd7_grctx_oclass;
extern struct nouveau_oclass *nvd9_grctx_oclass;
extern struct nvc0_graph_init nvd9_grctx_init_rop[];
extern struct nvc0_graph_mthd nvd9_grctx_init_mthd[];
void nve4_grctx_generate_main(struct nvc0_graph_priv *, struct nvc0_grctx *);
void nve4_grctx_generate_unkn(struct nvc0_graph_priv *);
extern struct nouveau_oclass *nve4_grctx_oclass;
extern struct nvc0_graph_init nve4_grctx_init_unk46xx[];
extern struct nvc0_graph_init nve4_grctx_init_unk47xx[];
extern struct nvc0_graph_init nve4_grctx_init_unk58xx[];
extern struct nvc0_graph_init nve4_grctx_init_unk80xx[];
extern struct nvc0_graph_init nve4_grctx_init_unk90xx[];
extern struct nouveau_oclass *nvf0_grctx_oclass;
extern struct nvc0_graph_init nvf0_grctx_init_unk44xx[];
extern struct nvc0_graph_init nvf0_grctx_init_unk5bxx[];
extern struct nvc0_graph_init nvf0_grctx_init_unk60xx[];
extern struct nouveau_oclass *nv108_grctx_oclass;
#define mmio_data(s,a,p) do { \
info->buffer[info->buffer_nr] = round_up(info->addr, (a)); \
info->addr = info->buffer[info->buffer_nr++] + (s); \
info->data->size = (s); \
info->data->align = (a); \
info->data->access = (p); \
info->data++; \
} while(0)
#define mmio_list(r,d,s,b) do { \
info->mmio->addr = (r); \
info->mmio->data = (d); \
info->mmio->shift = (s); \
info->mmio->buffer = (b); \
info->mmio++; \
nv_wr32(priv, (r), (d) | ((s) ? (info->buffer[(b)] >> (s)) : 0)); \
} while(0)
/* register init value lists */
extern const struct nvc0_graph_init nvc0_graph_init_main_0[];
extern const struct nvc0_graph_init nvc0_graph_init_fe_0[];
extern const struct nvc0_graph_init nvc0_graph_init_pri_0[];
extern const struct nvc0_graph_init nvc0_graph_init_rstr2d_0[];
extern const struct nvc0_graph_init nvc0_graph_init_pd_0[];
extern const struct nvc0_graph_init nvc0_graph_init_ds_0[];
extern const struct nvc0_graph_init nvc0_graph_init_scc_0[];
extern const struct nvc0_graph_init nvc0_graph_init_gpc_0[];
extern const struct nvc0_graph_init nvc0_graph_init_be_0[];
extern const struct nvc0_graph_init nvc0_graph_init_fe_1[];
extern const struct nvc0_graph_init nvc0_graph_init_tpc_1[];
extern const struct nvc0_graph_init nvc4_graph_init_ds_0[];
extern const struct nvc0_graph_init nvd9_graph_init_pd_0[];
extern const struct nvc0_graph_init nvd9_graph_init_ds_0[];
extern const struct nvc0_graph_init nvd9_graph_init_gpc_0[];
extern const struct nvc0_graph_init nvd9_graph_init_fe_1[];
extern const struct nvc0_graph_init nvd7_graph_init_ppc_0[];
extern const struct nvc0_graph_init nve4_graph_init_main_0[];
extern const struct nvc0_graph_init nve4_graph_init_be_0[];
extern const struct nvc0_graph_init nvf0_graph_init_fe_0[];
extern const struct nvc0_graph_init nvf0_graph_init_sked_0[];
extern const struct nvc0_graph_init nvf0_graph_init_cwd_0[];
#endif
drivers/gpu/drm/nouveau/core/engine/graph/nvc1.c
View file @ c33b1e8c
......@@ -23,6 +23,7 @@
*/
#include "nvc0.h"
#include "ctxnvc0.h"
/*******************************************************************************
* Graphics object classes
......@@ -39,11 +40,11 @@ nvc1_graph_sclass[] = {
};
/*******************************************************************************
* PGRAPH engine/subdev functions
* PGRAPH register lists
******************************************************************************/
static struct nvc0_graph_init
nvc1_graph_init_gpc[] = {
static const struct nvc0_graph_init
nvc1_graph_init_gpc_0[] = {
{ 0x4184a0, 1, 0x04, 0x00000000 },
{ 0x418604, 1, 0x04, 0x00000000 },
{ 0x418680, 1, 0x04, 0x00000000 },
......@@ -70,8 +71,8 @@ nvc1_graph_init_gpc[] = {
{}
};
static struct nvc0_graph_init
nvc1_graph_init_tpc[] = {
static const struct nvc0_graph_init
nvc1_graph_init_tpc_0[] = {
{ 0x419d08, 2, 0x04, 0x00000000 },
{ 0x419d10, 1, 0x04, 0x00000014 },
{ 0x419ab0, 1, 0x04, 0x00000000 },
......@@ -112,22 +113,26 @@ nvc1_graph_init_tpc[] = {
{}
};
struct nvc0_graph_init *
nvc1_graph_init_mmio[] = {
nvc0_graph_init_regs,
nvc0_graph_init_unk40xx,
nvc0_graph_init_unk44xx,
nvc0_graph_init_unk78xx,
nvc0_graph_init_unk60xx,
nvc4_graph_init_unk58xx,
nvc0_graph_init_unk80xx,
nvc1_graph_init_gpc,
nvc1_graph_init_tpc,
nvc0_graph_init_unk88xx,
nvc0_graph_tpc_0,
NULL
static const struct nvc0_graph_pack
nvc1_graph_pack_mmio[] = {
{ nvc0_graph_init_main_0 },
{ nvc0_graph_init_fe_0 },
{ nvc0_graph_init_pri_0 },
{ nvc0_graph_init_rstr2d_0 },
{ nvc0_graph_init_pd_0 },
{ nvc4_graph_init_ds_0 },
{ nvc0_graph_init_scc_0 },
{ nvc1_graph_init_gpc_0 },
{ nvc1_graph_init_tpc_0 },
{ nvc0_graph_init_be_0 },
{ nvc0_graph_init_fe_1 },
{}
};
/*******************************************************************************
* PGRAPH engine/subdev functions
******************************************************************************/
struct nouveau_oclass *
nvc1_graph_oclass = &(struct nvc0_graph_oclass) {
.base.handle = NV_ENGINE(GR, 0xc1),
......@@ -139,7 +144,7 @@ nvc1_graph_oclass = &(struct nvc0_graph_oclass) {
},
.cclass = &nvc1_grctx_oclass,
.sclass = nvc1_graph_sclass,
.mmio = nvc1_graph_init_mmio,
.mmio = nvc1_graph_pack_mmio,
.fecs.ucode = &nvc0_graph_fecs_ucode,
.gpccs.ucode = &nvc0_graph_gpccs_ucode,
}.base;
drivers/gpu/drm/nouveau/core/engine/graph/nvc4.c
View file @ c33b1e8c
......@@ -23,13 +23,14 @@
*/
#include "nvc0.h"
#include "ctxnvc0.h"
/*******************************************************************************
* PGRAPH engine/subdev functions
* PGRAPH register lists
******************************************************************************/
struct nvc0_graph_init
nvc4_graph_init_unk58xx[] = {
const struct nvc0_graph_init
nvc4_graph_init_ds_0[] = {
{ 0x405844, 1, 0x04, 0x00ffffff },
{ 0x405850, 1, 0x04, 0x00000000 },
{ 0x405900, 1, 0x04, 0x00002834 },
......@@ -37,8 +38,8 @@ nvc4_graph_init_unk58xx[] = {
{}
};
static struct nvc0_graph_init
nvc4_graph_init_tpc[] = {
static const struct nvc0_graph_init
nvc4_graph_init_tpc_0[] = {
{ 0x419d08, 2, 0x04, 0x00000000 },
{ 0x419d10, 1, 0x04, 0x00000014 },
{ 0x419ab0, 1, 0x04, 0x00000000 },
......@@ -77,22 +78,26 @@ nvc4_graph_init_tpc[] = {
{}
};
static struct nvc0_graph_init *
nvc4_graph_init_mmio[] = {
nvc0_graph_init_regs,
nvc0_graph_init_unk40xx,
nvc0_graph_init_unk44xx,
nvc0_graph_init_unk78xx,
nvc0_graph_init_unk60xx,
nvc4_graph_init_unk58xx,
nvc0_graph_init_unk80xx,
nvc0_graph_init_gpc,
nvc4_graph_init_tpc,
nvc0_graph_init_unk88xx,
nvc0_graph_tpc_0,
NULL
static const struct nvc0_graph_pack
nvc4_graph_pack_mmio[] = {
{ nvc0_graph_init_main_0 },
{ nvc0_graph_init_fe_0 },
{ nvc0_graph_init_pri_0 },
{ nvc0_graph_init_rstr2d_0 },
{ nvc0_graph_init_pd_0 },
{ nvc4_graph_init_ds_0 },
{ nvc0_graph_init_scc_0 },
{ nvc0_graph_init_gpc_0 },
{ nvc4_graph_init_tpc_0 },
{ nvc0_graph_init_be_0 },
{ nvc0_graph_init_fe_1 },
{}
};
/*******************************************************************************
* PGRAPH engine/subdev functions
******************************************************************************/
struct nouveau_oclass *
nvc4_graph_oclass = &(struct nvc0_graph_oclass) {
.base.handle = NV_ENGINE(GR, 0xc3),
......@@ -104,7 +109,7 @@ nvc4_graph_oclass = &(struct nvc0_graph_oclass) {
},
.cclass = &nvc4_grctx_oclass,
.sclass = nvc0_graph_sclass,
.mmio = nvc4_graph_init_mmio,
.mmio = nvc4_graph_pack_mmio,
.fecs.ucode = &nvc0_graph_fecs_ucode,
.gpccs.ucode = &nvc0_graph_gpccs_ucode,
}.base;
drivers/gpu/drm/nouveau/core/engine/graph/nvc8.c
View file @ c33b1e8c
......@@ -23,6 +23,7 @@
*/
#include "nvc0.h"
#include "ctxnvc0.h"
/*******************************************************************************
* Graphics object classes
......@@ -40,11 +41,11 @@ nvc8_graph_sclass[] = {
};
/*******************************************************************************
* PGRAPH engine/subdev functions
* PGRAPH register lists
******************************************************************************/
static struct nvc0_graph_init
nvc8_graph_init_gpc[] = {
static const struct nvc0_graph_init
nvc8_graph_init_gpc_0[] = {
{ 0x4184a0, 1, 0x04, 0x00000000 },
{ 0x418604, 1, 0x04, 0x00000000 },
{ 0x418680, 1, 0x04, 0x00000000 },
......@@ -71,8 +72,8 @@ nvc8_graph_init_gpc[] = {
{}
};
static struct nvc0_graph_init
nvc8_graph_init_tpc[] = {
static const struct nvc0_graph_init
nvc8_graph_init_tpc_0[] = {
{ 0x419d08, 2, 0x04, 0x00000000 },
{ 0x419d10, 1, 0x04, 0x00000014 },
{ 0x419ab0, 1, 0x04, 0x00000000 },
......@@ -108,22 +109,27 @@ nvc8_graph_init_tpc[] = {
{}
};
static struct nvc0_graph_init *
nvc8_graph_init_mmio[] = {
nvc0_graph_init_regs,
nvc0_graph_init_unk40xx,
nvc0_graph_init_unk44xx,
nvc0_graph_init_unk78xx,
nvc0_graph_init_unk60xx,
nvc0_graph_init_unk58xx,
nvc0_graph_init_unk80xx,
nvc8_graph_init_gpc,
nvc8_graph_init_tpc,
nvc0_graph_init_unk88xx,
nvc0_graph_tpc_0,
NULL
static const struct nvc0_graph_pack
nvc8_graph_pack_mmio[] = {
{ nvc0_graph_init_main_0 },
{ nvc0_graph_init_fe_0 },
{ nvc0_graph_init_pri_0 },
{ nvc0_graph_init_rstr2d_0 },
{ nvc0_graph_init_pd_0 },
{ nvc0_graph_init_ds_0 },
{ nvc0_graph_init_scc_0 },
{ nvc8_graph_init_gpc_0 },
{ nvc8_graph_init_tpc_0 },
{ nvc0_graph_init_be_0 },
{ nvc0_graph_init_fe_1 },
{ nvc0_graph_init_tpc_1 },
{}
};
/*******************************************************************************
* PGRAPH engine/subdev functions
******************************************************************************/
struct nouveau_oclass *
nvc8_graph_oclass = &(struct nvc0_graph_oclass) {
.base.handle = NV_ENGINE(GR, 0xc8),
......@@ -135,7 +141,7 @@ nvc8_graph_oclass = &(struct nvc0_graph_oclass) {
},
.cclass = &nvc8_grctx_oclass,
.sclass = nvc8_graph_sclass,
.mmio = nvc8_graph_init_mmio,
.mmio = nvc8_graph_pack_mmio,
.fecs.ucode = &nvc0_graph_fecs_ucode,
.gpccs.ucode = &nvc0_graph_gpccs_ucode,
}.base;
drivers/gpu/drm/nouveau/core/engine/graph/nvd7.c
View file @ c33b1e8c
......@@ -23,71 +23,14 @@
*/
#include "nvc0.h"
#include "ctxnvc0.h"
/*******************************************************************************
* PGRAPH engine/subdev functions
* PGRAPH register lists
******************************************************************************/
#include "fuc/hubnvd7.fuc.h"
struct nvc0_graph_ucode
nvd7_graph_fecs_ucode = {
.code.data = nvd7_grhub_code,
.code.size = sizeof(nvd7_grhub_code),
.data.data = nvd7_grhub_data,
.data.size = sizeof(nvd7_grhub_data),
};
#include "fuc/gpcnvd7.fuc.h"
struct nvc0_graph_ucode
nvd7_graph_gpccs_ucode = {
.code.data = nvd7_grgpc_code,
.code.size = sizeof(nvd7_grgpc_code),
.data.data = nvd7_grgpc_data,
.data.size = sizeof(nvd7_grgpc_data),
};
static struct nvc0_graph_init
nvd7_graph_init_gpc[] = {
{ 0x418408, 1, 0x04, 0x00000000 },
{ 0x4184a0, 1, 0x04, 0x00000000 },
{ 0x4184a4, 2, 0x04, 0x00000000 },
{ 0x418604, 1, 0x04, 0x00000000 },
{ 0x418680, 1, 0x04, 0x00000000 },
{ 0x418714, 1, 0x04, 0x00000000 },
{ 0x418384, 1, 0x04, 0x00000000 },
{ 0x418814, 3, 0x04, 0x00000000 },
{ 0x418b04, 1, 0x04, 0x00000000 },
{ 0x4188c8, 2, 0x04, 0x00000000 },
{ 0x4188d0, 1, 0x04, 0x00010000 },
{ 0x4188d4, 1, 0x04, 0x00000001 },
{ 0x418910, 1, 0x04, 0x00010001 },
{ 0x418914, 1, 0x04, 0x00000301 },
{ 0x418918, 1, 0x04, 0x00800000 },
{ 0x418980, 1, 0x04, 0x77777770 },
{ 0x418984, 3, 0x04, 0x77777777 },
{ 0x418c04, 1, 0x04, 0x00000000 },
{ 0x418c64, 1, 0x04, 0x00000000 },
{ 0x418c68, 1, 0x04, 0x00000000 },
{ 0x418c88, 1, 0x04, 0x00000000 },
{ 0x418cb4, 2, 0x04, 0x00000000 },
{ 0x418d00, 1, 0x04, 0x00000000 },
{ 0x418d28, 1, 0x04, 0x00000000 },
{ 0x418f00, 1, 0x04, 0x00000000 },
{ 0x418f08, 1, 0x04, 0x00000000 },
{ 0x418f20, 2, 0x04, 0x00000000 },
{ 0x418e00, 1, 0x04, 0x00000003 },
{ 0x418e08, 1, 0x04, 0x00000000 },
{ 0x418e1c, 1, 0x04, 0x00000000 },
{ 0x418e20, 1, 0x04, 0x00000000 },
{ 0x41900c, 1, 0x04, 0x00000000 },
{ 0x419018, 1, 0x04, 0x00000000 },
{}
};
static struct nvc0_graph_init
nvd7_graph_init_tpc[] = {
static const struct nvc0_graph_init
nvd7_graph_init_tpc_0[] = {
{ 0x419d08, 2, 0x04, 0x00000000 },
{ 0x419d10, 1, 0x04, 0x00000014 },
{ 0x419ab0, 1, 0x04, 0x00000000 },
......@@ -98,7 +41,7 @@ nvd7_graph_init_tpc[] = {
{ 0x41980c, 1, 0x04, 0x00000010 },
{ 0x419844, 1, 0x04, 0x00000000 },
{ 0x41984c, 1, 0x04, 0x00005bc8 },
{ 0x419850, 2, 0x04, 0x00000000 },
{ 0x419850, 3, 0x04, 0x00000000 },
{ 0x419c98, 1, 0x04, 0x00000000 },
{ 0x419ca8, 1, 0x04, 0x80000000 },
{ 0x419cb4, 1, 0x04, 0x00000000 },
......@@ -123,31 +66,60 @@ nvd7_graph_init_tpc[] = {
{}
};
static struct nvc0_graph_init
nvd7_graph_init_tpc_0[] = {
{ 0x40402c, 1, 0x04, 0x00000000 },
{ 0x4040f0, 1, 0x04, 0x00000000 },
{ 0x404174, 1, 0x04, 0x00000000 },
{ 0x503018, 1, 0x04, 0x00000001 },
const struct nvc0_graph_init
nvd7_graph_init_ppc_0[] = {
{ 0x41be04, 1, 0x04, 0x00000000 },
{ 0x41be08, 1, 0x04, 0x00000004 },
{ 0x41be0c, 1, 0x04, 0x00000000 },
{ 0x41be10, 1, 0x04, 0x003b8bc7 },
{ 0x41be14, 2, 0x04, 0x00000000 },
{ 0x41bfd4, 1, 0x04, 0x00800000 },
{ 0x41bfdc, 1, 0x04, 0x00000000 },
{ 0x41bff8, 2, 0x04, 0x00000000 },
{ 0x41becc, 1, 0x04, 0x00000000 },
{ 0x41bee8, 2, 0x04, 0x00000000 },
{}
};
static struct nvc0_graph_init *
nvd7_graph_init_mmio[] = {
nvc0_graph_init_regs,
nvc0_graph_init_unk40xx,
nvc0_graph_init_unk44xx,
nvc0_graph_init_unk78xx,
nvc0_graph_init_unk60xx,
nvd9_graph_init_unk64xx,
nvd9_graph_init_unk58xx,
nvc0_graph_init_unk80xx,
nvd7_graph_init_gpc,
nvd7_graph_init_tpc,
nve4_graph_init_unk,
nvc0_graph_init_unk88xx,
nvd7_graph_init_tpc_0,
NULL
static const struct nvc0_graph_pack
nvd7_graph_pack_mmio[] = {
{ nvc0_graph_init_main_0 },
{ nvc0_graph_init_fe_0 },
{ nvc0_graph_init_pri_0 },
{ nvc0_graph_init_rstr2d_0 },
{ nvd9_graph_init_pd_0 },
{ nvd9_graph_init_ds_0 },
{ nvc0_graph_init_scc_0 },
{ nvd9_graph_init_gpc_0 },
{ nvd7_graph_init_tpc_0 },
{ nvd7_graph_init_ppc_0 },
{ nvc0_graph_init_be_0 },
{ nvd9_graph_init_fe_1 },
{}
};
/*******************************************************************************
* PGRAPH engine/subdev functions
******************************************************************************/
#include "fuc/hubnvd7.fuc.h"
struct nvc0_graph_ucode
nvd7_graph_fecs_ucode = {
.code.data = nvd7_grhub_code,
.code.size = sizeof(nvd7_grhub_code),
.data.data = nvd7_grhub_data,
.data.size = sizeof(nvd7_grhub_data),
};
#include "fuc/gpcnvd7.fuc.h"
struct nvc0_graph_ucode
nvd7_graph_gpccs_ucode = {
.code.data = nvd7_grgpc_code,
.code.size = sizeof(nvd7_grgpc_code),
.data.data = nvd7_grgpc_data,
.data.size = sizeof(nvd7_grgpc_data),
};
struct nouveau_oclass *
......@@ -161,7 +133,7 @@ nvd7_graph_oclass = &(struct nvc0_graph_oclass) {
},
.cclass = &nvd7_grctx_oclass,
.sclass = nvc8_graph_sclass,
.mmio = nvd7_graph_init_mmio,
.mmio = nvd7_graph_pack_mmio,
.fecs.ucode = &nvd7_graph_fecs_ucode,
.gpccs.ucode = &nvd7_graph_gpccs_ucode,
}.base;
drivers/gpu/drm/nouveau/core/engine/graph/nvd9.c
View file @ c33b1e8c
......@@ -23,33 +23,33 @@
*/
#include "nvc0.h"
#include "ctxnvc0.h"
/*******************************************************************************
* PGRAPH engine/subdev functions
* PGRAPH register lists
******************************************************************************/
struct nvc0_graph_init
nvd9_graph_init_unk64xx[] = {
const struct nvc0_graph_init
nvd9_graph_init_pd_0[] = {
{ 0x406024, 1, 0x04, 0x00000000 },
{ 0x4064f0, 3, 0x04, 0x00000000 },
{}
};
struct nvc0_graph_init
nvd9_graph_init_unk58xx[] = {
const struct nvc0_graph_init
nvd9_graph_init_ds_0[] = {
{ 0x405844, 1, 0x04, 0x00ffffff },
{ 0x405850, 1, 0x04, 0x00000000 },
{ 0x405900, 1, 0x04, 0x00002834 },
{ 0x405908, 1, 0x04, 0x00000000 },
{ 0x405928, 1, 0x04, 0x00000000 },
{ 0x40592c, 1, 0x04, 0x00000000 },
{ 0x405928, 2, 0x04, 0x00000000 },
{}
};
static struct nvc0_graph_init
nvd9_graph_init_gpc[] = {
const struct nvc0_graph_init
nvd9_graph_init_gpc_0[] = {
{ 0x418408, 1, 0x04, 0x00000000 },
{ 0x4184a0, 1, 0x04, 0x00000000 },
{ 0x4184a4, 2, 0x04, 0x00000000 },
{ 0x4184a0, 3, 0x04, 0x00000000 },
{ 0x418604, 1, 0x04, 0x00000000 },
{ 0x418680, 1, 0x04, 0x00000000 },
{ 0x418714, 1, 0x04, 0x00000000 },
......@@ -65,27 +65,24 @@ nvd9_graph_init_gpc[] = {
{ 0x418980, 1, 0x04, 0x77777770 },
{ 0x418984, 3, 0x04, 0x77777777 },
{ 0x418c04, 1, 0x04, 0x00000000 },
{ 0x418c64, 1, 0x04, 0x00000000 },
{ 0x418c68, 1, 0x04, 0x00000000 },
{ 0x418c64, 2, 0x04, 0x00000000 },
{ 0x418c88, 1, 0x04, 0x00000000 },
{ 0x418cb4, 2, 0x04, 0x00000000 },
{ 0x418d00, 1, 0x04, 0x00000000 },
{ 0x418d28, 1, 0x04, 0x00000000 },
{ 0x418d2c, 1, 0x04, 0x00000000 },
{ 0x418d28, 2, 0x04, 0x00000000 },
{ 0x418f00, 1, 0x04, 0x00000000 },
{ 0x418f08, 1, 0x04, 0x00000000 },
{ 0x418f20, 2, 0x04, 0x00000000 },
{ 0x418e00, 1, 0x04, 0x00000003 },
{ 0x418e08, 1, 0x04, 0x00000000 },
{ 0x418e1c, 1, 0x04, 0x00000000 },
{ 0x418e20, 1, 0x04, 0x00000000 },
{ 0x418e1c, 2, 0x04, 0x00000000 },
{ 0x41900c, 1, 0x04, 0x00000000 },
{ 0x419018, 1, 0x04, 0x00000000 },
{}
};
static struct nvc0_graph_init
nvd9_graph_init_tpc[] = {
static const struct nvc0_graph_init
nvd9_graph_init_tpc_0[] = {
{ 0x419d08, 2, 0x04, 0x00000000 },
{ 0x419d10, 1, 0x04, 0x00000014 },
{ 0x419ab0, 1, 0x04, 0x00000000 },
......@@ -108,11 +105,9 @@ nvd9_graph_init_tpc[] = {
{ 0x419cc0, 2, 0x04, 0x00000000 },
{ 0x419bd4, 1, 0x04, 0x00800000 },
{ 0x419bdc, 1, 0x04, 0x00000000 },
{ 0x419bf8, 1, 0x04, 0x00000000 },
{ 0x419bfc, 1, 0x04, 0x00000000 },
{ 0x419bf8, 2, 0x04, 0x00000000 },
{ 0x419d2c, 1, 0x04, 0x00000000 },
{ 0x419d48, 1, 0x04, 0x00000000 },
{ 0x419d4c, 1, 0x04, 0x00000000 },
{ 0x419d48, 2, 0x04, 0x00000000 },
{ 0x419c0c, 1, 0x04, 0x00000000 },
{ 0x419e00, 1, 0x04, 0x00000000 },
{ 0x419ea0, 1, 0x04, 0x00000000 },
......@@ -131,23 +126,34 @@ nvd9_graph_init_tpc[] = {
{}
};
static struct nvc0_graph_init *
nvd9_graph_init_mmio[] = {
nvc0_graph_init_regs,
nvc0_graph_init_unk40xx,
nvc0_graph_init_unk44xx,
nvc0_graph_init_unk78xx,
nvc0_graph_init_unk60xx,
nvd9_graph_init_unk64xx,
nvd9_graph_init_unk58xx,
nvc0_graph_init_unk80xx,
nvd9_graph_init_gpc,
nvd9_graph_init_tpc,
nvc0_graph_init_unk88xx,
nvc0_graph_tpc_0,
NULL
const struct nvc0_graph_init
nvd9_graph_init_fe_1[] = {
{ 0x40402c, 1, 0x04, 0x00000000 },
{ 0x4040f0, 1, 0x04, 0x00000000 },
{ 0x404174, 1, 0x04, 0x00000000 },
{}
};
static const struct nvc0_graph_pack
nvd9_graph_pack_mmio[] = {
{ nvc0_graph_init_main_0 },
{ nvc0_graph_init_fe_0 },
{ nvc0_graph_init_pri_0 },
{ nvc0_graph_init_rstr2d_0 },
{ nvd9_graph_init_pd_0 },
{ nvd9_graph_init_ds_0 },
{ nvc0_graph_init_scc_0 },
{ nvd9_graph_init_gpc_0 },
{ nvd9_graph_init_tpc_0 },
{ nvc0_graph_init_be_0 },
{ nvd9_graph_init_fe_1 },
{}
};
/*******************************************************************************
* PGRAPH engine/subdev functions
******************************************************************************/
struct nouveau_oclass *
nvd9_graph_oclass = &(struct nvc0_graph_oclass) {
.base.handle = NV_ENGINE(GR, 0xd9),
......@@ -159,7 +165,7 @@ nvd9_graph_oclass = &(struct nvc0_graph_oclass) {
},
.cclass = &nvd9_grctx_oclass,
.sclass = nvc8_graph_sclass,
.mmio = nvd9_graph_init_mmio,
.mmio = nvd9_graph_pack_mmio,
.fecs.ucode = &nvc0_graph_fecs_ucode,
.gpccs.ucode = &nvc0_graph_gpccs_ucode,
}.base;
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