Merge samba.org:/home/paulus/kernel/linux-2.5

into samba.org:/home/paulus/kernel/for-linus-ppc

arch/ppc/Config.help

@@ -340,9 +340,16 @@ CONFIG_PREP_RESIDUAL
   other useful pieces of information.  Sometimes this information is
   not present or incorrect.
 
-  Unless you expect to boot on a PReP system, there is not need to
+  Unless you expect to boot on a PReP system, there is no need to
   select Y.
 
+PReP residual data available in /proc/residual
+CONFIG_PROC_PREPRESIDUAL
+  Enabling this option will create a /proc/residual file which allows
+  you to get at the residual data on PReP systems.  You will need a tool
+  (lsresidual) to parse it.  If you aren't on a PReP system, you don't
+  want this.
+
 CONFIG_ADB
   Apple Desktop Bus (ADB) support is for support of devices which
   are connected to an ADB port.  ADB devices tend to have 4 pins.

arch/ppc/boot/chrp/start.c

 /*
- * BK Id: SCCS/s.start.c 1.8 07/25/01 18:13:07 trini
+ * BK Id: %F% %I% %G% %U% %#%
  */
 /*
  * Copyright (C) Paul Mackerras 1997.
@@ -11,7 +11,7 @@
  */
 #include <stdarg.h>
 
-int (*prom)();
+int (*prom)(void *args);
 
 void *chosen_handle;
 void *stdin;
@@ -30,7 +30,7 @@ extern int strlen(const char *s);
 void
 start(int a1, int a2, void *promptr)
 {
-    prom = (int (*)()) promptr;
+    prom = promptr;
     chosen_handle = finddevice("/chosen");
     if (chosen_handle == (void *) -1)
 	exit();
@@ -65,7 +65,7 @@ write(void *handle, void *ptr, int nb)
     args.addr = ptr;
     args.len = nb;
     args.actual = -1;
-    (*prom)(&args);
+    prom(&args);
     return args.actual;
 }
 
@@ -211,7 +211,7 @@ fputs(char *str, void *f)
 }
 
 int
-readchar()
+readchar(void)
 {
     char ch;
 

arch/ppc/boot/common/crt0.S

@@ -69,7 +69,7 @@ __start:
 	bdnz	1b			# If we are not done yet, keep clearing
 2:
 
-#ifdef CONFIG_4xx
+#ifdef CONFIG_40x
 	## Set up the stack
 
 	lis	r9,_start@h		# r9 = &_start (text section entry)

arch/ppc/boot/common/misc-simple.c

@@ -67,7 +67,7 @@ extern int CRT_tstc(void);
 extern unsigned long serial_init(int chan, void *ignored);
 extern void serial_close(unsigned long com_port);
 extern void gunzip(void *, int, unsigned char *, int *);
-extern void setup_legacy(void);
+extern void serial_fixups(void);
 
 struct bi_record *
 decompress_kernel(unsigned long load_addr, int num_words, unsigned long cksum)
@@ -76,7 +76,7 @@ decompress_kernel(unsigned long load_addr, int num_words, unsigned long cksum)
 	char *cp, ch;
 	struct bi_record *rec, *birecs;
 
-	setup_legacy();
+	serial_fixups();
 	com_port = serial_init(0, NULL);
 
 	/* assume the chunk below 8M is free */

arch/ppc/boot/common/relocate.S

@@ -9,7 +9,7 @@
  *	   trini@mvista.com
  * Derived from arch/ppc/boot/prep/head.S (Cort Dougan, many others).
  *
- * Copyright 2001 MontaVista Software Inc.
+ * Copyright 2001-2002 MontaVista Software Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -188,10 +188,11 @@ start_ldr:
 	bl	decompress_kernel
 
 	/*
-	 * Make sure the kernel knows we don't have things set  in
+	 * Make sure the kernel knows we don't have things set in
 	 * registers.  -- Tom
 	 */
 	li	r4,0
+	li	r5,0
 	li	r6,0
 
 	/*

arch/ppc/boot/prep/misc.c

@@ -75,7 +75,7 @@ extern void gunzip(void *, int, unsigned char *, int *);
 
 extern void _put_MSR(unsigned int val);
 extern unsigned long serial_init(int chan, void *ignored);
-extern void setup_legacy(void);
+extern void serial_fixups(void);
 
 void
 writel(unsigned int val, unsigned int address)
@@ -134,7 +134,7 @@ decompress_kernel(unsigned long load_addr, int num_words, unsigned long cksum,
 	int start_multi = 0;
 	unsigned int pci_viddid, pci_did, tulip_pci_base, tulip_base;
 
-	setup_legacy();
+	serial_fixups();
 #if defined(CONFIG_SERIAL_CONSOLE)
 	com_port = serial_init(0, NULL);
 #endif /* CONFIG_SERIAL_CONSOLE */

arch/ppc/boot/simple/chrpmap.S

@@ -3,15 +3,15 @@
  *
  * Author: Tom Rini <trini@mvista.com>
  *
- * This will go and setup ISA_io to 0xFE00000.
+ * This will go and setup ISA_io to 0xFE00000 and return.
  */
 
 #include <asm/ppc_asm.h>
 
 	.text
 
-	.globl setup_legacy
-setup_legacy:
+	.globl serial_fixups
+serial_fixups:
 	lis	r3,ISA_io@h	/* Load ISA_io */
 	ori	r3,r3,ISA_io@l
 	lis	r4,0xFE00	/* Load the value, 0xFE00000 */

arch/ppc/boot/simple/direct.S

@@ -4,11 +4,12 @@
  * Author: Tom Rini <trini@mvista.com>
  *
  * This is an empty function for machines which use SERIAL_IO_MEM
- * and don't need ISA_io set to anything but 0;
+ * and don't need ISA_io set to anything but 0, or perform any other
+ * serial fixups.
  */
 
 	.text
 
-	.globl setup_legacy
-setup_legacy:
+	.globl serial_fixups
+serial_fixups:
 	blr

arch/ppc/boot/simple/embed_config.c

@@ -4,9 +4,17 @@
 
 /* Board specific functions for those embedded 8xx boards that do
  * not have boot monitor support for board information.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
  */
+
 #include <linux/types.h>
 #include <linux/config.h>
+#include <linux/string.h>
+#include <asm/io.h>
 #ifdef CONFIG_8xx
 #include <asm/mpc8xx.h>
 #endif
@@ -14,12 +22,6 @@
 #include <asm/mpc8260.h>
 #include <asm/immap_8260.h>
 #endif
-#ifdef CONFIG_4xx
-#include <asm/io.h>
-#endif
-#if defined(CONFIG_405GP) || defined(CONFIG_NP405H) || defined(CONFIG_NP405L)
-#include <linux/netdevice.h>
-#endif
 
 /* For those boards that don't provide one.
 */
@@ -222,6 +224,23 @@ rpx_memsize(bd_t *bd, u_char *cp)
 	bd->bi_memsize = size * 1024 * 1024;
 }
 #endif /* LITE || CLASSIC || EP405 */
+#if defined(CONFIG_EP405)
+static void
+rpx_nvramsize(bd_t *bd, u_char *cp)
+{
+	uint	size;
+
+	size = 0;
+
+	while (*cp != '\n') {
+		size *= 10;
+		size += (*cp) - '0';
+		cp++;
+	}
+
+	bd->bi_nvramsize = size * 1024;
+}
+#endif /* CONFIG_EP405 */
 
 #endif	/* Embedded Planet boards */
 
@@ -641,7 +660,11 @@ embed_config(bd_t **bdp)
 #ifdef CONFIG_TREEBOOT
 /* This could possibly work for all treeboot roms.
 */
+#if defined(CONFIG_ASH)
+#define BOARD_INFO_VECTOR       0xFFF80B50 /* openbios 1.19 moved this vector down  - armin */
+#else
 #define	BOARD_INFO_VECTOR	0xFFFE0B50
+#endif
 
 void
 embed_config(bd_t **bdp)
@@ -658,8 +681,8 @@ embed_config(bd_t **bdp)
 	/* shut down the Ethernet controller that the boot rom
 	 * sometimes leaves running.
 	 */
-	mtdcr(DCRN_MALCR, MALCR_MMSR);                /* 1st reset MAL */
-	while (mfdcr(DCRN_MALCR) & MALCR_MMSR) {};    /* wait for the reset */
+	mtdcr(DCRN_MALCR(DCRN_MAL_BASE), MALCR_MMSR);     /* 1st reset MAL */
+	while (mfdcr(DCRN_MALCR(DCRN_MAL_BASE)) & MALCR_MMSR) {}; /* wait for the reset */	
 	emacp->em0mr0 = 0x20000000;        /* then reset EMAC */
 	eieio();
 #endif
@@ -684,24 +707,20 @@ embed_config(bd_t **bdp)
 			bd->bi_pci_enetaddr[i] = *cp++;
 #endif
 		}
+		bd->bi_tbfreq = 200 * 1000 * 1000;
 		bd->bi_intfreq = 200000000;
 		bd->bi_busfreq = 100000000;
 #ifdef CONFIG_PCI
 		bd->bi_pci_busfreq = 66666666;
 #endif
-		/* Yeah, this look weird, but on Redwood 4 they are
-		 * different object in the structure.  When RW5 uses
-		 * OpenBIOS, it requires a special value.
-		 */
+	}
+	/* Yeah, this look weird, but on Redwood 4 they are
+	 * different object in the structure.  When RW5 uses
+	 * OpenBIOS, it requires a special value.
+	 */
 #ifdef CONFIG_REDWOOD_5
-	bd->bi_intfreq = 200 * 1000 * 1000;
-	bd->bi_busfreq = 0;
-
-		bd->bi_tbfreq = 27 * 1000 * 1000;
-#elif CONFIG_REDWOOD_4
-		bd->bi_tbfreq = bd->bi_intfreq;
+	bd->bi_tbfreq = 27 * 1000 * 1000;
 #endif
-	}
 }
 #endif
 
@@ -751,6 +770,13 @@ embed_config(bd_t **bdp)
 	        	                }
                 	}
 
+			if (*cp == 'N') {
+				cp++;
+				if (*cp == 'V') {
+					cp += 2;
+					rpx_nvramsize(bd, cp);
+				}
+			}
 			while ((*cp != '\n') && (*cp != 0xff))
 			      cp++;
 
@@ -771,3 +797,28 @@ embed_config(bd_t **bdp)
 }
 #endif
 
+#ifdef CONFIG_RAINIER
+/* Rainier uses vxworks bootrom */
+void
+embed_config(bd_t **bdp)
+{
+	u_char	*cp;
+	int	i;
+	bd_t	*bd;
+	
+	bd = &bdinfo;
+	*bdp = bd;
+
+	bd->bi_memsize   = (32 * 1024 * 1024) ;
+	bd->bi_intfreq = 133000000; //the internal clock is 133 MHz
+	bd->bi_busfreq   = 100000000;
+	bd->bi_pci_busfreq= 33000000;
+
+	cp = (u_char *)def_enet_addr;
+	for (i=0; i<6; i++) {
+		bd->bi_enetaddr[i] = *cp++;
+	}
+
+}
+#endif
+

arch/ppc/boot/simple/legacy.S

@@ -3,15 +3,15 @@
  *
  * Author: Tom Rini <trini@mvista.com>
  *
- * This will go and setup ISA_io to 0x8000000.
+ * This will go and setup ISA_io to 0x8000000 and return.
  */
 
 #include <asm/ppc_asm.h>
 
 	.text
 
-	.globl setup_legacy
-setup_legacy:
+	.globl serial_fixups
+serial_fixups:
 	lis	r3,ISA_io@h	/* Load ISA_io */
 	ori	r3,r3,ISA_io@l
 	lis	r4,0x8000	/* Load the value, 0x8000000 */

arch/ppc/boot/simple/misc-embedded.c

@@ -54,7 +54,7 @@ char *bootrom_cmdline = "";
 char compiled_string[] = CONFIG_CMDLINE;
 #endif
 char ramroot_string[] = "root=/dev/ram";
-char netroot_string[] = "root=/dev/nfs rw ip=auto";
+char netroot_string[] = "root=/dev/nfs rw ip=on";
 
 /* Serial port to use. */
 unsigned long com_port;

arch/ppc/config.in

@@ -18,11 +18,15 @@ define_bool CONFIG_PPC y
 define_bool CONFIG_PPC32 y
 choice 'Processor Type'	\
 	"6xx/7xx/74xx/8260	CONFIG_6xx	\
-	 4xx			CONFIG_4xx	\
+	 40x			CONFIG_40x	\
 	 POWER3               	CONFIG_POWER3	\
 	 8xx			CONFIG_8xx	\
 	 iSeries		CONFIG_PPC_ISERIES"	6xx
 
+if [ "$CONFIG_40x" = "y" ]; then
+  define_bool CONFIG_4xx y
+fi
+
 if [ "$CONFIG_6xx" = "y" ]; then
    bool 'MPC8260 CPM Support' CONFIG_8260
 fi
@@ -52,17 +56,21 @@ if [ "$CONFIG_8260" = "y" ]; then
 	 Willow		CONFIG_WILLOW"	Willow
 fi
 
-if [ "$CONFIG_4xx" = "y" ]; then
+if [ "$CONFIG_40x" = "y" ]; then
     choice 'Machine Type'			\
 	"Ash		CONFIG_ASH		\
 	 Ceder		CONFIG_CEDER		\
 	 CPCI405	CONFIG_CPCI405 		\
-	 EP405		CONFIG_EP405 		\
+	 EP405/EP405PC	CONFIG_EP405 		\
 	 Oak		CONFIG_OAK 		\
 	 Redwood-4	CONFIG_REDWOOD_4 	\
 	 Redwood-5	CONFIG_REDWOOD_5 	\
 	 Tivo		CONFIG_TIVO 		\
 	 Walnut		CONFIG_WALNUT"	Walnut
+
+   if [ "$CONFIG_EP405" = "y" ]; then
+      bool 'EP405PC Support' CONFIG_EP405PC
+   fi  
 fi
 
 if [ "$CONFIG_8xx" = "y" ]; then
@@ -182,7 +190,7 @@ if [ "$CONFIG_4xx" = "y" -o "$CONFIG_8xx" = "y" ]; then
    bool 'Math emulation' CONFIG_MATH_EMULATION
 fi
 
-if [ "$CONFIG_4xx" = "y" ]; then
+if [ "$CONFIG_40x" = "y" ]; then
 # It's often necessary to know the specific 4xx processor type.
 # Fortunately, it is impled (so far) from the board type, so we
 # don't need to ask more redundant questions.
@@ -238,11 +246,9 @@ if [ "$CONFIG_4xx" = "y" ]; then
    bool 'Blue Logic DMA' CONFIG_405_DMA
    dep_bool 'Power Management support (experimental)' CONFIG_PM $CONFIG_EXPERIMENTAL
 
-   if [ "$CONFIG_4xx" = "y" ]; then
-      choice 'TTYS0 device and default console'	\
+   choice 'TTYS0 device and default console'	\
 	"UART0  CONFIG_UART0_TTYS0		\
 	 UART1	CONFIG_UART0_TTYS1"		UART0
-   fi
 
    define_bool CONFIG_IBM405_ERR51 y
    define_bool CONFIG_NOT_COHERENT_CACHE y
@@ -282,7 +288,7 @@ if [ "$CONFIG_ADVANCED_OPTIONS" = "y" ]; then
    if [ "$CONFIG_8xx" = "y" ]; then
       bool "Pinned Kernel TLBs (860 ONLY)" CONFIG_PIN_TLB
    fi
-   if [ "$CONFIG_4xx" = "y" ]; then
+   if [ "$CONFIG_40x" = "y" ]; then
       bool "Pinned Kernel TLBs" CONFIG_PIN_TLB
    fi
    if [ "$CONFIG_ALL_PPC" != "y" ]; then
@@ -362,6 +368,7 @@ if [ "$CONFIG_ALL_PPC" = "y" ]; then
    bool 'Support for Open Firmware device tree in /proc' CONFIG_PROC_DEVICETREE
    bool 'Support for RTAS (RunTime Abstraction Services) in /proc' CONFIG_PPC_RTAS
    bool 'Support for PReP Residual Data' CONFIG_PREP_RESIDUAL
+   dep_bool '  Support for reading of PReP Residual Data in /proc' CONFIG_PROC_PREPRESIDUAL $CONFIG_PREP_RESIDUAL
 fi
 
 bool 'Default bootloader kernel arguments' CONFIG_CMDLINE_BOOL
@@ -574,15 +581,15 @@ if [ "$CONFIG_8260" = "y" ]; then
    source arch/ppc/8260_io/Config.in
 fi
 
-if [ "$CONFIG_4xx" = "y"]; then
+if [ "$CONFIG_40x" = "y" ]; then
    mainmenu_option next_comment
-   comment 'IBM 4xx options'
+   comment 'IBM 40x options'
    if [ "$CONFIG_STB03xxx" = "y" ]; then
       bool 'STB IR Keyboard' CONFIG_STB_KB
       bool 'SICC Serial port' CONFIG_SERIAL_SICC
       if [ "$CONFIG_SERIAL_SICC" = "y" -a "$CONFIG_UART0_TTYS1" = "y" ]; then
-         define_bool CONFIG_UART1_DFLT_CONSOLE y	
-         define_bool CONFIG_SERIAL_SICC_CONSOLE y
+	 define_bool CONFIG_UART1_DFLT_CONSOLE y	
+	 define_bool CONFIG_SERIAL_SICC_CONSOLE y
       fi
    fi
    endmenu
@@ -621,8 +628,8 @@ if [ "$CONFIG_ALL_PPC" = "y" ]; then
 fi
 if [ "$CONFIG_4xx" = "y" -o "$CONFIG_GT64260" = "y"		\
      -o "$CONFIG_LOPEC" = "y" -o "$CONFIG_MCPN765" = "y"	\
-     -o "$CONFIG_PRPMC800" = "y" -o "$CONFIG_SANDPOINT" = "y"	\
-     -o "$CONFIG_ZX4500" = "y" ]; then
+     -o "$CONFIG_PPLUS" = "y" -o "$CONFIG_PRPMC800" = "y"	\
+     -o "$CONFIG_SANDPOINT" = "y" -o "$CONFIG_ZX4500" = "y" ]; then
    bool 'Support for early boot texts over serial port' CONFIG_SERIAL_TEXT_DEBUG
 fi
 endmenu

arch/ppc/kernel/Makefile

@@ -21,7 +21,7 @@ CFLAGS_btext.o		+= -mrelocatable-lib
 
 # Start off with 'head.o', change as needed.
 HEAD-y				:= head.o
-HEAD-$(CONFIG_4xx)		:= head_4xx.o
+HEAD-$(CONFIG_40x)		:= head_4xx.o
 HEAD-$(CONFIG_8xx)		:= head_8xx.o
 HEAD-$(CONFIG_PPC_ISERIES)	:= iSeries_head.o
 
@@ -54,19 +54,18 @@ obj-$(CONFIG_PM)		+= ppc4xx_pm.o
 endif
 obj-$(CONFIG_8xx)		+= m8xx_setup.o ppc8xx_pic.o
 ifeq ($(CONFIG_8xx),y)
-obj-$(CONFIG_PCI)		+= qspan_pci.o
-ifndef CONFIG_MATH_EMULATION
+obj-$(CONFIG_PCI)		+= qspan_pci.o i8259.o
+ifneq ($(CONFIG_MATH_EMULATION),n)
 obj-y				+= softemu8xx.o
 endif
 endif
-obj-$(CONFIG_MBX)		+= i8259.o
 obj-$(CONFIG_ALL_PPC)		+= prom_init.o prom.o open_pic.o \
 					indirect_pci.o i8259.o
 obj-$(CONFIG_ADIR)		+= i8259.o indirect_pci.o pci_auto.o \
 					todc_time.o
 obj-$(CONFIG_EV64260)		+= gt64260_common.o gt64260_pic.o \
 					indirect_pci.o todc_time.o pci_auto.o
-obj-$(CONFIG_GEMINI)		+= open_pic.o
+obj-$(CONFIG_GEMINI)		+= open_pic.o i8259.o
 obj-$(CONFIG_K2)		+= i8259.o indirect_pci.o todc_time.o \
 					pci_auto.o
 obj-$(CONFIG_LOPEC)		+= mpc10x_common.o indirect_pci.o pci_auto.o \

arch/ppc/kernel/cputable.c

@@ -283,7 +283,7 @@ struct cpu_spec	cpu_specs[] = {
 	__setup_cpu_8xx	/* Empty */
     },
 #endif /* CONFIG_8xx */
-#ifdef CONFIG_4xx
+#ifdef CONFIG_40x
     {	/* 403GC */
     	0xffffff00, 0x00200200, "403GC",
     	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
@@ -333,7 +333,38 @@ struct cpu_spec	cpu_specs[] = {
 	16, 8,
 	0, /*__setup_cpu_405 */
     },
-#endif /* CONFIG_4xx */
+    {	/* NP4GS3 */
+    	0xffff0000, 0x40B10000, "NP4GS3",
+    	CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
+    	PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
+	16, 8,
+	0, /*__setup_cpu_405 */
+    },
+    {   /* NP405H */
+        0xffff0000, 0x41410000, "NP405H",
+        CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
+        PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
+        16, 8,
+        0, /*__setup_cpu_405 */
+     },
+
+#endif /* CONFIG_40x */
+#ifdef CONFIG_440
+    { /* 440GP Rev. B */
+        0xf0000fff, 0x40000440, "440GP Rev. B",
+        CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
+        PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
+        32, 32,
+        0, /*__setup_cpu_440 */
+    },
+    { /* 440GP Rev. C */
+        0xf0000fff, 0x40000481, "440GP Rev. C",
+        CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
+        PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
+        32, 32,
+        0, /*__setup_cpu_440 */
+    },
+#endif /* CONFIG_440 */
 #if !CLASSIC_PPC
     {	/* default match */
     	0x00000000, 0x00000000, "(generic PPC)",

arch/ppc/kernel/head.S

@@ -507,7 +507,6 @@ InstructionTLBMiss:
 	lwz	r2,0(r2)		/* get pmd entry */
 	rlwinm.	r2,r2,0,0,19		/* extract address of pte page */
 	beq-	InstructionAddressInvalid	/* return if no mapping */
-	tophys(r2,r2)
 	rlwimi	r2,r3,22,20,29		/* insert next 10 bits of address */
 	lwz	r3,0(r2)		/* get linux-style pte */
 	andc.	r1,r1,r3		/* check access & ~permission */
@@ -582,7 +581,6 @@ DataLoadTLBMiss:
 	lwz	r2,0(r2)		/* get pmd entry */
 	rlwinm.	r2,r2,0,0,19		/* extract address of pte page */
 	beq-	DataAddressInvalid	/* return if no mapping */
-	tophys(r2,r2)
 	rlwimi	r2,r3,22,20,29		/* insert next 10 bits of address */
 	lwz	r3,0(r2)		/* get linux-style pte */
 	andc.	r1,r1,r3		/* check access & ~permission */
@@ -655,7 +653,6 @@ DataStoreTLBMiss:
 	lwz	r2,0(r2)		/* get pmd entry */
 	rlwinm.	r2,r2,0,0,19		/* extract address of pte page */
 	beq-	DataAddressInvalid	/* return if no mapping */
-	tophys(r2,r2)
 	rlwimi	r2,r3,22,20,29		/* insert next 10 bits of address */
 	lwz	r3,0(r2)		/* get linux-style pte */
 	andc.	r1,r1,r3		/* check access & ~permission */

arch/ppc/kernel/i8259.c

@@ -21,17 +21,37 @@ static spinlock_t i8259_lock = SPIN_LOCK_UNLOCKED;
 
 int i8259_pic_irq_offset;
 
-/* Acknowledge the irq using the PCI host bridge's interrupt acknowledge
- * feature. (Polling is somehow broken on some IBM and Motorola PReP boxes.)
+/*
+ * Acknowledge the IRQ using either the PCI host bridge's interrupt
+ * acknowledge feature or poll.  How i8259_init() is called determines
+ * which is called.  It should be noted that polling is broken on some
+ * IBM and Motorola PReP boxes so we must use the int-ack feature on them.
  */
-int i8259_irq(struct pt_regs *regs)
+int
+i8259_irq(struct pt_regs *regs)
 {
 	int irq;
 
-	spin_lock/*_irqsave*/(&i8259_lock/*, flags*/);
+	spin_lock(&i8259_lock);
+
+	/* Either int-ack or poll for the IRQ */
+	if (pci_intack)
+		irq = *pci_intack;
+	else {
+		/* Perform an interrupt acknowledge cycle on controller 1. */
+		outb(0x0C, 0x20);		/* prepare for poll */
+		irq = inb(0x20) & 7;
+		if (irq == 2 ) {
+			/*
+			 * Interrupt is cascaded so perform interrupt
+			 * acknowledge on controller 2.
+			 */
+			outb(0x0C, 0xA0);	/* prepare for poll */
+			irq = (inb(0xA0) & 7) + 8;
+		}
+	}
 
-	irq = *pci_intack;
-	if (irq==7) {
+	if (irq == 7) {
 		/*
 		 * This may be a spurious interrupt.
 		 *
@@ -39,47 +59,13 @@ int i8259_irq(struct pt_regs *regs)
 		 * significant bit is not set then there is no valid
 		 * interrupt.
 		 */
-		if(~inb(0x20)&0x80) {
+		if (!pci_intack)
+			outb(0x0B, 0x20);	/* ISR register */
+		if(~inb(0x20) & 0x80)
 			irq = -1;
-		}
 	}
-	spin_unlock/*_irqrestore*/(&i8259_lock/*, flags*/);
-	return irq;
-}
 
-/* Poke the 8259's directly using poll commands. */
-int i8259_poll(void)
-{
-	int irq;
-
-	spin_lock/*_irqsave*/(&i8259_lock/*, flags*/);
-	/*
-	 * Perform an interrupt acknowledge cycle on controller 1
-	 */
-	outb(0x0C, 0x20); /* prepare for poll */
-	irq = inb(0x20) & 7;
-	if (irq == 2) {
-		/*
-		 * Interrupt is cascaded so perform interrupt
-		 * acknowledge on controller 2
-		 */
-		outb(0x0C, 0xA0); /* prepare for poll */
-		irq = (inb(0xA0) & 7) + 8;
-	} else if (irq==7) {
-		/*
-		 * This may be a spurious interrupt
-		 *
-		 * Read the interrupt status register. If the most
-		 * significant bit is not set then there is no valid
-		 * interrupt
-		 */
-		outb(0x0b, 0x20);
-		if(~inb(0x20)&0x80) {
-			spin_unlock/*_irqrestore*/(&i8259_lock/*, flags*/);
-			return -1;
-		}
-	}
-	spin_unlock/*_irqrestore*/(&i8259_lock/*, flags*/);
+	spin_unlock(&i8259_lock);
 	return irq;
 }
 
@@ -171,11 +157,13 @@ static struct resource pic_edgectrl_iores = {
 	"8259 edge control", 0x4d0, 0x4d1, IORESOURCE_BUSY
 };
 
-/* i8259_init()
+/*
+ * i8259_init()
  * intack_addr - PCI interrupt acknowledge (real) address which will return
  *               the active irq from the 8259
  */
-void __init i8259_init(long intack_addr)
+void __init
+i8259_init(long intack_addr)
 {
 	unsigned long flags;
 
@@ -209,9 +197,6 @@ void __init i8259_init(long intack_addr)
 	request_resource(&ioport_resource, &pic2_iores);
 	request_resource(&ioport_resource, &pic_edgectrl_iores);
 
-	/* XXX remove me after board maintainers fix their i8259_init calls */
-	if (intack_addr == 0)
-		panic("You must supply a PCI interrupt acknowledge address to i8259_init()\n");
-
-	pci_intack = ioremap(intack_addr, 1);
+	if (intack_addr != 0)
+		pci_intack = ioremap(intack_addr, 1);
 }

arch/ppc/kernel/misc.S

@@ -354,7 +354,7 @@ _GLOBAL(_nmask_and_or_msr)
  * Flush MMU TLB
  */
 _GLOBAL(_tlbia)
-#if defined(CONFIG_4xx) && defined(CONFIG_PIN_TLB)
+#if defined(CONFIG_40x) && defined(CONFIG_PIN_TLB)
 	/* This needs to be coordinated with other pinning functions since
 	 * we don't keep a memory location of number of entries to reduce
 	 * cache pollution during these operations.
@@ -401,14 +401,14 @@ _GLOBAL(_tlbia)
 	tlbia
 	sync
 #endif /* CONFIG_SMP */
-#endif /* CONFIG_4xx */
+#endif /* defined(CONFIG_40x) && defined(CONFIG_PIN_TLB) */
 	blr	
 
 /*
  * Flush MMU TLB for a particular address
  */
 _GLOBAL(_tlbie)
-#ifdef CONFIG_4xx
+#ifdef CONFIG_40x
 	tlbsx.	r3, 0, r3
 	bne	10f
 	sync
@@ -418,7 +418,7 @@ _GLOBAL(_tlbie)
 	tlbwe	r3, r3, TLB_TAG
 	isync
 10:
-#else
+#else /* ! CONFIG_40x */
 #if defined(CONFIG_SMP)
 	rlwinm	r8,r1,0,0,18
 	lwz	r8,TI_CPU(r8)
@@ -451,7 +451,7 @@ _GLOBAL(_tlbie)
 	tlbie	r3
 	sync
 #endif /* CONFIG_SMP */
-#endif /* CONFIG_4xx */
+#endif /* ! CONFIG_40x */
 	blr
 
 /*
@@ -463,7 +463,7 @@ _GLOBAL(flush_instruction_cache)
 	isync
 	lis	r5, IDC_INVALL@h
 	mtspr	IC_CST, r5
-#elif defined(CONFIG_4xx)
+#elif defined(CONFIG_40x)
 #ifdef CONFIG_403GCX
 	li      r3, 512
 	mtctr   r3

arch/ppc/kernel/open_pic.c

@@ -799,26 +799,20 @@ static void openpic_ipi_action(int cpl, void *dev_id, struct pt_regs *regs)
 
 #endif /* CONFIG_SMP */
 
-/* This one may be merged with PReP and CHRP */
 int
 openpic_get_irq(struct pt_regs *regs)
 {
-/*
- * Clean up needed. -VAL
- */
 	int irq = openpic_irq();
 
-	/* Management of the cascade should be moved out of here */
-
-	/* Yep - because openpic !=> i8259, for one thing. -VAL */
-	if (open_pic_irq_offset && irq == open_pic_irq_offset)
-	{
-#ifndef CONFIG_GEMINI
-		irq = i8259_irq(regs); /* get IRQ from cascade */
-#endif
+	/*
+	 * This needs to be cleaned up.  We don't necessarily have
+	 * an i8259 cascaded or even a cascade.
+	 */
+	if (open_pic_irq_offset && irq == open_pic_irq_offset) {
+		/* Get the IRQ from the cascade. */
+		irq = i8259_irq(regs);
 		openpic_eoi();
-	}
-	if (irq == OPENPIC_VEC_SPURIOUS + open_pic_irq_offset)
+	} else if (irq == OPENPIC_VEC_SPURIOUS + open_pic_irq_offset)
 		irq = -1;
 	return irq;
 }

arch/ppc/kernel/ppc-stub.c

@@ -514,7 +514,7 @@ static struct hard_trap_info
 	unsigned int tt;		/* Trap type code for powerpc */
 	unsigned char signo;		/* Signal that we map this trap into */
 } hard_trap_info[] = {
-#if defined(CONFIG_4xx)
+#if defined(CONFIG_40x)
 	{ 0x100, SIGINT  },		/* critical input interrupt */
 	{ 0x200, SIGSEGV },		/* machine check */
 	{ 0x300, SIGSEGV },		/* data storage */
@@ -613,7 +613,7 @@ handle_exception (struct pt_regs *regs)
 	sigval = computeSignal(regs->trap);
 	ptr = remcomOutBuffer;
 
-#if defined(CONFIG_4xx)
+#if defined(CONFIG_40x)
 	*ptr++ = 'S';
 	*ptr++ = hexchars[sigval >> 4];
 	*ptr++ = hexchars[sigval & 0xf];
@@ -785,7 +785,7 @@ handle_exception (struct pt_regs *regs)
  * some location may have changed something that is in the instruction cache.
  */
 			kgdb_flush_cache_all();
-#if defined(CONFIG_4xx)
+#if defined(CONFIG_40x)
 			strcpy(remcomOutBuffer, "OK");
 			putpacket(remcomOutBuffer);
 #endif
@@ -802,7 +802,7 @@ handle_exception (struct pt_regs *regs)
 
 		case 's':
 			kgdb_flush_cache_all();
-#if defined(CONFIG_4xx)
+#if defined(CONFIG_40x)
 			regs->msr |= MSR_DE;
 			regs->dbcr0 |= (DBCR0_IDM | DBCR0_IC);
 			set_msr(msr);

arch/ppc/mm/Makefile

@@ -21,7 +21,7 @@ obj-y				:= fault.o init.o mem_pieces.o extable.o \
 
 obj-$(CONFIG_PPC_STD_MMU)	+= hashtable.o ppc_mmu.o tlb.o
 obj-$(CONFIG_PPC_ISERIES)	+= iSeries_hashtable.o iSeries_mmu.o tlb.o
-obj-$(CONFIG_4xx)		+= 4xx_mmu.o
+obj-$(CONFIG_40x)		+= 4xx_mmu.o
 obj-$(CONFIG_NOT_COHERENT_CACHE)	+= cachemap.o
 
 include $(TOPDIR)/Rules.make

arch/ppc/platforms/Makefile

@@ -12,7 +12,7 @@
 ifdef CONFIG_PPC64BRIDGE
 EXTRA_AFLAGS		:= -Wa,-mppc64bridge
 endif
-ifdef CONFIG_4xx
+ifdef CONFIG_40x
 EXTRA_AFLAGS		:= -Wa,-m405
 endif
 

arch/ppc/platforms/ep405.c

@@ -32,42 +32,51 @@
 #define DBG(x...)
 #endif
 
-void *ep405_bcsr;
-void *ep405_nvram;
+u8 *ep405_bcsr;
+u8 *ep405_nvram;
+
+static struct {
+	u8 cpld_xirq_select;
+	int pci_idsel;
+	int irq;
+} ep405_devtable[] = {
+#ifdef CONFIG_EP405PC
+	{0x07, 0x0E, 25},		/* EP405PC: USB */
+#endif
+};
+#define EP405_DEVTABLE_SIZE (sizeof(ep405_devtable)/sizeof(ep405_devtable[0]))
 
 int __init
 ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
 {
-	static char pci_irq_table[][4] =
-	    /*
-	     *      PCI IDSEL/INTPIN->INTLINE
-	     *      A       B       C       D
-	     */
-	{
-		{28, 28, 28, 28},	/* IDSEL 1 - PCI slot 1 */
-		{29, 29, 29, 29},	/* IDSEL 2 - PCI slot 2 */
-		{30, 30, 30, 30},	/* IDSEL 3 - PCI slot 3 */
-		{31, 31, 31, 31},	/* IDSEL 4 - PCI slot 4 */
-	};
-	const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
-	return PCI_IRQ_TABLE_LOOKUP;
+	int i;
+
+	/* AFAICT this is only called a few times during PCI setup, so
+	   performance is not critical */
+	for (i = 0; i < EP405_DEVTABLE_SIZE; i++) {
+		if (idsel == ep405_devtable[i].pci_idsel)
+			return ep405_devtable[i].irq;
+	}
+	return -1;
 };
 
 void __init
 board_setup_arch(void)
 {
+	bd_t *bip = (bd_t *) __res;
+
 #ifdef CONFIG_PPC_RTC
-	/* FIXME: what if NVRAM size is not 512k */
-	TODC_INIT(TODC_TYPE_DS1557, ep405_nvram, ep405_nvram, ep405_nvram, 8);
-#endif				/* CONFIG_PPC_RTC */
+	if (bip->bi_nvramsize == 512*1024) {
+		/* FIXME: we should properly handle NVRTCs of different sizes */
+		TODC_INIT(TODC_TYPE_DS1557, ep405_nvram, ep405_nvram, ep405_nvram, 8);
+	}
+#endif
 }
 
 void __init
-bios_fixup(struct pci_controller *hose, void *pcil0_base)
+bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
 {
-
 	unsigned int bar_response, bar;
-	struct pcil0_regs *pcip;
 	/*
 	 * Expected PCI mapping:
 	 *
@@ -82,29 +91,7 @@ bios_fixup(struct pci_controller *hose, void *pcil0_base)
 	 *
 	 */
 
-#ifdef DEBUG
-	int i;
-	pcip = (struct pcil0_regs *) pcil0_base;
-
-	printk("ioremap PCLIO_BASE = 0x%x\n", pcip);
-	printk("PCI bridge regs before fixup \n");
-	for (i = 0; i <= 3; i++) {
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
-	}
-	printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
-	printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
-	printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
-	printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
-
-#else
-	pcip = (struct pcil0_regs *) pcil0_base;
-#endif
-	/* added for IBM boot rom version 1.15 bios bar changes  -AK */
-
-	/* Disable region first */
+	/* Disable region zero first */
 	out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
 	/* PLB starting addr, PCI: 0x80000000 */
 	out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
@@ -133,6 +120,11 @@ bios_fixup(struct pci_controller *hose, void *pcil0_base)
 	out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
 	out_le32((void *) &(pcip->ptm2ms), 0x00000000);
 
+	/* Configure PTM (PCI->PLB) region 1 */
+	out_le32((void *) &(pcip->ptm1la), 0x00000000); /* PLB base address */
+	/* Disable PTM region 2 */
+	out_le32((void *) &(pcip->ptm2ms), 0x00000000);
+
 	/* Zero config bars */
 	for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
 		early_write_config_dword(hose, hose->first_busno,
@@ -146,42 +138,60 @@ bios_fixup(struct pci_controller *hose, void *pcil0_base)
 		    PCI_FUNC(hose->first_busno), bar, bar_response);
 	}
 	/* end work arround */
-
-#ifdef DEBUG
-	printk("PCI bridge regs after fixup \n");
-	for (i = 0; i <= 3; i++) {
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
-	}
-	printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
-	printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
-	printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
-	printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
-#endif
 }
 
 void __init
 board_io_mapping(void)
 {
+	bd_t *bip = (bd_t *) __res;
+
 	ep405_bcsr = ioremap(EP405_BCSR_PADDR, EP405_BCSR_SIZE);
-	ep405_nvram = ioremap(EP405_NVRAM_PADDR, EP405_NVRAM_SIZE);
+
+	if (bip->bi_nvramsize > 0) {
+		ep405_nvram = ioremap(EP405_NVRAM_PADDR, bip->bi_nvramsize);
+	}
 }
 
 void __init
 board_setup_irq(void)
 {
+	int i;
+
+	/* Workaround for a bug in the firmware it incorrectly sets
+	   the IRQ polarities for XIRQ0 and XIRQ1 */
+	mtdcr(DCRN_UIC_PR(DCRN_UIC0_BASE), 0xffffff80); /* set the polarity */
+	mtdcr(DCRN_UIC_SR(DCRN_UIC0_BASE), 0x00000060); /* clear bogus interrupts */
+
+	/* Activate the XIRQs from the CPLD */
+	writeb(0xf0, ep405_bcsr+10);
+
+	/* Set up IRQ routing */
+	for (i = 0; i < EP405_DEVTABLE_SIZE; i++) {
+		if ( (ep405_devtable[i].irq >= 25)
+		     && (ep405_devtable[i].irq) <= 31) {
+			writeb(ep405_devtable[i].cpld_xirq_select, ep405_bcsr+5);
+			writeb(ep405_devtable[i].irq - 25, ep405_bcsr+6);
+		}
+	}
 }
 
 void __init
 board_init(void)
 {
+	bd_t *bip = (bd_t *) __res;
+
 #ifdef CONFIG_PPC_RTC
-	ppc_md.time_init = todc_time_init;
-	ppc_md.set_rtc_time = todc_set_rtc_time;
-	ppc_md.get_rtc_time = todc_get_rtc_time;
+	/* FIXME: we should be able to access the NVRAM even if PPC_RTC is not configured */
 	ppc_md.nvram_read_val = todc_direct_read_val;
 	ppc_md.nvram_write_val = todc_direct_write_val;
+
+	if (bip->bi_nvramsize == 512*1024) {
+		ppc_md.time_init = todc_time_init;
+		ppc_md.set_rtc_time = todc_set_rtc_time;
+		ppc_md.get_rtc_time = todc_get_rtc_time;
+	} else {
+		printk("EP405: NVRTC size is not 512k (not a DS1557).  Not sure what to do with it\n");
+	}
+
 #endif
 }

arch/ppc/platforms/ep405.h

@@ -22,37 +22,20 @@ typedef struct board_info {
 	unsigned int	 bi_intfreq;		/* Processor speed, in Hz */
 	unsigned int	 bi_busfreq;		/* PLB Bus speed, in Hz */
 	unsigned int	 bi_pci_busfreq;	/* PCI Bus speed, in Hz */
+	unsigned int	 bi_nvramsize;		/* Size of the NVRAM/RTC */
 } bd_t;
 
 /* Some 4xx parts use a different timebase frequency from the internal clock.
 */
 #define bi_tbfreq bi_intfreq
 
-extern void *ep405_bcsr;
-extern void *ep405_nvram;
+extern u8 *ep405_bcsr;
+extern u8 *ep405_nvram;
 
 /* Map for the BCSR and NVRAM space */
 #define EP405_BCSR_PADDR	((uint)0xf4000000)
 #define EP405_BCSR_SIZE		((uint)16)
 #define EP405_NVRAM_PADDR	((uint)0xf4200000)
-/* FIXME: what if the board has something other than 512k NVRAM */
-#define EP405_NVRAM_SIZE	((uint)512*1024)
-
-/* Early initialization address mapping for block_io.
- * Standard 405GP map.
- */
-#define PPC4xx_PCI_IO_PADDR	((uint)PPC405_PCI_PHY_IO_BASE)
-#define PPC4xx_PCI_IO_VADDR	PPC4xx_PCI_IO_PADDR
-#define PPC4xx_PCI_IO_SIZE	((uint)64*1024)
-#define PPC4xx_PCI_CFG_PADDR	((uint)PPC405_PCI_CONFIG_ADDR)
-#define PPC4xx_PCI_CFG_VADDR	PPC4xx_PCI_CFG_PADDR
-#define PPC4xx_PCI_CFG_SIZE	((uint)4*1024)
-#define PPC4xx_PCI_LCFG_PADDR	((uint)0xef400000)
-#define PPC4xx_PCI_LCFG_VADDR	PPC4xx_PCI_LCFG_PADDR
-#define PPC4xx_PCI_LCFG_SIZE	((uint)4*1024)
-#define PPC4xx_ONB_IO_PADDR	((uint)0xef600000)
-#define PPC4xx_ONB_IO_VADDR	PPC4xx_ONB_IO_PADDR
-#define PPC4xx_ONB_IO_SIZE	((uint)4*1024)
 
 /* serial defines */
 #define BASE_BAUD		399193

arch/ppc/platforms/ibm405.h

@@ -32,6 +32,9 @@
  *
  *	Version 1.0 (02/01/17) - A. Kuster
  *	Initial version	 - moved 405  specific out of the other core.h's
+ *
+ *	Version 1.0 (02/08/02) - A. Kuster
+ *	removed DCRN_UIC1_BASE to NP405L & H
  */
 
 #ifdef __KERNEL__
@@ -57,7 +60,6 @@
 #define DCRN_CHCR0	(DCRN_CHCR_BASE + 0x0)	/* Chip Control Register 1 */
 #define DCRN_CHCR1	(DCRN_CHCR_BASE + 0x1)	/* Chip Control Register 2 */
 #endif
-#define CHR1_CETE	0x00800000	/* CPU external timer enable */
 #define CHR1_PCIPW	0x00008000	/* PCI Int enable/Peripheral Write enable */
 
 #ifdef DCRN_CHPSR_BASE
@@ -211,25 +213,38 @@
 #define IOCR_SCS	0x00000002
 #define IOCR_SPC	0x00000001
 
-#ifdef DCRN_MAL_BASE
-#define DCRN_MALCR		(DCRN_MAL_BASE + 0x0)	/* MAL Configuration */
-#define DCRN_MALDBR		(DCRN_MAL_BASE + 0x3)	/* Debug Register */
-#define DCRN_MALESR		(DCRN_MAL_BASE + 0x1)	/* Error Status */
-#define DCRN_MALIER		(DCRN_MAL_BASE + 0x2)	/* Interrupt Enable */
-#define DCRN_MALTXCARR		(DCRN_MAL_BASE + 0x5)	/* TX Channed Active Reset Register */
-#define DCRN_MALTXCASR		(DCRN_MAL_BASE + 0x4)	/* TX Channel Active Set Register */
-#define DCRN_MALTXDEIR		(DCRN_MAL_BASE + 0x7)	/* Tx Descriptor Error Interrupt */
-#define DCRN_MALTXEOBISR	(DCRN_MAL_BASE + 0x6)	/* Tx End of Buffer Interrupt Status */
-#define DCRN_MALRXCARR		(DCRN_MAL_BASE + 0x11)	/* RX Channed Active Reset Register */
-#define DCRN_MALRXCASR		(DCRN_MAL_BASE + 0x10)	/* RX Channel Active Set Register */
-#define DCRN_MALRXDEIR		(DCRN_MAL_BASE + 0x13)	/* Rx Descriptor Error Interrupt */
-#define DCRN_MALRXEOBISR	(DCRN_MAL_BASE + 0x12)	/* Rx End of Buffer Interrupt Status */
-#define DCRN_MALRXCTP0R		(DCRN_MAL_BASE + 0x40)	/* Channel Rx 0 Channel Table Pointer */
-#define DCRN_MALTXCTP0R		(DCRN_MAL_BASE + 0x20)	/* Channel Tx 0 Channel Table Pointer */
-#define DCRN_MALTXCTP1R		(DCRN_MAL_BASE + 0x21)	/* Channel Tx 1 Channel Table Pointer */
-#define DCRN_MALRCBS0		(DCRN_MAL_BASE + 0x60)	/* Channel Rx 0 Channel Buffer Size */
-#endif
-	/* DCRN_MALCR */
+#define DCRN_MALCR(base)	(base + 0x0)	/* MAL Configuration */
+#define DCRN_MALDBR(base)	((base) + 0x3)	/* Debug Register */
+#define DCRN_MALESR(base)	((base) + 0x1)	/* Error Status */
+#define DCRN_MALIER(base)	((base) + 0x2)	/* Interrupt Enable */
+#define DCRN_MALTXCARR(base)	((base) + 0x5)	/* TX Channed Active Reset Register */
+#define DCRN_MALTXCASR(base)	((base) + 0x4)	/* TX Channel Active Set Register */
+#define DCRN_MALTXDEIR(base)	((base) + 0x7)	/* Tx Descriptor Error Interrupt */
+#define DCRN_MALTXEOBISR(base)	((base) + 0x6)	/* Tx End of Buffer Interrupt Status */
+#define DCRN_MALRXCARR(base)	((base) + 0x11)	/* RX Channed Active Reset Register */
+#define DCRN_MALRXCASR(base)	((base) + 0x10)	/* RX Channel Active Set Register */
+#define DCRN_MALRXDEIR(base)	((base) + 0x13)	/* Rx Descriptor Error Interrupt */
+#define DCRN_MALRXEOBISR(base)	((base) + 0x12)	/* Rx End of Buffer Interrupt Status */
+#define DCRN_MALRXCTP0R(base)	((base) + 0x40)	/* Channel Rx 0 Channel Table Pointer */
+#define DCRN_MALRXCTP1R(base)	((base) + 0x41)	/* Channel Rx 1 Channel Table Pointer */
+#define DCRN_MALTXCTP0R(base)	((base) + 0x20)	/* Channel Tx 0 Channel Table Pointer */
+#define DCRN_MALTXCTP1R(base)	((base) + 0x21)	/* Channel Tx 1 Channel Table Pointer */
+#define DCRN_MALTXCTP2R(base)	((base) + 0x22)	/* Channel Tx 2 Channel Table Pointer */
+#define DCRN_MALTXCTP3R(base)	((base) + 0x23)	/* Channel Tx 3 Channel Table Pointer */
+#define DCRN_MALRCBS0(base)	((base) + 0x60)	/* Channel Rx 0 Channel Buffer Size */
+#define DCRN_MALRCBS1(base)	((base) + 0x61)	/* Channel Rx 1 Channel Buffer Size */
+
+/* EMAC DCRN's */
+#define DCRN_MALRXCTP2R(base)	((base) + 0x42)	/* Channel Rx 2 Channel Table Pointer */
+#define DCRN_MALRXCTP3R(base)	((base) + 0x43)	/* Channel Rx 3 Channel Table Pointer */
+#define DCRN_MALTXCTP4R(base)	((base) + 0x24)	/* Channel Tx 4 Channel Table Pointer */
+#define DCRN_MALTXCTP5R(base)	((base) + 0x25)	/* Channel Tx 5 Channel Table Pointer */
+#define DCRN_MALTXCTP6R(base)	((base) + 0x26)	/* Channel Tx 6 Channel Table Pointer */
+#define DCRN_MALTXCTP7R(base)	((base) + 0x27)	/* Channel Tx 7 Channel Table Pointer */
+#define DCRN_MALRCBS2(base)	((base) + 0x62)	/* Channel Rx 2 Channel Buffer Size */
+#define DCRN_MALRCBS3(base)	((base) + 0x63)	/* Channel Rx 3 Channel Buffer Size */
+
+ /* DCRN_MALCR */
 #define MALCR_MMSR		0x80000000	/* MAL Software reset */
 #define MALCR_PLBP_1		0x00400000	/* MAL reqest priority: */
 #define MALCR_PLBP_2		0x00800000	/* lowsest is 00 */
@@ -294,28 +309,14 @@
 #define DCRN_POB0_BESR1	(DCRN_POB0_BASE + 0x4)
 #endif
 
-#ifdef DCRN_UIC0_BASE
-#define DCRN_UIC0_SR	(DCRN_UIC0_BASE + 0x0)
-#define DCRN_UIC0_ER	(DCRN_UIC0_BASE + 0x2)
-#define DCRN_UIC0_CR	(DCRN_UIC0_BASE + 0x3)
-#define DCRN_UIC0_PR	(DCRN_UIC0_BASE + 0x4)
-#define DCRN_UIC0_TR	(DCRN_UIC0_BASE + 0x5)
-#define DCRN_UIC0_MSR	(DCRN_UIC0_BASE + 0x6)
-#define DCRN_UIC0_VR	(DCRN_UIC0_BASE + 0x7)
-#define DCRN_UIC0_VCR	(DCRN_UIC0_BASE + 0x8)
-#endif
-
-#ifdef DCRN_UIC1_BASE
-#define DCRN_UIC1_SR	(DCRN_UIC1_BASE + 0x0)
-#define DCRN_UIC1_SRS	(DCRN_UIC1_BASE + 0x1)
-#define DCRN_UIC1_ER	(DCRN_UIC1_BASE + 0x2)
-#define DCRN_UIC1_CR	(DCRN_UIC1_BASE + 0x3)
-#define DCRN_UIC1_PR	(DCRN_UIC1_BASE + 0x4)
-#define DCRN_UIC1_TR	(DCRN_UIC1_BASE + 0x5)
-#define DCRN_UIC1_MSR	(DCRN_UIC1_BASE + 0x6)
-#define DCRN_UIC1_VR	(DCRN_UIC1_BASE + 0x7)
-#define DCRN_UIC1_VCR	(DCRN_UIC1_BASE + 0x8)
-#endif
+#define DCRN_UIC_SR(base)	(base + 0x0)
+#define DCRN_UIC_ER(base)	(base + 0x2)
+#define DCRN_UIC_CR(base)	(base + 0x3)
+#define DCRN_UIC_PR(base)	(base + 0x4)
+#define DCRN_UIC_TR(base)	(base + 0x5)
+#define DCRN_UIC_MSR(base)	(base + 0x6)
+#define DCRN_UIC_VR(base)	(base + 0x7)
+#define DCRN_UIC_VCR(base)	(base + 0x8)
 
 #ifdef DCRN_SDRAM0_BASE
 #define DCRN_SDRAM0_CFGADDR	(DCRN_SDRAM0_BASE + 0x0)	/* Memory Controller Address */

arch/ppc/platforms/ibm405gp.h

@@ -36,6 +36,13 @@
  *
  *	Version 1.1 02/01/17 - A. Kuster
  *	Moved offsets to ibm405.h
+ *
+ *	Version 1.2 05/01/02 - Armin
+ *	 added IIC_PORT_DFNS
+ *
+ *	Version 1.3 - armin
+ *	  removed iic & uart num defines
+ *	  and IIC_PORT_DFNS
  */
 
 #ifdef __KERNEL__
@@ -88,30 +95,36 @@
 #define UART1_INT	1
 
 #define PCIL0_BASE	0xEF400000
-#define UART0_IO_BASE	(u8 *) 0xEF600300
-#define UART1_IO_BASE	(u8 *) 0xEF600400
+#define UART0_IO_BASE	0xEF600300
+#define UART1_IO_BASE	0xEF600400
 #define IIC0_BASE	0xEF600500
 #define OPB0_BASE	0xEF600600
 #define GPIO0_BASE	0xEF600700
 #define EMAC0_BASE	0xEF600800
 
 #define EMAC_NUMS	1
-#define UART_NUMS	2
+#define IIC0_IRQ	2
+#define IIC1_IRQ	0
+
+#define IIC_OWN		0x55
+#define IIC_CLOCK	50
 #define BD_EMAC_ADDR(e,i) bi_enetaddr[i]
 
 #define STD_UART_OP(num)					\
 	{ 0, BASE_BAUD, 0, UART##num##_INT,			\
 		(ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST),	\
-		iomem_base: UART##num##_IO_BASE,		\
+		iomem_base: (u8 *)UART##num##_IO_BASE,		\
 		io_type: SERIAL_IO_MEM},
 
 #if defined(CONFIG_UART0_TTYS0)
+#define SERIAL_DEBUG_IO_BASE	UART0_IO_BASE
 #define SERIAL_PORT_DFNS	\
 	STD_UART_OP(0)		\
 	STD_UART_OP(1)
 #endif
 
 #if defined(CONFIG_UART0_TTYS1)
+#define SERIAL_DEBUG_IO_BASE	UART1_IO_BASE
 #define SERIAL_PORT_DFNS	\
 	STD_UART_OP(1)		\
 	STD_UART_OP(0)
@@ -123,6 +136,11 @@
 #define DCRN_CPMSR_BASE		0x0B8
 #define DCRN_CPMFR_BASE		0x0BA
 
+#define CHR0_U0EC	0x00000080	/* Select external clock for UART0 */
+#define CHR0_U1EC	0x00000040	/* Select external clock for UART1 */
+#define CHR0_UDIV	0x0000003E	/* UART internal clock divisor */
+#define CHR1_CETE	0x00800000	/* CPU external timer enable */
+
 #define DCRN_CHPSR_BASE         0x0B4
 #define  PSR_PLL_FWD_MASK        0xC0000000
 #define  PSR_PLL_FDBACK_MASK     0x30000000
@@ -169,6 +187,7 @@
 #define DCRN_POB0_BASE		0x0A0
 #define DCRN_SDRAM0_BASE	0x010
 #define DCRN_UIC0_BASE		0x0C0
+#define UIC0 DCRN_UIC0_BASE
 
 #include <platforms/ibm405.h>
 

arch/ppc/platforms/ibm_ocp.h

 /*
- * ibm_ips.h
+ * ibm_ocp.h
  *
  *	This was dirived from the ppc4xx.h and all 405GP specific definition and board
  *	inclusions where moved here.
@@ -36,8 +36,8 @@
  */
 
 #ifdef __KERNEL__
-#ifndef __ASM_IBM_IPS_H__
-#define __ASM_IBM_IPS_H__
+#ifndef __ASM_IBM_OCP_H__
+#define __ASM_IBM_OCP_H__
 
 #ifndef __ASSEMBLY__
 #include <linux/types.h>
@@ -188,5 +188,5 @@ typedef struct ide_regs {
 } ide_t;
 
 #endif				/* __ASSEMBLY__ */
-#endif				/* __ASM_IBM_IPS_H__ */
+#endif				/* __ASM_IBM_OCP_H__ */
 #endif				/* __KERNEL__ */

arch/ppc/platforms/lopec_pci.c

@@ -6,7 +6,7 @@
  * Author: Dan Cox
  *         danc@mvista.com (or, alternately, source@mvista.com)
  *
- * Copyright 2001 MontaVista Software Inc.
+ * Copyright 2001-2002 MontaVista Software Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -14,18 +14,11 @@
  * option) any later version.
  */
 
-#include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/pci.h>
-#include <linux/slab.h>
 
 #include <asm/machdep.h>
-#include <asm/byteorder.h>
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/uaccess.h>
 #include <asm/pci-bridge.h>
-#include <asm/open_pic.h>
 #include <asm/mpc10x.h>
 
 static inline int __init

arch/ppc/platforms/lopec_setup.c

@@ -15,34 +15,23 @@
  */
 
 #include <linux/config.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/pci.h>
-#include <linux/time.h>
 #include <linux/types.h>
-#include <linux/major.h>
-#include <linux/kdev_t.h>
+#include <linux/delay.h>
+#include <linux/pci_ids.h>
+#include <linux/ioport.h>
+#include <linux/init.h>
 #include <linux/ide.h>
-#include <linux/irq.h>
 #include <linux/seq_file.h>
+#include <linux/blk.h>
 #include <linux/console.h>
 
-#include <asm/system.h>
-#include <asm/pgtable.h>
-#include <asm/machdep.h>
-#include <asm/page.h>
-#include <asm/dma.h>
 #include <asm/io.h>
-#include <asm/time.h>
-#include <asm/delay.h>
-#include <asm/irq.h>
 #include <asm/open_pic.h>
 #include <asm/i8259.h>
-#include <asm/pci-bridge.h>
 #include <asm/todc.h>
 #include <asm/bootinfo.h>
 #include <asm/mpc10x.h>
+#include <asm/hw_irq.h>
 
 extern void lopec_find_bridges(void);
 
@@ -230,7 +219,7 @@ lopec_init_IRQ(void)
 	i8259_init(0xfef00000);
 }
 
-void __init
+static int __init
 lopec_request_io(void)
 {
 	outb(0x00, 0x4d0);
@@ -242,9 +231,11 @@ lopec_request_io(void)
 	request_region(0x80, 0x10, "dma page reg");
 	request_region(0xa0, 0x20, "pic2");
 	request_region(0xc0, 0x20, "dma2");
+	
+	return 0;
 }
 
-arch_initcall(lopec_request_io);
+device_initcall(lopec_request_io);
 
 static void __init
 lopec_map_io(void)

arch/ppc/platforms/mcpn765_setup.c

@@ -6,7 +6,7 @@
  * Author: Mark A. Greer
  *         mgreer@mvista.com
  *
- * Copyright 2001 MontaVista Software Inc.
+ * Copyright 2001-2002 MontaVista Software Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -31,7 +31,6 @@
 #include <linux/delay.h>
 #include <linux/irq.h>
 #include <linux/ide.h>
-#include <linux/irq.h>
 #include <linux/seq_file.h>
 
 #include <asm/system.h>
@@ -125,7 +124,7 @@ mcpn765_setup_arch(void)
 	OpenPIC_NumInitSenses = sizeof(mcpn765_openpic_initsenses);
 
 	printk("Motorola MCG MCPN765 cPCI Non-System Board\n");
-	printk("MCPN765 port (C) 2001 MontaVista Software, Inc. (source@mvista.com)\n");
+	printk("MCPN765 port (MontaVista Software, Inc. (source@mvista.com))\n");
 
 	if ( ppc_md.progress )
 		ppc_md.progress("mcpn765_setup_arch: exit", 0);

arch/ppc/platforms/pplus_setup.c

@@ -72,7 +72,6 @@
 #include <asm/todc.h>
 #include <asm/bootinfo.h>
 
-#undef CONFIG_SERIAL_TEXT_DEBUG
 #undef DUMP_DBATS
 
 TODC_ALLOC();
@@ -500,9 +499,7 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 
 #ifdef CONFIG_SERIAL_TEXT_DEBUG
 	ppc_md.progress = pplus_progress;
-#else /* !CONFIG_SERIAL_TEXT_DEBUG */
-	ppc_md.progress = NULL;
-#endif /* CONFIG_SERIAL_TEXT_DEBUG */
+#endif
 
 #if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
 	ppc_ide_md.default_irq = pplus_ide_default_irq;

arch/ppc/platforms/prep_setup.c

@@ -117,9 +117,6 @@ prep_show_cpuinfo(struct seq_file *m)
 {
 	extern char *Motherboard_map_name;
 	int cachew;
-#ifdef CONFIG_PREP_RESIDUAL
-	int i;
-#endif
 
 	seq_printf(m, "machine\t\t: PReP %s\n", Motherboard_map_name);
 
@@ -180,6 +177,8 @@ prep_show_cpuinfo(struct seq_file *m)
 no_l2:
 #ifdef CONFIG_PREP_RESIDUAL
 	if (res->ResidualLength != 0) {
+		int i;
+
 		/* print info about SIMMs */
 		seq_printf(m, "simms\t\t: ");
 		for (i = 0; (res->ActualNumMemories) && (i < MAX_MEMS); i++) {
@@ -812,8 +811,8 @@ prep_map_io(void)
 	io_block_mapping(0xf0000000, PREP_ISA_MEM_BASE, 0x08000000, _PAGE_IO);
 }
 
-static void __init
-prep_init2(void)
+static int __init
+prep_request_io(void)
 {
 #ifdef CONFIG_NVRAM
 	request_region(PREP_NVRAM_AS0, 0x8, "nvram");
@@ -822,8 +821,12 @@ prep_init2(void)
 	request_region(0x40,0x20,"timer");
 	request_region(0x80,0x10,"dma page reg");
 	request_region(0xc0,0x20,"dma2");
+
+	return 0;
 }
 
+device_initcall(prep_request_io);
+
 void __init
 prep_init(unsigned long r3, unsigned long r4, unsigned long r5,
 		unsigned long r6, unsigned long r7)
@@ -863,7 +866,6 @@ prep_init(unsigned long r3, unsigned long r4, unsigned long r5,
 	ppc_md.init_IRQ       = prep_init_IRQ;
 	/* this gets changed later on if we have an OpenPIC -- Cort */
 	ppc_md.get_irq        = i8259_irq;
-	ppc_md.init           = prep_init2;
 
 	ppc_md.restart        = prep_restart;
 	ppc_md.power_off      = prep_power_off;

arch/ppc/platforms/residual.c

@@ -876,3 +876,38 @@ PnP_TAG_PACKET __init *PnP_find_large_vendor_packet(unsigned char *p,
 	};
 	return 0; /* not found */
 }
+
+#ifdef CONFIG_PROC_PREPRESIDUAL
+static int proc_prep_residual_read(char * buf, char ** start, off_t off,
+		int count, int *eof, void *data)
+{
+	int n;
+
+	n = res->ResidualLength - off;
+	if (n < 0) {
+		*eof = 1;
+		n = 0;
+	}
+	else {
+		if (n > count)
+			n = count;
+		else
+			*eof = 1;
+
+		memcpy(buf, (char *)res + off, n);
+		*start = buf;
+	}
+
+	return n;
+}
+
+void __init
+proc_prep_residual_init(void)
+{
+	if (res->ResidualLength)
+		create_proc_read_entry("residual", S_IRUGO, NULL,
+					proc_prep_residual_read, NULL);
+}
+
+__initcall(proc_prep_residual_init);
+#endif

arch/ppc/platforms/sandpoint_setup.c

@@ -6,7 +6,7 @@
  * Author: Mark A. Greer
  *         mgreer@mvista.com
  *
- * Copyright 2000, 2001 MontaVista Software Inc.
+ * Copyright 2000-2002 MontaVista Software Inc.
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -71,7 +71,6 @@
 #include <linux/delay.h>
 #include <linux/irq.h>
 #include <linux/ide.h>
-#include <linux/irq.h>
 #include <linux/seq_file.h>
 
 #include <asm/system.h>
@@ -180,7 +179,7 @@ sandpoint_setup_arch(void)
 #endif
 
 	printk("Motorola SPS Sandpoint Test Platform\n");
-	printk("Sandpoint port (C) 2000, 2001 MontaVista Software, Inc. (source@mvista.com)\n");
+	printk("Sandpoint port (MontaVista Software, Inc. (source@mvista.com))\n");
 
 	/* The Sandpoint rom doesn't enable any caches.  Do that now.
 	 * The 7450 portion will also set up the L3s once I get enough

include/asm-ppc/bitops.h

@@ -262,6 +262,18 @@ static __inline__ int ffs(int x)
 	return __ilog2(x & -x) + 1;
 }
 
+/*
+ * fls: find last (most-significant) bit set.
+ * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
+ */
+static __inline__ int fls(unsigned int x)
+{
+	int lz;
+
+	asm ("cntlzw %0,%1" : "=r" (lz) : "r" (x));
+	return 32 - lz;
+}
+
 /*
  * hweightN: returns the hamming weight (i.e. the number
  * of bits set) of a N-bit word

include/asm-ppc/hardirq.h

@@ -59,7 +59,7 @@ static inline int irqs_running (void)
 	for (i = 0; i < smp_num_cpus; i++)
 		if (local_irq_count(i))
 			return 1;
-		return 0;
+	return 0;
 }
 
 static inline void release_irqlock(int cpu)

include/asm-ppc/i8259.h

@@ -9,8 +9,7 @@
 
 extern struct hw_interrupt_type i8259_pic;
 
-void i8259_init(long);
-int i8259_irq(struct pt_regs *regs);
-int i8259_poll(void);
+extern void i8259_init(long intack_addr);
+extern int i8259_irq(struct pt_regs *regs);
 
 #endif /* _PPC_KERNEL_i8259_H */

include/asm-ppc/ibm4xx.h

@@ -16,7 +16,7 @@
 
 #include <linux/config.h>
 
-#ifdef CONFIG_4xx
+#ifdef CONFIG_40x
 
 #if defined(CONFIG_ASH)
 #include <platforms/ash.h>
@@ -54,9 +54,7 @@
 #define PPC4xx_MACHINE_NAME	"Unidentified 4xx class"
 #endif
 
-#ifndef NR_BOARD_IRQS
-#define NR_BOARD_IRQS 0
-#endif
+
 
 /* IO_BASE is for PCI I/O.
  * ISA not supported, just here to resolve copilation.
@@ -95,6 +93,6 @@ extern unsigned char __res[];
 		asm volatile("mtdcr " stringify(rn) ",%0" : : "r" (v));}
 
 #endif /* __ASSEMBLY__ */
-#endif /* CONFIG_4xx */
+#endif /* CONFIG_40x */
 #endif /* __ASM_IBM4XX_H__ */
 #endif /* __KERNEL__ */

include/asm-ppc/io.h

@@ -26,7 +26,7 @@
 #define PREP_ISA_MEM_BASE 	0xc0000000
 #define PREP_PCI_DRAM_OFFSET 	0x80000000
 
-#if defined(CONFIG_4xx)
+#if defined(CONFIG_40x)
 #include <asm/ibm4xx.h>
 #elif defined(CONFIG_8xx)
 #include <asm/mpc8xx.h>
@@ -412,11 +412,43 @@ static inline int isa_check_signature(unsigned long io_addr,
 	return 0;
 }
 
-/* Nothing to do */
+#ifdef CONFIG_NOT_COHERENT_CACHE
+
+/*
+ * DMA-consistent mapping functions for PowerPCs that don't support
+ * cache snooping.  These allocate/free a region of uncached mapped
+ * memory space for use with DMA devices.  Alternatively, you could
+ * allocate the space "normally" and use the cache management functions
+ * to ensure it is consistent.
+ */
+extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle);
+extern void consistent_free(void *vaddr);
+extern void consistent_sync(void *vaddr, size_t size, int rw);
+extern void consistent_sync_page(struct page *page, unsigned long offset,
+				 size_t size, int rw);
+
+#define dma_cache_inv(_start,_size) \
+	invalidate_dcache_range(_start, (_start + _size))
+#define dma_cache_wback(_start,_size) \
+	clean_dcache_range(_start, (_start + _size))
+#define dma_cache_wback_inv(_start,_size) \
+	flush_dcache_range(_start, (_start + _size))
+
+#else /* ! CONFIG_NOT_COHERENT_CACHE */
+
+/*
+ * Cache coherent cores.
+ */
 
 #define dma_cache_inv(_start,_size)		do { } while (0)
 #define dma_cache_wback(_start,_size)		do { } while (0)
 #define dma_cache_wback_inv(_start,_size)	do { } while (0)
 
-#endif
+#define consistent_alloc(gfp, size, handle)	NULL
+#define consistent_free(addr, size)		do { } while (0)
+#define consistent_sync(addr, size, rw)		do { } while (0)
+#define consistent_sync_page(pg, off, sz, rw)	do { } while (0)
+
+#endif /* ! CONFIG_NOT_COHERENT_CACHE */
+#endif /* _PPC_IO_H */
 #endif /* __KERNEL__ */

include/asm-ppc/irq.h

@@ -13,8 +13,22 @@ extern void disable_irq(unsigned int);
 extern void disable_irq_nosync(unsigned int);
 extern void enable_irq(unsigned int);
 
-#if defined(CONFIG_4xx)
+#if defined(CONFIG_40x)
 #include <asm/ibm4xx.h>
+
+#ifndef NR_BOARD_IRQS
+#define NR_BOARD_IRQS 0
+#endif
+
+#ifndef UIC_WIDTH /* Number of interrupts per device */
+#define UIC_WIDTH 32
+#endif
+
+#ifndef NR_UICS /* number  of UIC devices */
+#define NR_UICS 1
+#endif
+
+#if defined (CONFIG_403)
 /*
  * The PowerPC 403 cores' Asynchronous Interrupt Controller (AIC) has
  * 32 possible interrupts, a majority of which are not implemented on
@@ -22,26 +36,36 @@ extern void enable_irq(unsigned int);
  * there are eight internal interrupts for the on-chip serial port
  * (SPU), DMA controller, and JTAG controller.
  *
- * The PowerPC 405 cores' Universal Interrupt Controller (UIC) has 32
+ */
+
+#define	NR_AIC_IRQS 32 
+#define	NR_IRQS	 (NR_AIC_IRQS + NR_BOARD_IRQS)
+
+#elif !defined (CONFIG_403)
+
+/*
+ *  The PowerPC 405 cores' Universal Interrupt Controller (UIC) has 32
  * possible interrupts as well. There are seven, configurable external
  * interrupt pins and there are 17 internal interrupts for the on-chip
  * serial port, DMA controller, on-chip Ethernet controller, PCI, etc.
  *
  */
 
-#define	NR_AIC_IRQS	32
-#define	NR_IRQS		(NR_AIC_IRQS + NR_BOARD_IRQS)
 
+#define NR_UIC_IRQS UIC_WIDTH
+#define NR_IRQS		((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS)
+#endif
 static __inline__ int
 irq_cannonicalize(int irq)
 {
 	return (irq);
 }
 
-#elif defined (CONFIG_NP405)
+#elif defined(CONFIG_440)
+#include <asm/ibm440.h>
 
-#define NR_AIC_IRQS	32
-#define NR_IRQS		(NR_AIC_IRQS + NR_BOARD_IRQS)
+#define	NR_UIC_IRQS	64
+#define	NR_IRQS		(NR_UIC_IRQS + NR_BOARD_IRQS)
 
 static __inline__ int
 irq_cannonicalize(int irq)
@@ -119,7 +143,7 @@ static __inline__ int irq_cannonicalize(int irq)
 	return irq;
 }
 
-#else /* CONFIG_4xx + CONFIG_8xx */
+#else /* CONFIG_40x + CONFIG_8xx */
 /*
  * this is the # irq's for all ppc arch's (pmac/chrp/prep)
  * so it is the max of them all

include/asm-ppc/pgalloc.h

@@ -20,6 +20,7 @@ extern void pgd_free(pgd_t *pgd);
  */
 #define pmd_alloc_one(mm,address)       ({ BUG(); ((pmd_t *)2); })
 #define pmd_free(x)                     do { } while (0)
+#define pmd_free_tlb(tlb,x)		do { } while (0)
 #define pgd_populate(mm, pmd, pte)      BUG()
 
 #define pmd_populate_kernel(mm, pmd, pte)	\
@@ -32,6 +33,8 @@ extern struct page *pte_alloc_one(struct mm_struct *mm, unsigned long addr);
 extern void pte_free_kernel(pte_t *pte);
 extern void pte_free(struct page *pte);
 
+#define pte_free_tlb(tlb, pte)	pte_free((pte))
+
 #define check_pgt_cache()	do { } while (0)
 
 #endif /* _PPC_PGALLOC_H */

include/asm-ppc/pgtable.h

@@ -125,9 +125,9 @@ extern unsigned long ioremap_bot, ioremap_base;
  * (hardware-defined) PowerPC PTE as closely as possible.
  */
 
-#if defined(CONFIG_4xx)
+#if defined(CONFIG_40x)
 
-/* There are several potential gotchas here.  The 4xx hardware TLBLO
+/* There are several potential gotchas here.  The 40x hardware TLBLO
    field looks like this:
 
    0  1  2  3  4  ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31
@@ -135,7 +135,7 @@ extern unsigned long ioremap_bot, ioremap_base;
 
    Where possible we make the Linux PTE bits match up with this
 
-   - bits 20 and 21 must be cleared, because we use 4k pages (4xx can
+   - bits 20 and 21 must be cleared, because we use 4k pages (40x can
      support down to 1k pages), this is done in the TLBMiss exception
      handler.
    - We use only zones 0 (for kernel pages) and 1 (for user pages)
@@ -143,7 +143,7 @@ extern unsigned long ioremap_bot, ioremap_base;
      miss handler.  Bit 27 is PAGE_USER, thus selecting the correct
      zone.
    - PRESENT *must* be in the bottom two bits because swap cache
-     entries use the top 30 bits.  Because 4xx doesn't support SMP
+     entries use the top 30 bits.  Because 40x doesn't support SMP
      anyway, M is irrelevant so we borrow it for PAGE_PRESENT.  Bit 30
      is cleared in the TLB miss handler before the TLB entry is loaded.
    - All other bits of the PTE are loaded into TLBLO without
@@ -153,7 +153,7 @@ extern unsigned long ioremap_bot, ioremap_base;
      PRESENT.
 */
 
-/* Definitions for 4xx embedded chips. */
+/* Definitions for 40x embedded chips. */
 #define	_PAGE_GUARDED	0x001	/* G: page is guarded from prefetch */
 #define _PAGE_PRESENT	0x002	/* software: PTE contains a translation */
 #define	_PAGE_NO_CACHE	0x004	/* I: caching is inhibited */
@@ -451,7 +451,7 @@ static inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address)
 
 /* Find an entry in the third-level page table.. */
 #define __pte_offset(address)		\
-	((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
+	(((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
 #define pte_offset_kernel(dir, addr)	\
 	((pte_t *) pmd_page_kernel(*(dir)) + __pte_offset(addr))
 #define pte_offset_map(dir, addr)		\

include/asm-ppc/serial.h

@@ -33,7 +33,7 @@
 #include <platforms/spruce_serial.h>
 #elif defined(CONFIG_ZX4500)
 #include <platforms/zx4500_serial.h>
-#elif defined(CONFIG_4xx)
+#elif defined(CONFIG_40x)
 #include <asm/ibm4xx.h>
 #else
 

include/asm-ppc/spinlock.h

@@ -65,7 +65,7 @@ static inline void _raw_spin_unlock(spinlock_t *lock)
 	lock->lock = 0;
 }
 
-#define _raw_spin_trylock(lock) (!test_and_set_bit(0,(lock)))
+#define _raw_spin_trylock(l) (!test_and_set_bit(0,&(l)->lock))
 
 #else
 

include/asm-ppc/time.h

@@ -43,7 +43,7 @@ int via_calibrate_decr(void);
  */
 static __inline__ unsigned int get_dec(void)
 {
-#if defined(CONFIG_4xx)
+#if defined(CONFIG_40x)
 	return (mfspr(SPRN_PIT));
 #else
 	return (mfspr(SPRN_DEC));
@@ -52,7 +52,7 @@ static __inline__ unsigned int get_dec(void)
 
 static __inline__ void set_dec(unsigned int val)
 {
-#if defined(CONFIG_4xx)
+#if defined(CONFIG_40x)
 	return;		/* Have to let it auto-reload */
 #elif defined(CONFIG_8xx_CPU6)
 	set_dec_cpu6(val);