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Commit c42e2533 authored by David S. Miller's avatar David S. Miller
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Merge branch 'cxgb4-next' 

Hariprasad Shenai says:

====================
RDMA/cxgb4,cxgb4vf,cxgb4i,csiostor: Cleanup macros

This series moves the debugfs code to a new file debugfs.c and cleans up
macros/register defines.

Various patches have ended up changing the style of the symbolic macros/register
defines and some of them used the macros/register defines that matches the
output of the script from the hardware team.

As a result, the current kernel.org files are a mix of different macro styles.
Since this macro/register defines is used by five different drivers, a
few patch series have ended up adding duplicate macro/register define entries
with different styles. This makes these register define/macro files a complete
mess and we want to make them clean and consistent.

Will post few more series so that we can cover all the macros so that they all
follow the same style to be consistent.

The patches series is created against 'net-next' tree.
And includes patches on cxgb4, cxgb4vf, iw_cxgb4, csiostor and cxgb4i driver.

We have included all the maintainers of respective drivers. Kindly review the
change and let us know in case of any review comments.

V3: Use suffix instead of prefix for macros/register defines
V2: Changes the description and cover-letter content to answer David Miller's
question
====================
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 1a288172 e2ac9628
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Showing with 816 additions and 568 deletions
drivers/infiniband/hw/cxgb4/cm.c
View file @ c42e2533
...@@ -472,10 +472,10 @@ static void send_flowc(struct c4iw_ep *ep, struct sk_buff *skb) ...@@ -472,10 +472,10 @@ static void send_flowc(struct c4iw_ep *ep, struct sk_buff *skb)
skb = get_skb(skb, flowclen, GFP_KERNEL); skb = get_skb(skb, flowclen, GFP_KERNEL);
flowc = (struct fw_flowc_wr *)__skb_put(skb, flowclen); flowc = (struct fw_flowc_wr *)__skb_put(skb, flowclen);
flowc->op_to_nparams = cpu_to_be32(FW_WR_OP(FW_FLOWC_WR) | flowc->op_to_nparams = cpu_to_be32(FW_WR_OP_V(FW_FLOWC_WR) |
FW_FLOWC_WR_NPARAMS(8)); FW_FLOWC_WR_NPARAMS_V(8));
flowc->flowid_len16 = cpu_to_be32(FW_WR_LEN16(DIV_ROUND_UP(flowclen, flowc->flowid_len16 = cpu_to_be32(FW_WR_LEN16_V(DIV_ROUND_UP(flowclen,
16)) | FW_WR_FLOWID(ep->hwtid)); 16)) | FW_WR_FLOWID_V(ep->hwtid));
flowc->mnemval[0].mnemonic = FW_FLOWC_MNEM_PFNVFN; flowc->mnemval[0].mnemonic = FW_FLOWC_MNEM_PFNVFN;
flowc->mnemval[0].val = cpu_to_be32(FW_PFVF_CMD_PFN flowc->mnemval[0].val = cpu_to_be32(FW_PFVF_CMD_PFN
...@@ -803,16 +803,16 @@ static void send_mpa_req(struct c4iw_ep *ep, struct sk_buff *skb, ...@@ -803,16 +803,16 @@ static void send_mpa_req(struct c4iw_ep *ep, struct sk_buff *skb,
req = (struct fw_ofld_tx_data_wr *)skb_put(skb, wrlen); req = (struct fw_ofld_tx_data_wr *)skb_put(skb, wrlen);
memset(req, 0, wrlen); memset(req, 0, wrlen);
req->op_to_immdlen = cpu_to_be32( req->op_to_immdlen = cpu_to_be32(
FW_WR_OP(FW_OFLD_TX_DATA_WR) | FW_WR_OP_V(FW_OFLD_TX_DATA_WR) |
FW_WR_COMPL(1) | FW_WR_COMPL_F |
FW_WR_IMMDLEN(mpalen)); FW_WR_IMMDLEN_V(mpalen));
req->flowid_len16 = cpu_to_be32( req->flowid_len16 = cpu_to_be32(
FW_WR_FLOWID(ep->hwtid) | FW_WR_FLOWID_V(ep->hwtid) |
FW_WR_LEN16(wrlen >> 4)); FW_WR_LEN16_V(wrlen >> 4));
req->plen = cpu_to_be32(mpalen); req->plen = cpu_to_be32(mpalen);
req->tunnel_to_proxy = cpu_to_be32( req->tunnel_to_proxy = cpu_to_be32(
FW_OFLD_TX_DATA_WR_FLUSH(1) | FW_OFLD_TX_DATA_WR_FLUSH_F |
FW_OFLD_TX_DATA_WR_SHOVE(1)); FW_OFLD_TX_DATA_WR_SHOVE_F);
mpa = (struct mpa_message *)(req + 1); mpa = (struct mpa_message *)(req + 1);
memcpy(mpa->key, MPA_KEY_REQ, sizeof(mpa->key)); memcpy(mpa->key, MPA_KEY_REQ, sizeof(mpa->key));
...@@ -897,16 +897,16 @@ static int send_mpa_reject(struct c4iw_ep *ep, const void *pdata, u8 plen) ...@@ -897,16 +897,16 @@ static int send_mpa_reject(struct c4iw_ep *ep, const void *pdata, u8 plen)
req = (struct fw_ofld_tx_data_wr *)skb_put(skb, wrlen); req = (struct fw_ofld_tx_data_wr *)skb_put(skb, wrlen);
memset(req, 0, wrlen); memset(req, 0, wrlen);
req->op_to_immdlen = cpu_to_be32( req->op_to_immdlen = cpu_to_be32(
FW_WR_OP(FW_OFLD_TX_DATA_WR) | FW_WR_OP_V(FW_OFLD_TX_DATA_WR) |
FW_WR_COMPL(1) | FW_WR_COMPL_F |
FW_WR_IMMDLEN(mpalen)); FW_WR_IMMDLEN_V(mpalen));
req->flowid_len16 = cpu_to_be32( req->flowid_len16 = cpu_to_be32(
FW_WR_FLOWID(ep->hwtid) | FW_WR_FLOWID_V(ep->hwtid) |
FW_WR_LEN16(wrlen >> 4)); FW_WR_LEN16_V(wrlen >> 4));
req->plen = cpu_to_be32(mpalen); req->plen = cpu_to_be32(mpalen);
req->tunnel_to_proxy = cpu_to_be32( req->tunnel_to_proxy = cpu_to_be32(
FW_OFLD_TX_DATA_WR_FLUSH(1) | FW_OFLD_TX_DATA_WR_FLUSH_F |
FW_OFLD_TX_DATA_WR_SHOVE(1)); FW_OFLD_TX_DATA_WR_SHOVE_F);
mpa = (struct mpa_message *)(req + 1); mpa = (struct mpa_message *)(req + 1);
memset(mpa, 0, sizeof(*mpa)); memset(mpa, 0, sizeof(*mpa));
...@@ -977,16 +977,16 @@ static int send_mpa_reply(struct c4iw_ep *ep, const void *pdata, u8 plen) ...@@ -977,16 +977,16 @@ static int send_mpa_reply(struct c4iw_ep *ep, const void *pdata, u8 plen)
req = (struct fw_ofld_tx_data_wr *) skb_put(skb, wrlen); req = (struct fw_ofld_tx_data_wr *) skb_put(skb, wrlen);
memset(req, 0, wrlen); memset(req, 0, wrlen);
req->op_to_immdlen = cpu_to_be32( req->op_to_immdlen = cpu_to_be32(
FW_WR_OP(FW_OFLD_TX_DATA_WR) | FW_WR_OP_V(FW_OFLD_TX_DATA_WR) |
FW_WR_COMPL(1) | FW_WR_COMPL_F |
FW_WR_IMMDLEN(mpalen)); FW_WR_IMMDLEN_V(mpalen));
req->flowid_len16 = cpu_to_be32( req->flowid_len16 = cpu_to_be32(
FW_WR_FLOWID(ep->hwtid) | FW_WR_FLOWID_V(ep->hwtid) |
FW_WR_LEN16(wrlen >> 4)); FW_WR_LEN16_V(wrlen >> 4));
req->plen = cpu_to_be32(mpalen); req->plen = cpu_to_be32(mpalen);
req->tunnel_to_proxy = cpu_to_be32( req->tunnel_to_proxy = cpu_to_be32(
FW_OFLD_TX_DATA_WR_FLUSH(1) | FW_OFLD_TX_DATA_WR_FLUSH_F |
FW_OFLD_TX_DATA_WR_SHOVE(1)); FW_OFLD_TX_DATA_WR_SHOVE_F);
mpa = (struct mpa_message *)(req + 1); mpa = (struct mpa_message *)(req + 1);
memset(mpa, 0, sizeof(*mpa)); memset(mpa, 0, sizeof(*mpa));
...@@ -1751,7 +1751,7 @@ static void send_fw_act_open_req(struct c4iw_ep *ep, unsigned int atid) ...@@ -1751,7 +1751,7 @@ static void send_fw_act_open_req(struct c4iw_ep *ep, unsigned int atid)
req = (struct fw_ofld_connection_wr *)__skb_put(skb, sizeof(*req)); req = (struct fw_ofld_connection_wr *)__skb_put(skb, sizeof(*req));
memset(req, 0, sizeof(*req)); memset(req, 0, sizeof(*req));
req->op_compl = htonl(V_WR_OP(FW_OFLD_CONNECTION_WR)); req->op_compl = htonl(V_WR_OP(FW_OFLD_CONNECTION_WR));
req->len16_pkd = htonl(FW_WR_LEN16(DIV_ROUND_UP(sizeof(*req), 16))); req->len16_pkd = htonl(FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*req), 16)));
req->le.filter = cpu_to_be32(cxgb4_select_ntuple( req->le.filter = cpu_to_be32(cxgb4_select_ntuple(
ep->com.dev->rdev.lldi.ports[0], ep->com.dev->rdev.lldi.ports[0],
ep->l2t)); ep->l2t));
...@@ -3537,8 +3537,8 @@ static void send_fw_pass_open_req(struct c4iw_dev *dev, struct sk_buff *skb, ...@@ -3537,8 +3537,8 @@ static void send_fw_pass_open_req(struct c4iw_dev *dev, struct sk_buff *skb,
req_skb = alloc_skb(sizeof(struct fw_ofld_connection_wr), GFP_KERNEL); req_skb = alloc_skb(sizeof(struct fw_ofld_connection_wr), GFP_KERNEL);
req = (struct fw_ofld_connection_wr *)__skb_put(req_skb, sizeof(*req)); req = (struct fw_ofld_connection_wr *)__skb_put(req_skb, sizeof(*req));
memset(req, 0, sizeof(*req)); memset(req, 0, sizeof(*req));
req->op_compl = htonl(V_WR_OP(FW_OFLD_CONNECTION_WR) | FW_WR_COMPL(1)); req->op_compl = htonl(V_WR_OP(FW_OFLD_CONNECTION_WR) | FW_WR_COMPL_F);
req->len16_pkd = htonl(FW_WR_LEN16(DIV_ROUND_UP(sizeof(*req), 16))); req->len16_pkd = htonl(FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*req), 16)));
req->le.version_cpl = htonl(F_FW_OFLD_CONNECTION_WR_CPL); req->le.version_cpl = htonl(F_FW_OFLD_CONNECTION_WR_CPL);
req->le.filter = (__force __be32) filter; req->le.filter = (__force __be32) filter;
req->le.lport = lport; req->le.lport = lport;
......
drivers/infiniband/hw/cxgb4/cq.c
View file @ c42e2533
...@@ -51,9 +51,9 @@ static int destroy_cq(struct c4iw_rdev *rdev, struct t4_cq *cq, ...@@ -51,9 +51,9 @@ static int destroy_cq(struct c4iw_rdev *rdev, struct t4_cq *cq,
res_wr = (struct fw_ri_res_wr *)__skb_put(skb, wr_len); res_wr = (struct fw_ri_res_wr *)__skb_put(skb, wr_len);
memset(res_wr, 0, wr_len); memset(res_wr, 0, wr_len);
res_wr->op_nres = cpu_to_be32( res_wr->op_nres = cpu_to_be32(
FW_WR_OP(FW_RI_RES_WR) | FW_WR_OP_V(FW_RI_RES_WR) |
V_FW_RI_RES_WR_NRES(1) | V_FW_RI_RES_WR_NRES(1) |
FW_WR_COMPL(1)); FW_WR_COMPL_F);
res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16)); res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
res_wr->cookie = (unsigned long) &wr_wait; res_wr->cookie = (unsigned long) &wr_wait;
res = res_wr->res; res = res_wr->res;
...@@ -121,9 +121,9 @@ static int create_cq(struct c4iw_rdev *rdev, struct t4_cq *cq, ...@@ -121,9 +121,9 @@ static int create_cq(struct c4iw_rdev *rdev, struct t4_cq *cq,
res_wr = (struct fw_ri_res_wr *)__skb_put(skb, wr_len); res_wr = (struct fw_ri_res_wr *)__skb_put(skb, wr_len);
memset(res_wr, 0, wr_len); memset(res_wr, 0, wr_len);
res_wr->op_nres = cpu_to_be32( res_wr->op_nres = cpu_to_be32(
FW_WR_OP(FW_RI_RES_WR) | FW_WR_OP_V(FW_RI_RES_WR) |
V_FW_RI_RES_WR_NRES(1) | V_FW_RI_RES_WR_NRES(1) |
FW_WR_COMPL(1)); FW_WR_COMPL_F);
res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16)); res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
res_wr->cookie = (unsigned long) &wr_wait; res_wr->cookie = (unsigned long) &wr_wait;
res = res_wr->res; res = res_wr->res;
......
drivers/infiniband/hw/cxgb4/mem.c
View file @ c42e2533
...@@ -74,10 +74,10 @@ static int _c4iw_write_mem_dma_aligned(struct c4iw_rdev *rdev, u32 addr, ...@@ -74,10 +74,10 @@ static int _c4iw_write_mem_dma_aligned(struct c4iw_rdev *rdev, u32 addr,
req = (struct ulp_mem_io *)__skb_put(skb, wr_len); req = (struct ulp_mem_io *)__skb_put(skb, wr_len);
memset(req, 0, wr_len); memset(req, 0, wr_len);
INIT_ULPTX_WR(req, wr_len, 0, 0); INIT_ULPTX_WR(req, wr_len, 0, 0);
req->wr.wr_hi = cpu_to_be32(FW_WR_OP(FW_ULPTX_WR) | req->wr.wr_hi = cpu_to_be32(FW_WR_OP_V(FW_ULPTX_WR) |
(wait ? FW_WR_COMPL(1) : 0)); (wait ? FW_WR_COMPL_F : 0));
req->wr.wr_lo = wait ? (__force __be64)(unsigned long) &wr_wait : 0L; req->wr.wr_lo = wait ? (__force __be64)(unsigned long) &wr_wait : 0L;
req->wr.wr_mid = cpu_to_be32(FW_WR_LEN16(DIV_ROUND_UP(wr_len, 16))); req->wr.wr_mid = cpu_to_be32(FW_WR_LEN16_V(DIV_ROUND_UP(wr_len, 16)));
req->cmd = cpu_to_be32(ULPTX_CMD(ULP_TX_MEM_WRITE)); req->cmd = cpu_to_be32(ULPTX_CMD(ULP_TX_MEM_WRITE));
req->cmd |= cpu_to_be32(V_T5_ULP_MEMIO_ORDER(1)); req->cmd |= cpu_to_be32(V_T5_ULP_MEMIO_ORDER(1));
req->dlen = cpu_to_be32(ULP_MEMIO_DATA_LEN(len>>5)); req->dlen = cpu_to_be32(ULP_MEMIO_DATA_LEN(len>>5));
...@@ -135,13 +135,13 @@ static int _c4iw_write_mem_inline(struct c4iw_rdev *rdev, u32 addr, u32 len, ...@@ -135,13 +135,13 @@ static int _c4iw_write_mem_inline(struct c4iw_rdev *rdev, u32 addr, u32 len,
INIT_ULPTX_WR(req, wr_len, 0, 0); INIT_ULPTX_WR(req, wr_len, 0, 0);
if (i == (num_wqe-1)) { if (i == (num_wqe-1)) {
req->wr.wr_hi = cpu_to_be32(FW_WR_OP(FW_ULPTX_WR) | req->wr.wr_hi = cpu_to_be32(FW_WR_OP_V(FW_ULPTX_WR) |
FW_WR_COMPL(1)); FW_WR_COMPL_F);
req->wr.wr_lo = (__force __be64)(unsigned long) &wr_wait; req->wr.wr_lo = (__force __be64)(unsigned long) &wr_wait;
} else } else
req->wr.wr_hi = cpu_to_be32(FW_WR_OP(FW_ULPTX_WR)); req->wr.wr_hi = cpu_to_be32(FW_WR_OP_V(FW_ULPTX_WR));
req->wr.wr_mid = cpu_to_be32( req->wr.wr_mid = cpu_to_be32(
FW_WR_LEN16(DIV_ROUND_UP(wr_len, 16))); FW_WR_LEN16_V(DIV_ROUND_UP(wr_len, 16)));
req->cmd = cmd; req->cmd = cmd;
req->dlen = cpu_to_be32(ULP_MEMIO_DATA_LEN( req->dlen = cpu_to_be32(ULP_MEMIO_DATA_LEN(
......
drivers/infiniband/hw/cxgb4/qp.c
View file @ c42e2533
...@@ -271,9 +271,9 @@ static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq, ...@@ -271,9 +271,9 @@ static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
res_wr = (struct fw_ri_res_wr *)__skb_put(skb, wr_len); res_wr = (struct fw_ri_res_wr *)__skb_put(skb, wr_len);
memset(res_wr, 0, wr_len); memset(res_wr, 0, wr_len);
res_wr->op_nres = cpu_to_be32( res_wr->op_nres = cpu_to_be32(
FW_WR_OP(FW_RI_RES_WR) | FW_WR_OP_V(FW_RI_RES_WR) |
V_FW_RI_RES_WR_NRES(2) | V_FW_RI_RES_WR_NRES(2) |
FW_WR_COMPL(1)); FW_WR_COMPL_F);
res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16)); res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
res_wr->cookie = (unsigned long) &wr_wait; res_wr->cookie = (unsigned long) &wr_wait;
res = res_wr->res; res = res_wr->res;
...@@ -1082,10 +1082,10 @@ static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe, ...@@ -1082,10 +1082,10 @@ static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe,
wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe)); wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
memset(wqe, 0, sizeof *wqe); memset(wqe, 0, sizeof *wqe);
wqe->op_compl = cpu_to_be32(FW_WR_OP(FW_RI_INIT_WR)); wqe->op_compl = cpu_to_be32(FW_WR_OP_V(FW_RI_INIT_WR));
wqe->flowid_len16 = cpu_to_be32( wqe->flowid_len16 = cpu_to_be32(
FW_WR_FLOWID(qhp->ep->hwtid) | FW_WR_FLOWID_V(qhp->ep->hwtid) |
FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16))); FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe), 16)));
wqe->u.terminate.type = FW_RI_TYPE_TERMINATE; wqe->u.terminate.type = FW_RI_TYPE_TERMINATE;
wqe->u.terminate.immdlen = cpu_to_be32(sizeof *term); wqe->u.terminate.immdlen = cpu_to_be32(sizeof *term);
...@@ -1204,11 +1204,11 @@ static int rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp, ...@@ -1204,11 +1204,11 @@ static int rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe)); wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
memset(wqe, 0, sizeof *wqe); memset(wqe, 0, sizeof *wqe);
wqe->op_compl = cpu_to_be32( wqe->op_compl = cpu_to_be32(
FW_WR_OP(FW_RI_INIT_WR) | FW_WR_OP_V(FW_RI_INIT_WR) |
FW_WR_COMPL(1)); FW_WR_COMPL_F);
wqe->flowid_len16 = cpu_to_be32( wqe->flowid_len16 = cpu_to_be32(
FW_WR_FLOWID(ep->hwtid) | FW_WR_FLOWID_V(ep->hwtid) |
FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16))); FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe), 16)));
wqe->cookie = (unsigned long) &ep->com.wr_wait; wqe->cookie = (unsigned long) &ep->com.wr_wait;
wqe->u.fini.type = FW_RI_TYPE_FINI; wqe->u.fini.type = FW_RI_TYPE_FINI;
...@@ -1273,11 +1273,11 @@ static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp) ...@@ -1273,11 +1273,11 @@ static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp)
wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe)); wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
memset(wqe, 0, sizeof *wqe); memset(wqe, 0, sizeof *wqe);
wqe->op_compl = cpu_to_be32( wqe->op_compl = cpu_to_be32(
FW_WR_OP(FW_RI_INIT_WR) | FW_WR_OP_V(FW_RI_INIT_WR) |
FW_WR_COMPL(1)); FW_WR_COMPL_F);
wqe->flowid_len16 = cpu_to_be32( wqe->flowid_len16 = cpu_to_be32(
FW_WR_FLOWID(qhp->ep->hwtid) | FW_WR_FLOWID_V(qhp->ep->hwtid) |
FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16))); FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe), 16)));
wqe->cookie = (unsigned long) &qhp->ep->com.wr_wait; wqe->cookie = (unsigned long) &qhp->ep->com.wr_wait;
......
drivers/net/ethernet/chelsio/cxgb4/Makefile
View file @ c42e2533
...@@ -6,3 +6,4 @@ obj-$(CONFIG_CHELSIO_T4) += cxgb4.o ...@@ -6,3 +6,4 @@ obj-$(CONFIG_CHELSIO_T4) += cxgb4.o
cxgb4-objs := cxgb4_main.o l2t.o t4_hw.o sge.o cxgb4-objs := cxgb4_main.o l2t.o t4_hw.o sge.o
cxgb4-$(CONFIG_CHELSIO_T4_DCB) += cxgb4_dcb.o cxgb4-$(CONFIG_CHELSIO_T4_DCB) += cxgb4_dcb.o
cxgb4-$(CONFIG_DEBUG_FS) += cxgb4_debugfs.o
drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
View file @ c42e2533
...@@ -354,7 +354,7 @@ struct link_config { ...@@ -354,7 +354,7 @@ struct link_config {
unsigned char link_ok; /* link up? */ unsigned char link_ok; /* link up? */
}; };
#define FW_LEN16(fw_struct) FW_CMD_LEN16(sizeof(fw_struct) / 16) #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
enum { enum {
MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */ MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */
...@@ -1085,4 +1085,5 @@ void t4_db_dropped(struct adapter *adapter); ...@@ -1085,4 +1085,5 @@ void t4_db_dropped(struct adapter *adapter);
int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
u32 addr, u32 val); u32 addr, u32 val);
void t4_sge_decode_idma_state(struct adapter *adapter, int state); void t4_sge_decode_idma_state(struct adapter *adapter, int state);
void t4_free_mem(void *addr);
#endif /* __CXGB4_H__ */ #endif /* __CXGB4_H__ */
drivers/net/ethernet/chelsio/cxgb4/cxgb4_dcb.h
View file @ c42e2533
...@@ -42,9 +42,9 @@ ...@@ -42,9 +42,9 @@
do { \ do { \
memset(&(__pcmd), 0, sizeof(__pcmd)); \ memset(&(__pcmd), 0, sizeof(__pcmd)); \
(__pcmd).op_to_portid = \ (__pcmd).op_to_portid = \
cpu_to_be32(FW_CMD_OP(FW_PORT_CMD) | \ cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) | \
FW_CMD_REQUEST | \ FW_CMD_REQUEST_F | \
FW_CMD_##__op | \ FW_CMD_##__op##_F | \
FW_PORT_CMD_PORTID(__port)); \ FW_PORT_CMD_PORTID(__port)); \
(__pcmd).action_to_len16 = \ (__pcmd).action_to_len16 = \
cpu_to_be32(FW_PORT_CMD_ACTION(__action) | \ cpu_to_be32(FW_PORT_CMD_ACTION(__action) | \
......
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c 0 → 100644
View file @ c42e2533
/*
* This file is part of the Chelsio T4 Ethernet driver for Linux.
*
* Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the
* OpenIB.org BSD license below:
*
* Redistribution and use in source and binary forms, with or
* without modification, are permitted provided that the following
* conditions are met:
*
* - Redistributions of source code must retain the above
* copyright notice, this list of conditions and the following
* disclaimer.
*
* - Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#include <linux/seq_file.h>
#include <linux/debugfs.h>
#include <linux/string_helpers.h>
#include <linux/sort.h>
#include "cxgb4.h"
#include "t4_regs.h"
#include "t4fw_api.h"
#include "cxgb4_debugfs.h"
#include "l2t.h"
static ssize_t mem_read(struct file *file, char __user *buf, size_t count,
loff_t *ppos)
{
loff_t pos = *ppos;
loff_t avail = file_inode(file)->i_size;
unsigned int mem = (uintptr_t)file->private_data & 3;
struct adapter *adap = file->private_data - mem;
__be32 *data;
int ret;
if (pos < 0)
return -EINVAL;
if (pos >= avail)
return 0;
if (count > avail - pos)
count = avail - pos;
data = t4_alloc_mem(count);
if (!data)
return -ENOMEM;
spin_lock(&adap->win0_lock);
ret = t4_memory_rw(adap, 0, mem, pos, count, data, T4_MEMORY_READ);
spin_unlock(&adap->win0_lock);
if (ret) {
t4_free_mem(data);
return ret;
}
ret = copy_to_user(buf, data, count);
t4_free_mem(data);
if (ret)
return -EFAULT;
*ppos = pos + count;
return count;
}
static const struct file_operations mem_debugfs_fops = {
.owner = THIS_MODULE,
.open = simple_open,
.read = mem_read,
.llseek = default_llseek,
};
static void add_debugfs_mem(struct adapter *adap, const char *name,
unsigned int idx, unsigned int size_mb)
{
struct dentry *de;
de = debugfs_create_file(name, S_IRUSR, adap->debugfs_root,
(void *)adap + idx, &mem_debugfs_fops);
if (de && de->d_inode)
de->d_inode->i_size = size_mb << 20;
}
/* Add an array of Debug FS files.
*/
void add_debugfs_files(struct adapter *adap,
struct t4_debugfs_entry *files,
unsigned int nfiles)
{
int i;
/* debugfs support is best effort */
for (i = 0; i < nfiles; i++)
debugfs_create_file(files[i].name, files[i].mode,
adap->debugfs_root,
(void *)adap + files[i].data,
files[i].ops);
}
int t4_setup_debugfs(struct adapter *adap)
{
int i;
u32 size;
static struct t4_debugfs_entry t4_debugfs_files[] = {
{ "l2t", &t4_l2t_fops, S_IRUSR, 0},
};
add_debugfs_files(adap,
t4_debugfs_files,
ARRAY_SIZE(t4_debugfs_files));
i = t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A);
if (i & EDRAM0_ENABLE_F) {
size = t4_read_reg(adap, MA_EDRAM0_BAR_A);
add_debugfs_mem(adap, "edc0", MEM_EDC0, EDRAM0_SIZE_G(size));
}
if (i & EDRAM1_ENABLE_F) {
size = t4_read_reg(adap, MA_EDRAM1_BAR_A);
add_debugfs_mem(adap, "edc1", MEM_EDC1, EDRAM1_SIZE_G(size));
}
if (is_t4(adap->params.chip)) {
size = t4_read_reg(adap, MA_EXT_MEMORY_BAR_A);
if (i & EXT_MEM_ENABLE_F)
add_debugfs_mem(adap, "mc", MEM_MC,
EXT_MEM_SIZE_G(size));
} else {
if (i & EXT_MEM0_ENABLE_F) {
size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A);
add_debugfs_mem(adap, "mc0", MEM_MC0,
EXT_MEM0_SIZE_G(size));
}
if (i & EXT_MEM1_ENABLE_F) {
size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
add_debugfs_mem(adap, "mc1", MEM_MC1,
EXT_MEM1_SIZE_G(size));
}
}
return 0;
}
drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.h 0 → 100644
View file @ c42e2533
/*
* This file is part of the Chelsio T4 Ethernet driver for Linux.
*
* Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the
* OpenIB.org BSD license below:
*
* Redistribution and use in source and binary forms, with or
* without modification, are permitted provided that the following
* conditions are met:
*
* - Redistributions of source code must retain the above
* copyright notice, this list of conditions and the following
* disclaimer.
*
* - Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef __CXGB4_DEBUGFS_H
#define __CXGB4_DEBUGFS_H
#include <linux/export.h>
struct t4_debugfs_entry {
const char *name;
const struct file_operations *ops;
mode_t mode;
unsigned char data;
};
int t4_setup_debugfs(struct adapter *adap);
void add_debugfs_files(struct adapter *adap,
struct t4_debugfs_entry *files,
unsigned int nfiles);
#endif
drivers/net/ethernet/chelsio/cxgb4/cxgb4_uld.h
View file @ c42e2533
...@@ -52,10 +52,10 @@ enum { ...@@ -52,10 +52,10 @@ enum {
}; };
#define INIT_TP_WR(w, tid) do { \ #define INIT_TP_WR(w, tid) do { \
(w)->wr.wr_hi = htonl(FW_WR_OP(FW_TP_WR) | \ (w)->wr.wr_hi = htonl(FW_WR_OP_V(FW_TP_WR) | \
FW_WR_IMMDLEN(sizeof(*w) - sizeof(w->wr))); \ FW_WR_IMMDLEN_V(sizeof(*w) - sizeof(w->wr))); \
(w)->wr.wr_mid = htonl(FW_WR_LEN16(DIV_ROUND_UP(sizeof(*w), 16)) | \ (w)->wr.wr_mid = htonl(FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*w), 16)) | \
FW_WR_FLOWID(tid)); \ FW_WR_FLOWID_V(tid)); \
(w)->wr.wr_lo = cpu_to_be64(0); \ (w)->wr.wr_lo = cpu_to_be64(0); \
} while (0) } while (0)
...@@ -65,9 +65,10 @@ enum { ...@@ -65,9 +65,10 @@ enum {
} while (0) } while (0)
#define INIT_ULPTX_WR(w, wrlen, atomic, tid) do { \ #define INIT_ULPTX_WR(w, wrlen, atomic, tid) do { \
(w)->wr.wr_hi = htonl(FW_WR_OP(FW_ULPTX_WR) | FW_WR_ATOMIC(atomic)); \ (w)->wr.wr_hi = htonl(FW_WR_OP_V(FW_ULPTX_WR) | \
(w)->wr.wr_mid = htonl(FW_WR_LEN16(DIV_ROUND_UP(wrlen, 16)) | \ FW_WR_ATOMIC_V(atomic)); \
FW_WR_FLOWID(tid)); \ (w)->wr.wr_mid = htonl(FW_WR_LEN16_V(DIV_ROUND_UP(wrlen, 16)) | \
FW_WR_FLOWID_V(tid)); \
(w)->wr.wr_lo = cpu_to_be64(0); \ (w)->wr.wr_lo = cpu_to_be64(0); \
} while (0) } while (0)
......
drivers/net/ethernet/chelsio/cxgb4/sge.c
View file @ c42e2533
...@@ -1092,10 +1092,10 @@ out_free: dev_kfree_skb_any(skb); ...@@ -1092,10 +1092,10 @@ out_free: dev_kfree_skb_any(skb);
goto out_free; goto out_free;
} }
wr_mid = FW_WR_LEN16(DIV_ROUND_UP(flits, 2)); wr_mid = FW_WR_LEN16_V(DIV_ROUND_UP(flits, 2));
if (unlikely(credits < ETHTXQ_STOP_THRES)) { if (unlikely(credits < ETHTXQ_STOP_THRES)) {
eth_txq_stop(q); eth_txq_stop(q);
wr_mid |= FW_WR_EQUEQ | FW_WR_EQUIQ; wr_mid |= FW_WR_EQUEQ_F | FW_WR_EQUIQ_F;
} }
wr = (void *)&q->q.desc[q->q.pidx]; wr = (void *)&q->q.desc[q->q.pidx];
...@@ -1112,8 +1112,8 @@ out_free: dev_kfree_skb_any(skb); ...@@ -1112,8 +1112,8 @@ out_free: dev_kfree_skb_any(skb);
int eth_xtra_len = skb_network_offset(skb) - ETH_HLEN; int eth_xtra_len = skb_network_offset(skb) - ETH_HLEN;
len += sizeof(*lso); len += sizeof(*lso);
wr->op_immdlen = htonl(FW_WR_OP(FW_ETH_TX_PKT_WR) | wr->op_immdlen = htonl(FW_WR_OP_V(FW_ETH_TX_PKT_WR) |
FW_WR_IMMDLEN(len)); FW_WR_IMMDLEN_V(len));
lso->c.lso_ctrl = htonl(LSO_OPCODE(CPL_TX_PKT_LSO) | lso->c.lso_ctrl = htonl(LSO_OPCODE(CPL_TX_PKT_LSO) |
LSO_FIRST_SLICE | LSO_LAST_SLICE | LSO_FIRST_SLICE | LSO_LAST_SLICE |
LSO_IPV6(v6) | LSO_IPV6(v6) |
...@@ -1135,8 +1135,8 @@ out_free: dev_kfree_skb_any(skb); ...@@ -1135,8 +1135,8 @@ out_free: dev_kfree_skb_any(skb);
q->tx_cso += ssi->gso_segs; q->tx_cso += ssi->gso_segs;
} else { } else {
len += sizeof(*cpl); len += sizeof(*cpl);
wr->op_immdlen = htonl(FW_WR_OP(FW_ETH_TX_PKT_WR) | wr->op_immdlen = htonl(FW_WR_OP_V(FW_ETH_TX_PKT_WR) |
FW_WR_IMMDLEN(len)); FW_WR_IMMDLEN_V(len));
cpl = (void *)(wr + 1); cpl = (void *)(wr + 1);
if (skb->ip_summed == CHECKSUM_PARTIAL) { if (skb->ip_summed == CHECKSUM_PARTIAL) {
cntrl = hwcsum(skb) | TXPKT_IPCSUM_DIS; cntrl = hwcsum(skb) | TXPKT_IPCSUM_DIS;
...@@ -1224,7 +1224,7 @@ static void ctrlq_check_stop(struct sge_ctrl_txq *q, struct fw_wr_hdr *wr) ...@@ -1224,7 +1224,7 @@ static void ctrlq_check_stop(struct sge_ctrl_txq *q, struct fw_wr_hdr *wr)
{ {
reclaim_completed_tx_imm(&q->q); reclaim_completed_tx_imm(&q->q);
if (unlikely(txq_avail(&q->q) < TXQ_STOP_THRES)) { if (unlikely(txq_avail(&q->q) < TXQ_STOP_THRES)) {
wr->lo |= htonl(FW_WR_EQUEQ | FW_WR_EQUIQ); wr->lo |= htonl(FW_WR_EQUEQ_F | FW_WR_EQUIQ_F);
q->q.stops++; q->q.stops++;
q->full = 1; q->full = 1;
} }
...@@ -1406,7 +1406,7 @@ static void ofldtxq_stop(struct sge_ofld_txq *q, struct sk_buff *skb) ...@@ -1406,7 +1406,7 @@ static void ofldtxq_stop(struct sge_ofld_txq *q, struct sk_buff *skb)
{ {
struct fw_wr_hdr *wr = (struct fw_wr_hdr *)skb->data; struct fw_wr_hdr *wr = (struct fw_wr_hdr *)skb->data;
wr->lo |= htonl(FW_WR_EQUEQ | FW_WR_EQUIQ); wr->lo |= htonl(FW_WR_EQUEQ_F | FW_WR_EQUIQ_F);
q->q.stops++; q->q.stops++;
q->full = 1; q->full = 1;
} }
...@@ -2297,8 +2297,8 @@ int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq, ...@@ -2297,8 +2297,8 @@ int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
return -ENOMEM; return -ENOMEM;
memset(&c, 0, sizeof(c)); memset(&c, 0, sizeof(c));
c.op_to_vfn = htonl(FW_CMD_OP(FW_IQ_CMD) | FW_CMD_REQUEST | c.op_to_vfn = htonl(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
FW_CMD_WRITE | FW_CMD_EXEC | FW_CMD_WRITE_F | FW_CMD_EXEC_F |
FW_IQ_CMD_PFN(adap->fn) | FW_IQ_CMD_VFN(0)); FW_IQ_CMD_PFN(adap->fn) | FW_IQ_CMD_VFN(0));
c.alloc_to_len16 = htonl(FW_IQ_CMD_ALLOC | FW_IQ_CMD_IQSTART(1) | c.alloc_to_len16 = htonl(FW_IQ_CMD_ALLOC | FW_IQ_CMD_IQSTART(1) |
FW_LEN16(c)); FW_LEN16(c));
...@@ -2423,8 +2423,8 @@ int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq, ...@@ -2423,8 +2423,8 @@ int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
return -ENOMEM; return -ENOMEM;
memset(&c, 0, sizeof(c)); memset(&c, 0, sizeof(c));
c.op_to_vfn = htonl(FW_CMD_OP(FW_EQ_ETH_CMD) | FW_CMD_REQUEST | c.op_to_vfn = htonl(FW_CMD_OP_V(FW_EQ_ETH_CMD) | FW_CMD_REQUEST_F |
FW_CMD_WRITE | FW_CMD_EXEC | FW_CMD_WRITE_F | FW_CMD_EXEC_F |
FW_EQ_ETH_CMD_PFN(adap->fn) | FW_EQ_ETH_CMD_VFN(0)); FW_EQ_ETH_CMD_PFN(adap->fn) | FW_EQ_ETH_CMD_VFN(0));
c.alloc_to_len16 = htonl(FW_EQ_ETH_CMD_ALLOC | c.alloc_to_len16 = htonl(FW_EQ_ETH_CMD_ALLOC |
FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c)); FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c));
...@@ -2476,8 +2476,8 @@ int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq, ...@@ -2476,8 +2476,8 @@ int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
if (!txq->q.desc) if (!txq->q.desc)
return -ENOMEM; return -ENOMEM;
c.op_to_vfn = htonl(FW_CMD_OP(FW_EQ_CTRL_CMD) | FW_CMD_REQUEST | c.op_to_vfn = htonl(FW_CMD_OP_V(FW_EQ_CTRL_CMD) | FW_CMD_REQUEST_F |
FW_CMD_WRITE | FW_CMD_EXEC | FW_CMD_WRITE_F | FW_CMD_EXEC_F |
FW_EQ_CTRL_CMD_PFN(adap->fn) | FW_EQ_CTRL_CMD_PFN(adap->fn) |
FW_EQ_CTRL_CMD_VFN(0)); FW_EQ_CTRL_CMD_VFN(0));
c.alloc_to_len16 = htonl(FW_EQ_CTRL_CMD_ALLOC | c.alloc_to_len16 = htonl(FW_EQ_CTRL_CMD_ALLOC |
...@@ -2530,8 +2530,8 @@ int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq, ...@@ -2530,8 +2530,8 @@ int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq,
return -ENOMEM; return -ENOMEM;
memset(&c, 0, sizeof(c)); memset(&c, 0, sizeof(c));
c.op_to_vfn = htonl(FW_CMD_OP(FW_EQ_OFLD_CMD) | FW_CMD_REQUEST | c.op_to_vfn = htonl(FW_CMD_OP_V(FW_EQ_OFLD_CMD) | FW_CMD_REQUEST_F |
FW_CMD_WRITE | FW_CMD_EXEC | FW_CMD_WRITE_F | FW_CMD_EXEC_F |
FW_EQ_OFLD_CMD_PFN(adap->fn) | FW_EQ_OFLD_CMD_PFN(adap->fn) |
FW_EQ_OFLD_CMD_VFN(0)); FW_EQ_OFLD_CMD_VFN(0));
c.alloc_to_len16 = htonl(FW_EQ_OFLD_CMD_ALLOC | c.alloc_to_len16 = htonl(FW_EQ_OFLD_CMD_ALLOC |
......
drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
View file @ c42e2533
This diff is collapsed.
drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
View file @ c42e2533
...@@ -501,21 +501,62 @@ ...@@ -501,21 +501,62 @@
#define MC_BIST_STATUS_RDATA 0x7688 #define MC_BIST_STATUS_RDATA 0x7688
#define MA_EDRAM0_BAR 0x77c0 #define MA_EDRAM0_BAR_A 0x77c0
#define MA_EDRAM1_BAR 0x77c4
#define EDRAM_SIZE_MASK 0xfffU #define EDRAM0_SIZE_S 0
#define EDRAM_SIZE_GET(x) ((x) & EDRAM_SIZE_MASK) #define EDRAM0_SIZE_M 0xfffU
#define EDRAM0_SIZE_V(x) ((x) << EDRAM0_SIZE_S)
#define MA_EXT_MEMORY_BAR 0x77c8 #define EDRAM0_SIZE_G(x) (((x) >> EDRAM0_SIZE_S) & EDRAM0_SIZE_M)
#define EXT_MEM_SIZE_MASK 0x00000fffU
#define EXT_MEM_SIZE_SHIFT 0 #define MA_EDRAM1_BAR_A 0x77c4
#define EXT_MEM_SIZE_GET(x) (((x) & EXT_MEM_SIZE_MASK) >> EXT_MEM_SIZE_SHIFT)
#define EDRAM1_SIZE_S 0
#define MA_TARGET_MEM_ENABLE 0x77d8 #define EDRAM1_SIZE_M 0xfffU
#define EXT_MEM1_ENABLE 0x00000010U #define EDRAM1_SIZE_V(x) ((x) << EDRAM1_SIZE_S)
#define EXT_MEM_ENABLE 0x00000004U #define EDRAM1_SIZE_G(x) (((x) >> EDRAM1_SIZE_S) & EDRAM1_SIZE_M)
#define EDRAM1_ENABLE 0x00000002U
#define EDRAM0_ENABLE 0x00000001U #define MA_EXT_MEMORY_BAR_A 0x77c8
#define EXT_MEM_SIZE_S 0
#define EXT_MEM_SIZE_M 0xfffU
#define EXT_MEM_SIZE_V(x) ((x) << EXT_MEM_SIZE_S)
#define EXT_MEM_SIZE_G(x) (((x) >> EXT_MEM_SIZE_S) & EXT_MEM_SIZE_M)
#define MA_EXT_MEMORY1_BAR_A 0x7808
#define EXT_MEM1_SIZE_S 0
#define EXT_MEM1_SIZE_M 0xfffU
#define EXT_MEM1_SIZE_V(x) ((x) << EXT_MEM1_SIZE_S)
#define EXT_MEM1_SIZE_G(x) (((x) >> EXT_MEM1_SIZE_S) & EXT_MEM1_SIZE_M)
#define MA_EXT_MEMORY0_BAR_A 0x77c8
#define EXT_MEM0_SIZE_S 0
#define EXT_MEM0_SIZE_M 0xfffU
#define EXT_MEM0_SIZE_V(x) ((x) << EXT_MEM0_SIZE_S)
#define EXT_MEM0_SIZE_G(x) (((x) >> EXT_MEM0_SIZE_S) & EXT_MEM0_SIZE_M)
#define MA_TARGET_MEM_ENABLE_A 0x77d8
#define EXT_MEM_ENABLE_S 2
#define EXT_MEM_ENABLE_V(x) ((x) << EXT_MEM_ENABLE_S)
#define EXT_MEM_ENABLE_F EXT_MEM_ENABLE_V(1U)
#define EDRAM1_ENABLE_S 1
#define EDRAM1_ENABLE_V(x) ((x) << EDRAM1_ENABLE_S)
#define EDRAM1_ENABLE_F EDRAM1_ENABLE_V(1U)
#define EDRAM0_ENABLE_S 0
#define EDRAM0_ENABLE_V(x) ((x) << EDRAM0_ENABLE_S)
#define EDRAM0_ENABLE_F EDRAM0_ENABLE_V(1U)
#define EXT_MEM1_ENABLE_S 4
#define EXT_MEM1_ENABLE_V(x) ((x) << EXT_MEM1_ENABLE_S)
#define EXT_MEM1_ENABLE_F EXT_MEM1_ENABLE_V(1U)
#define EXT_MEM0_ENABLE_S 2
#define EXT_MEM0_ENABLE_V(x) ((x) << EXT_MEM0_ENABLE_S)
#define EXT_MEM0_ENABLE_F EXT_MEM0_ENABLE_V(1U)
#define MA_INT_CAUSE 0x77e0 #define MA_INT_CAUSE 0x77e0
#define MEM_PERR_INT_CAUSE 0x00000002U #define MEM_PERR_INT_CAUSE 0x00000002U
...@@ -532,7 +573,6 @@ ...@@ -532,7 +573,6 @@
#define MA_PARITY_ERROR_STATUS 0x77f4 #define MA_PARITY_ERROR_STATUS 0x77f4
#define MA_PARITY_ERROR_STATUS2 0x7804 #define MA_PARITY_ERROR_STATUS2 0x7804
#define MA_EXT_MEMORY1_BAR 0x7808
#define EDC_0_BASE_ADDR 0x7900 #define EDC_0_BASE_ADDR 0x7900
#define EDC_BIST_CMD 0x7904 #define EDC_BIST_CMD 0x7904
......
drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h
View file @ c42e2533
...@@ -109,18 +109,49 @@ struct fw_wr_hdr { ...@@ -109,18 +109,49 @@ struct fw_wr_hdr {
__be32 lo; __be32 lo;
}; };
#define FW_WR_OP(x) ((x) << 24) /* work request opcode (hi) */
#define FW_WR_OP_GET(x) (((x) >> 24) & 0xff) #define FW_WR_OP_S 24
#define FW_WR_ATOMIC(x) ((x) << 23) #define FW_WR_OP_M 0xff
#define FW_WR_FLUSH(x) ((x) << 22) #define FW_WR_OP_V(x) ((x) << FW_WR_OP_S)
#define FW_WR_COMPL(x) ((x) << 21) #define FW_WR_OP_G(x) (((x) >> FW_WR_OP_S) & FW_WR_OP_M)
#define FW_WR_IMMDLEN_MASK 0xff
#define FW_WR_IMMDLEN(x) ((x) << 0) /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER */
#define FW_WR_ATOMIC_S 23
#define FW_WR_EQUIQ (1U << 31) #define FW_WR_ATOMIC_V(x) ((x) << FW_WR_ATOMIC_S)
#define FW_WR_EQUEQ (1U << 30)
#define FW_WR_FLOWID(x) ((x) << 8) /* flush flag (hi) - firmware flushes flushable work request buffered
#define FW_WR_LEN16(x) ((x) << 0) * in the flow context.
*/
#define FW_WR_FLUSH_S 22
#define FW_WR_FLUSH_V(x) ((x) << FW_WR_FLUSH_S)
/* completion flag (hi) - firmware generates a cpl_fw6_ack */
#define FW_WR_COMPL_S 21
#define FW_WR_COMPL_V(x) ((x) << FW_WR_COMPL_S)
#define FW_WR_COMPL_F FW_WR_COMPL_V(1U)
/* work request immediate data length (hi) */
#define FW_WR_IMMDLEN_S 0
#define FW_WR_IMMDLEN_M 0xff
#define FW_WR_IMMDLEN_V(x) ((x) << FW_WR_IMMDLEN_S)
/* egress queue status update to associated ingress queue entry (lo) */
#define FW_WR_EQUIQ_S 31
#define FW_WR_EQUIQ_V(x) ((x) << FW_WR_EQUIQ_S)
#define FW_WR_EQUIQ_F FW_WR_EQUIQ_V(1U)
/* egress queue status update to egress queue status entry (lo) */
#define FW_WR_EQUEQ_S 30
#define FW_WR_EQUEQ_V(x) ((x) << FW_WR_EQUEQ_S)
#define FW_WR_EQUEQ_F FW_WR_EQUEQ_V(1U)
/* flow context identifier (lo) */
#define FW_WR_FLOWID_S 8
#define FW_WR_FLOWID_V(x) ((x) << FW_WR_FLOWID_S)
/* length in units of 16-bytes (lo) */
#define FW_WR_LEN16_S 0
#define FW_WR_LEN16_V(x) ((x) << FW_WR_LEN16_S)
#define HW_TPL_FR_MT_PR_IV_P_FC 0X32B #define HW_TPL_FR_MT_PR_IV_P_FC 0X32B
#define HW_TPL_FR_MT_PR_OV_P_FC 0X327 #define HW_TPL_FR_MT_PR_OV_P_FC 0X327
...@@ -539,26 +570,47 @@ struct fw_flowc_mnemval { ...@@ -539,26 +570,47 @@ struct fw_flowc_mnemval {
struct fw_flowc_wr { struct fw_flowc_wr {
__be32 op_to_nparams; __be32 op_to_nparams;
#define FW_FLOWC_WR_NPARAMS(x) ((x) << 0)
__be32 flowid_len16; __be32 flowid_len16;
struct fw_flowc_mnemval mnemval[0]; struct fw_flowc_mnemval mnemval[0];
}; };
#define FW_FLOWC_WR_NPARAMS_S 0
#define FW_FLOWC_WR_NPARAMS_V(x) ((x) << FW_FLOWC_WR_NPARAMS_S)
struct fw_ofld_tx_data_wr { struct fw_ofld_tx_data_wr {
__be32 op_to_immdlen; __be32 op_to_immdlen;
__be32 flowid_len16; __be32 flowid_len16;
__be32 plen; __be32 plen;
__be32 tunnel_to_proxy; __be32 tunnel_to_proxy;
#define FW_OFLD_TX_DATA_WR_TUNNEL(x) ((x) << 19)
#define FW_OFLD_TX_DATA_WR_SAVE(x) ((x) << 18)
#define FW_OFLD_TX_DATA_WR_FLUSH(x) ((x) << 17)
#define FW_OFLD_TX_DATA_WR_URGENT(x) ((x) << 16)
#define FW_OFLD_TX_DATA_WR_MORE(x) ((x) << 15)
#define FW_OFLD_TX_DATA_WR_SHOVE(x) ((x) << 14)
#define FW_OFLD_TX_DATA_WR_ULPMODE(x) ((x) << 10)
#define FW_OFLD_TX_DATA_WR_ULPSUBMODE(x) ((x) << 6)
}; };
#define FW_OFLD_TX_DATA_WR_TUNNEL_S 19
#define FW_OFLD_TX_DATA_WR_TUNNEL_V(x) ((x) << FW_OFLD_TX_DATA_WR_TUNNEL_S)
#define FW_OFLD_TX_DATA_WR_SAVE_S 18
#define FW_OFLD_TX_DATA_WR_SAVE_V(x) ((x) << FW_OFLD_TX_DATA_WR_SAVE_S)
#define FW_OFLD_TX_DATA_WR_FLUSH_S 17
#define FW_OFLD_TX_DATA_WR_FLUSH_V(x) ((x) << FW_OFLD_TX_DATA_WR_FLUSH_S)
#define FW_OFLD_TX_DATA_WR_FLUSH_F FW_OFLD_TX_DATA_WR_FLUSH_V(1U)
#define FW_OFLD_TX_DATA_WR_URGENT_S 16
#define FW_OFLD_TX_DATA_WR_URGENT_V(x) ((x) << FW_OFLD_TX_DATA_WR_URGENT_S)
#define FW_OFLD_TX_DATA_WR_MORE_S 15
#define FW_OFLD_TX_DATA_WR_MORE_V(x) ((x) << FW_OFLD_TX_DATA_WR_MORE_S)
#define FW_OFLD_TX_DATA_WR_SHOVE_S 14
#define FW_OFLD_TX_DATA_WR_SHOVE_V(x) ((x) << FW_OFLD_TX_DATA_WR_SHOVE_S)
#define FW_OFLD_TX_DATA_WR_SHOVE_F FW_OFLD_TX_DATA_WR_SHOVE_V(1U)
#define FW_OFLD_TX_DATA_WR_ULPMODE_S 10
#define FW_OFLD_TX_DATA_WR_ULPMODE_V(x) ((x) << FW_OFLD_TX_DATA_WR_ULPMODE_S)
#define FW_OFLD_TX_DATA_WR_ULPSUBMODE_S 6
#define FW_OFLD_TX_DATA_WR_ULPSUBMODE_V(x) \
((x) << FW_OFLD_TX_DATA_WR_ULPSUBMODE_S)
struct fw_cmd_wr { struct fw_cmd_wr {
__be32 op_dma; __be32 op_dma;
#define FW_CMD_WR_DMA (1U << 17) #define FW_CMD_WR_DMA (1U << 17)
...@@ -566,6 +618,9 @@ struct fw_cmd_wr { ...@@ -566,6 +618,9 @@ struct fw_cmd_wr {
__be64 cookie_daddr; __be64 cookie_daddr;
}; };
#define FW_CMD_WR_DMA_S 17
#define FW_CMD_WR_DMA_V(x) ((x) << FW_CMD_WR_DMA_S)
struct fw_eth_tx_pkt_vm_wr { struct fw_eth_tx_pkt_vm_wr {
__be32 op_immdlen; __be32 op_immdlen;
__be32 equiq_to_len16; __be32 equiq_to_len16;
...@@ -641,18 +696,39 @@ struct fw_cmd_hdr { ...@@ -641,18 +696,39 @@ struct fw_cmd_hdr {
__be32 lo; __be32 lo;
}; };
#define FW_CMD_OP(x) ((x) << 24) #define FW_CMD_OP_S 24
#define FW_CMD_OP_GET(x) (((x) >> 24) & 0xff) #define FW_CMD_OP_M 0xff
#define FW_CMD_REQUEST (1U << 23) #define FW_CMD_OP_V(x) ((x) << FW_CMD_OP_S)
#define FW_CMD_REQUEST_GET(x) (((x) >> 23) & 0x1) #define FW_CMD_OP_G(x) (((x) >> FW_CMD_OP_S) & FW_CMD_OP_M)
#define FW_CMD_READ (1U << 22)
#define FW_CMD_WRITE (1U << 21) #define FW_CMD_REQUEST_S 23
#define FW_CMD_EXEC (1U << 20) #define FW_CMD_REQUEST_V(x) ((x) << FW_CMD_REQUEST_S)
#define FW_CMD_RAMASK(x) ((x) << 20) #define FW_CMD_REQUEST_F FW_CMD_REQUEST_V(1U)
#define FW_CMD_RETVAL(x) ((x) << 8)
#define FW_CMD_RETVAL_GET(x) (((x) >> 8) & 0xff) #define FW_CMD_READ_S 22
#define FW_CMD_LEN16(x) ((x) << 0) #define FW_CMD_READ_V(x) ((x) << FW_CMD_READ_S)
#define FW_LEN16(fw_struct) FW_CMD_LEN16(sizeof(fw_struct) / 16) #define FW_CMD_READ_F FW_CMD_READ_V(1U)
#define FW_CMD_WRITE_S 21
#define FW_CMD_WRITE_V(x) ((x) << FW_CMD_WRITE_S)
#define FW_CMD_WRITE_F FW_CMD_WRITE_V(1U)
#define FW_CMD_EXEC_S 20
#define FW_CMD_EXEC_V(x) ((x) << FW_CMD_EXEC_S)
#define FW_CMD_EXEC_F FW_CMD_EXEC_V(1U)
#define FW_CMD_RAMASK_S 20
#define FW_CMD_RAMASK_V(x) ((x) << FW_CMD_RAMASK_S)
#define FW_CMD_RETVAL_S 8
#define FW_CMD_RETVAL_M 0xff
#define FW_CMD_RETVAL_V(x) ((x) << FW_CMD_RETVAL_S)
#define FW_CMD_RETVAL_G(x) (((x) >> FW_CMD_RETVAL_S) & FW_CMD_RETVAL_M)
#define FW_CMD_LEN16_S 0
#define FW_CMD_LEN16_V(x) ((x) << FW_CMD_LEN16_S)
#define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
enum fw_ldst_addrspc { enum fw_ldst_addrspc {
FW_LDST_ADDRSPC_FIRMWARE = 0x0001, FW_LDST_ADDRSPC_FIRMWARE = 0x0001,
......
drivers/net/ethernet/chelsio/cxgb4vf/sge.c
View file @ c42e2533
...@@ -132,7 +132,7 @@ enum { ...@@ -132,7 +132,7 @@ enum {
* we can specify for immediate data in the firmware Ethernet TX * we can specify for immediate data in the firmware Ethernet TX
* Work Request. * Work Request.
*/ */
MAX_IMM_TX_PKT_LEN = FW_WR_IMMDLEN_MASK, MAX_IMM_TX_PKT_LEN = FW_WR_IMMDLEN_M,
/* /*
* Max size of a WR sent through a control TX queue. * Max size of a WR sent through a control TX queue.
...@@ -1149,7 +1149,7 @@ int t4vf_eth_xmit(struct sk_buff *skb, struct net_device *dev) ...@@ -1149,7 +1149,7 @@ int t4vf_eth_xmit(struct sk_buff *skb, struct net_device *dev)
goto out_free; goto out_free;
} }
wr_mid = FW_WR_LEN16(DIV_ROUND_UP(flits, 2)); wr_mid = FW_WR_LEN16_V(DIV_ROUND_UP(flits, 2));
if (unlikely(credits < ETHTXQ_STOP_THRES)) { if (unlikely(credits < ETHTXQ_STOP_THRES)) {
/* /*
* After we're done injecting the Work Request for this * After we're done injecting the Work Request for this
...@@ -1161,7 +1161,7 @@ int t4vf_eth_xmit(struct sk_buff *skb, struct net_device *dev) ...@@ -1161,7 +1161,7 @@ int t4vf_eth_xmit(struct sk_buff *skb, struct net_device *dev)
* has opened up. * has opened up.
*/ */
txq_stop(txq); txq_stop(txq);
wr_mid |= FW_WR_EQUEQ | FW_WR_EQUIQ; wr_mid |= FW_WR_EQUEQ_F | FW_WR_EQUIQ_F;
} }
/* /*
...@@ -1191,9 +1191,9 @@ int t4vf_eth_xmit(struct sk_buff *skb, struct net_device *dev) ...@@ -1191,9 +1191,9 @@ int t4vf_eth_xmit(struct sk_buff *skb, struct net_device *dev)
int eth_xtra_len = skb_network_offset(skb) - ETH_HLEN; int eth_xtra_len = skb_network_offset(skb) - ETH_HLEN;
wr->op_immdlen = wr->op_immdlen =
cpu_to_be32(FW_WR_OP(FW_ETH_TX_PKT_VM_WR) | cpu_to_be32(FW_WR_OP_V(FW_ETH_TX_PKT_VM_WR) |
FW_WR_IMMDLEN(sizeof(*lso) + FW_WR_IMMDLEN_V(sizeof(*lso) +
sizeof(*cpl))); sizeof(*cpl)));
/* /*
* Fill in the LSO CPL message. * Fill in the LSO CPL message.
*/ */
...@@ -1228,8 +1228,8 @@ int t4vf_eth_xmit(struct sk_buff *skb, struct net_device *dev) ...@@ -1228,8 +1228,8 @@ int t4vf_eth_xmit(struct sk_buff *skb, struct net_device *dev)
len = is_eth_imm(skb) ? skb->len + sizeof(*cpl) : sizeof(*cpl); len = is_eth_imm(skb) ? skb->len + sizeof(*cpl) : sizeof(*cpl);
wr->op_immdlen = wr->op_immdlen =
cpu_to_be32(FW_WR_OP(FW_ETH_TX_PKT_VM_WR) | cpu_to_be32(FW_WR_OP_V(FW_ETH_TX_PKT_VM_WR) |
FW_WR_IMMDLEN(len)); FW_WR_IMMDLEN_V(len));
/* /*
* Set up TX Packet CPL pointer, control word and perform * Set up TX Packet CPL pointer, control word and perform
...@@ -2084,10 +2084,10 @@ int t4vf_sge_alloc_rxq(struct adapter *adapter, struct sge_rspq *rspq, ...@@ -2084,10 +2084,10 @@ int t4vf_sge_alloc_rxq(struct adapter *adapter, struct sge_rspq *rspq,
* into OS-independent common code ... * into OS-independent common code ...
*/ */
memset(&cmd, 0, sizeof(cmd)); memset(&cmd, 0, sizeof(cmd));
cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP(FW_IQ_CMD) | cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) |
FW_CMD_REQUEST | FW_CMD_REQUEST_F |
FW_CMD_WRITE | FW_CMD_WRITE_F |
FW_CMD_EXEC); FW_CMD_EXEC_F);
cmd.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_ALLOC | cmd.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_ALLOC |
FW_IQ_CMD_IQSTART(1) | FW_IQ_CMD_IQSTART(1) |
FW_LEN16(cmd)); FW_LEN16(cmd));
...@@ -2246,10 +2246,10 @@ int t4vf_sge_alloc_eth_txq(struct adapter *adapter, struct sge_eth_txq *txq, ...@@ -2246,10 +2246,10 @@ int t4vf_sge_alloc_eth_txq(struct adapter *adapter, struct sge_eth_txq *txq,
* into the common code ... * into the common code ...
*/ */
memset(&cmd, 0, sizeof(cmd)); memset(&cmd, 0, sizeof(cmd));
cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP(FW_EQ_ETH_CMD) | cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_ETH_CMD) |
FW_CMD_REQUEST | FW_CMD_REQUEST_F |
FW_CMD_WRITE | FW_CMD_WRITE_F |
FW_CMD_EXEC); FW_CMD_EXEC_F);
cmd.alloc_to_len16 = cpu_to_be32(FW_EQ_ETH_CMD_ALLOC | cmd.alloc_to_len16 = cpu_to_be32(FW_EQ_ETH_CMD_ALLOC |
FW_EQ_ETH_CMD_EQSTART | FW_EQ_ETH_CMD_EQSTART |
FW_LEN16(cmd)); FW_LEN16(cmd));
......
drivers/net/ethernet/chelsio/cxgb4vf/t4vf_common.h
View file @ c42e2533
...@@ -67,7 +67,7 @@ enum chip_type { ...@@ -67,7 +67,7 @@ enum chip_type {
/* /*
* The "len16" field of a Firmware Command Structure ... * The "len16" field of a Firmware Command Structure ...
*/ */
#define FW_LEN16(fw_struct) FW_CMD_LEN16(sizeof(fw_struct) / 16) #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
/* /*
* Per-VF statistics. * Per-VF statistics.
......
drivers/scsi/csiostor/csio_attr.c
View file @ c42e2533
...@@ -451,9 +451,9 @@ csio_fcoe_alloc_vnp(struct csio_hw *hw, struct csio_lnode *ln) ...@@ -451,9 +451,9 @@ csio_fcoe_alloc_vnp(struct csio_hw *hw, struct csio_lnode *ln)
/* Process Mbox response of VNP command */ /* Process Mbox response of VNP command */
rsp = (struct fw_fcoe_vnp_cmd *)(mbp->mb); rsp = (struct fw_fcoe_vnp_cmd *)(mbp->mb);
if (FW_CMD_RETVAL_GET(ntohl(rsp->alloc_to_len16)) != FW_SUCCESS) { if (FW_CMD_RETVAL_G(ntohl(rsp->alloc_to_len16)) != FW_SUCCESS) {
csio_ln_err(ln, "FCOE VNP ALLOC cmd returned 0x%x!\n", csio_ln_err(ln, "FCOE VNP ALLOC cmd returned 0x%x!\n",
FW_CMD_RETVAL_GET(ntohl(rsp->alloc_to_len16))); FW_CMD_RETVAL_G(ntohl(rsp->alloc_to_len16)));
ret = -EINVAL; ret = -EINVAL;
goto out_free; goto out_free;
} }
...@@ -526,9 +526,9 @@ csio_fcoe_free_vnp(struct csio_hw *hw, struct csio_lnode *ln) ...@@ -526,9 +526,9 @@ csio_fcoe_free_vnp(struct csio_hw *hw, struct csio_lnode *ln)
/* Process Mbox response of VNP command */ /* Process Mbox response of VNP command */
rsp = (struct fw_fcoe_vnp_cmd *)(mbp->mb); rsp = (struct fw_fcoe_vnp_cmd *)(mbp->mb);
if (FW_CMD_RETVAL_GET(ntohl(rsp->alloc_to_len16)) != FW_SUCCESS) { if (FW_CMD_RETVAL_G(ntohl(rsp->alloc_to_len16)) != FW_SUCCESS) {
csio_ln_err(ln, "FCOE VNP FREE cmd returned 0x%x!\n", csio_ln_err(ln, "FCOE VNP FREE cmd returned 0x%x!\n",
FW_CMD_RETVAL_GET(ntohl(rsp->alloc_to_len16))); FW_CMD_RETVAL_G(ntohl(rsp->alloc_to_len16)));
ret = -EINVAL; ret = -EINVAL;
} }
......
drivers/scsi/csiostor/csio_hw.c
View file @ c42e2533
...@@ -1370,9 +1370,9 @@ csio_hw_fw_config_file(struct csio_hw *hw, ...@@ -1370,9 +1370,9 @@ csio_hw_fw_config_file(struct csio_hw *hw,
caps_cmd = (struct fw_caps_config_cmd *)(mbp->mb); caps_cmd = (struct fw_caps_config_cmd *)(mbp->mb);
CSIO_INIT_MBP(mbp, caps_cmd, CSIO_MB_DEFAULT_TMO, hw, NULL, 1); CSIO_INIT_MBP(mbp, caps_cmd, CSIO_MB_DEFAULT_TMO, hw, NULL, 1);
caps_cmd->op_to_write = caps_cmd->op_to_write =
htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) | htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
FW_CMD_REQUEST | FW_CMD_REQUEST_F |
FW_CMD_READ); FW_CMD_READ_F);
caps_cmd->cfvalid_to_len16 = caps_cmd->cfvalid_to_len16 =
htonl(FW_CAPS_CONFIG_CMD_CFVALID | htonl(FW_CAPS_CONFIG_CMD_CFVALID |
FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) | FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
...@@ -1407,9 +1407,9 @@ csio_hw_fw_config_file(struct csio_hw *hw, ...@@ -1407,9 +1407,9 @@ csio_hw_fw_config_file(struct csio_hw *hw,
* And now tell the firmware to use the configuration we just loaded. * And now tell the firmware to use the configuration we just loaded.
*/ */
caps_cmd->op_to_write = caps_cmd->op_to_write =
htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) | htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
FW_CMD_REQUEST | FW_CMD_REQUEST_F |
FW_CMD_WRITE); FW_CMD_WRITE_F);
caps_cmd->cfvalid_to_len16 = htonl(FW_LEN16(*caps_cmd)); caps_cmd->cfvalid_to_len16 = htonl(FW_LEN16(*caps_cmd));
if (csio_mb_issue(hw, mbp)) { if (csio_mb_issue(hw, mbp)) {
...@@ -1678,7 +1678,7 @@ csio_get_fcoe_resinfo(struct csio_hw *hw) ...@@ -1678,7 +1678,7 @@ csio_get_fcoe_resinfo(struct csio_hw *hw)
} }
rsp = (struct fw_fcoe_res_info_cmd *)(mbp->mb); rsp = (struct fw_fcoe_res_info_cmd *)(mbp->mb);
retval = FW_CMD_RETVAL_GET(ntohl(rsp->retval_len16)); retval = FW_CMD_RETVAL_G(ntohl(rsp->retval_len16));
if (retval != FW_SUCCESS) { if (retval != FW_SUCCESS) {
csio_err(hw, "FW_FCOE_RES_INFO_CMD failed with ret x%x\n", csio_err(hw, "FW_FCOE_RES_INFO_CMD failed with ret x%x\n",
retval); retval);
......
drivers/scsi/csiostor/csio_hw_t4.c
View file @ c42e2533
...@@ -307,12 +307,12 @@ csio_t4_memory_rw(struct csio_hw *hw, u32 win, int mtype, u32 addr, ...@@ -307,12 +307,12 @@ csio_t4_memory_rw(struct csio_hw *hw, u32 win, int mtype, u32 addr,
* MEM_EDC1 = 1 * MEM_EDC1 = 1
* MEM_MC = 2 -- T4 * MEM_MC = 2 -- T4
*/ */
edc_size = EDRAM_SIZE_GET(csio_rd_reg32(hw, MA_EDRAM0_BAR)); edc_size = EDRAM0_SIZE_G(csio_rd_reg32(hw, MA_EDRAM0_BAR_A));
if (mtype != MEM_MC1) if (mtype != MEM_MC1)
memoffset = (mtype * (edc_size * 1024 * 1024)); memoffset = (mtype * (edc_size * 1024 * 1024));
else { else {
mc_size = EXT_MEM_SIZE_GET(csio_rd_reg32(hw, mc_size = EXT_MEM_SIZE_G(csio_rd_reg32(hw,
MA_EXT_MEMORY_BAR)); MA_EXT_MEMORY_BAR_A));
memoffset = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024; memoffset = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024;
} }
...@@ -383,11 +383,12 @@ static void ...@@ -383,11 +383,12 @@ static void
csio_t4_dfs_create_ext_mem(struct csio_hw *hw) csio_t4_dfs_create_ext_mem(struct csio_hw *hw)
{ {
u32 size; u32 size;
int i = csio_rd_reg32(hw, MA_TARGET_MEM_ENABLE); int i = csio_rd_reg32(hw, MA_TARGET_MEM_ENABLE_A);
if (i & EXT_MEM_ENABLE) {
size = csio_rd_reg32(hw, MA_EXT_MEMORY_BAR); if (i & EXT_MEM_ENABLE_F) {
size = csio_rd_reg32(hw, MA_EXT_MEMORY_BAR_A);
csio_add_debugfs_mem(hw, "mc", MEM_MC, csio_add_debugfs_mem(hw, "mc", MEM_MC,
EXT_MEM_SIZE_GET(size)); EXT_MEM_SIZE_G(size));
} }
} }
......
drivers/scsi/csiostor/csio_hw_t5.c
View file @ c42e2533
...@@ -298,12 +298,12 @@ csio_t5_memory_rw(struct csio_hw *hw, u32 win, int mtype, u32 addr, ...@@ -298,12 +298,12 @@ csio_t5_memory_rw(struct csio_hw *hw, u32 win, int mtype, u32 addr,
* MEM_MC0 = 2 -- For T5 * MEM_MC0 = 2 -- For T5
* MEM_MC1 = 3 -- For T5 * MEM_MC1 = 3 -- For T5
*/ */
edc_size = EDRAM_SIZE_GET(csio_rd_reg32(hw, MA_EDRAM0_BAR)); edc_size = EDRAM0_SIZE_G(csio_rd_reg32(hw, MA_EDRAM0_BAR_A));
if (mtype != MEM_MC1) if (mtype != MEM_MC1)
memoffset = (mtype * (edc_size * 1024 * 1024)); memoffset = (mtype * (edc_size * 1024 * 1024));
else { else {
mc_size = EXT_MEM_SIZE_GET(csio_rd_reg32(hw, mc_size = EXT_MEM_SIZE_G(csio_rd_reg32(hw,
MA_EXT_MEMORY_BAR)); MA_EXT_MEMORY_BAR_A));
memoffset = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024; memoffset = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024;
} }
...@@ -372,16 +372,17 @@ static void ...@@ -372,16 +372,17 @@ static void
csio_t5_dfs_create_ext_mem(struct csio_hw *hw) csio_t5_dfs_create_ext_mem(struct csio_hw *hw)
{ {
u32 size; u32 size;
int i = csio_rd_reg32(hw, MA_TARGET_MEM_ENABLE); int i = csio_rd_reg32(hw, MA_TARGET_MEM_ENABLE_A);
if (i & EXT_MEM_ENABLE) {
size = csio_rd_reg32(hw, MA_EXT_MEMORY_BAR); if (i & EXT_MEM_ENABLE_F) {
size = csio_rd_reg32(hw, MA_EXT_MEMORY_BAR_A);
csio_add_debugfs_mem(hw, "mc0", MEM_MC0, csio_add_debugfs_mem(hw, "mc0", MEM_MC0,
EXT_MEM_SIZE_GET(size)); EXT_MEM_SIZE_G(size));
} }
if (i & EXT_MEM1_ENABLE) { if (i & EXT_MEM1_ENABLE_F) {
size = csio_rd_reg32(hw, MA_EXT_MEMORY1_BAR); size = csio_rd_reg32(hw, MA_EXT_MEMORY1_BAR_A);
csio_add_debugfs_mem(hw, "mc1", MEM_MC1, csio_add_debugfs_mem(hw, "mc1", MEM_MC1,
EXT_MEM_SIZE_GET(size)); EXT_MEM_SIZE_G(size));
} }
} }
......
drivers/scsi/csiostor/csio_init.c
View file @ c42e2533
...@@ -128,10 +128,10 @@ static int csio_setup_debugfs(struct csio_hw *hw) ...@@ -128,10 +128,10 @@ static int csio_setup_debugfs(struct csio_hw *hw)
if (IS_ERR_OR_NULL(hw->debugfs_root)) if (IS_ERR_OR_NULL(hw->debugfs_root))
return -1; return -1;
i = csio_rd_reg32(hw, MA_TARGET_MEM_ENABLE); i = csio_rd_reg32(hw, MA_TARGET_MEM_ENABLE_A);
if (i & EDRAM0_ENABLE) if (i & EDRAM0_ENABLE_F)
csio_add_debugfs_mem(hw, "edc0", MEM_EDC0, 5); csio_add_debugfs_mem(hw, "edc0", MEM_EDC0, 5);
if (i & EDRAM1_ENABLE) if (i & EDRAM1_ENABLE_F)
csio_add_debugfs_mem(hw, "edc1", MEM_EDC1, 5); csio_add_debugfs_mem(hw, "edc1", MEM_EDC1, 5);
hw->chip_ops->chip_dfs_create_ext_mem(hw); hw->chip_ops->chip_dfs_create_ext_mem(hw);
......
drivers/scsi/csiostor/csio_lnode.c
View file @ c42e2533
...@@ -603,7 +603,7 @@ csio_ln_vnp_read_cbfn(struct csio_hw *hw, struct csio_mb *mbp) ...@@ -603,7 +603,7 @@ csio_ln_vnp_read_cbfn(struct csio_hw *hw, struct csio_mb *mbp)
enum fw_retval retval; enum fw_retval retval;
__be32 nport_id; __be32 nport_id;
retval = FW_CMD_RETVAL_GET(ntohl(rsp->alloc_to_len16)); retval = FW_CMD_RETVAL_G(ntohl(rsp->alloc_to_len16));
if (retval != FW_SUCCESS) { if (retval != FW_SUCCESS) {
csio_err(hw, "FCOE VNP read cmd returned error:0x%x\n", retval); csio_err(hw, "FCOE VNP read cmd returned error:0x%x\n", retval);
mempool_free(mbp, hw->mb_mempool); mempool_free(mbp, hw->mb_mempool);
...@@ -770,7 +770,7 @@ csio_ln_read_fcf_cbfn(struct csio_hw *hw, struct csio_mb *mbp) ...@@ -770,7 +770,7 @@ csio_ln_read_fcf_cbfn(struct csio_hw *hw, struct csio_mb *mbp)
(struct fw_fcoe_fcf_cmd *)(mbp->mb); (struct fw_fcoe_fcf_cmd *)(mbp->mb);
enum fw_retval retval; enum fw_retval retval;
retval = FW_CMD_RETVAL_GET(ntohl(rsp->retval_len16)); retval = FW_CMD_RETVAL_G(ntohl(rsp->retval_len16));
if (retval != FW_SUCCESS) { if (retval != FW_SUCCESS) {
csio_ln_err(ln, "FCOE FCF cmd failed with ret x%x\n", csio_ln_err(ln, "FCOE FCF cmd failed with ret x%x\n",
retval); retval);
...@@ -1506,7 +1506,7 @@ csio_fcoe_fwevt_handler(struct csio_hw *hw, __u8 cpl_op, __be64 *cmd) ...@@ -1506,7 +1506,7 @@ csio_fcoe_fwevt_handler(struct csio_hw *hw, __u8 cpl_op, __be64 *cmd)
} }
} else if (cpl_op == CPL_FW6_PLD) { } else if (cpl_op == CPL_FW6_PLD) {
wr = (struct fw_wr_hdr *) (cmd + 4); wr = (struct fw_wr_hdr *) (cmd + 4);
if (FW_WR_OP_GET(be32_to_cpu(wr->hi)) if (FW_WR_OP_G(be32_to_cpu(wr->hi))
== FW_RDEV_WR) { == FW_RDEV_WR) {
rdev_wr = (struct fw_rdev_wr *) (cmd + 4); rdev_wr = (struct fw_rdev_wr *) (cmd + 4);
...@@ -1574,17 +1574,17 @@ csio_fcoe_fwevt_handler(struct csio_hw *hw, __u8 cpl_op, __be64 *cmd) ...@@ -1574,17 +1574,17 @@ csio_fcoe_fwevt_handler(struct csio_hw *hw, __u8 cpl_op, __be64 *cmd)
return; return;
} else { } else {
csio_warn(hw, "unexpected WR op(0x%x) recv\n", csio_warn(hw, "unexpected WR op(0x%x) recv\n",
FW_WR_OP_GET(be32_to_cpu((wr->hi)))); FW_WR_OP_G(be32_to_cpu((wr->hi))));
CSIO_INC_STATS(hw, n_cpl_unexp); CSIO_INC_STATS(hw, n_cpl_unexp);
} }
} else if (cpl_op == CPL_FW6_MSG) { } else if (cpl_op == CPL_FW6_MSG) {
wr = (struct fw_wr_hdr *) (cmd); wr = (struct fw_wr_hdr *) (cmd);
if (FW_WR_OP_GET(be32_to_cpu(wr->hi)) == FW_FCOE_ELS_CT_WR) { if (FW_WR_OP_G(be32_to_cpu(wr->hi)) == FW_FCOE_ELS_CT_WR) {
csio_ln_mgmt_wr_handler(hw, wr, csio_ln_mgmt_wr_handler(hw, wr,
sizeof(struct fw_fcoe_els_ct_wr)); sizeof(struct fw_fcoe_els_ct_wr));
} else { } else {
csio_warn(hw, "unexpected WR op(0x%x) recv\n", csio_warn(hw, "unexpected WR op(0x%x) recv\n",
FW_WR_OP_GET(be32_to_cpu((wr->hi)))); FW_WR_OP_G(be32_to_cpu((wr->hi))));
CSIO_INC_STATS(hw, n_cpl_unexp); CSIO_INC_STATS(hw, n_cpl_unexp);
} }
} else { } else {
...@@ -1668,12 +1668,12 @@ csio_ln_prep_ecwr(struct csio_ioreq *io_req, uint32_t wr_len, ...@@ -1668,12 +1668,12 @@ csio_ln_prep_ecwr(struct csio_ioreq *io_req, uint32_t wr_len,
__be32 port_id; __be32 port_id;
wr = (struct fw_fcoe_els_ct_wr *)fw_wr; wr = (struct fw_fcoe_els_ct_wr *)fw_wr;
wr->op_immdlen = cpu_to_be32(FW_WR_OP(FW_FCOE_ELS_CT_WR) | wr->op_immdlen = cpu_to_be32(FW_WR_OP_V(FW_FCOE_ELS_CT_WR) |
FW_FCOE_ELS_CT_WR_IMMDLEN(immd_len)); FW_FCOE_ELS_CT_WR_IMMDLEN(immd_len));
wr_len = DIV_ROUND_UP(wr_len, 16); wr_len = DIV_ROUND_UP(wr_len, 16);
wr->flowid_len16 = cpu_to_be32(FW_WR_FLOWID(flow_id) | wr->flowid_len16 = cpu_to_be32(FW_WR_FLOWID_V(flow_id) |
FW_WR_LEN16(wr_len)); FW_WR_LEN16_V(wr_len));
wr->els_ct_type = sub_op; wr->els_ct_type = sub_op;
wr->ctl_pri = 0; wr->ctl_pri = 0;
wr->cp_en_class = 0; wr->cp_en_class = 0;
......
drivers/scsi/csiostor/csio_mb.c
View file @ c42e2533
This diff is collapsed.
drivers/scsi/csiostor/csio_scsi.c
View file @ c42e2533
...@@ -230,10 +230,10 @@ csio_scsi_init_cmd_wr(struct csio_ioreq *req, void *addr, uint32_t size) ...@@ -230,10 +230,10 @@ csio_scsi_init_cmd_wr(struct csio_ioreq *req, void *addr, uint32_t size)
struct csio_dma_buf *dma_buf; struct csio_dma_buf *dma_buf;
uint8_t imm = csio_hw_to_scsim(hw)->proto_cmd_len; uint8_t imm = csio_hw_to_scsim(hw)->proto_cmd_len;
wr->op_immdlen = cpu_to_be32(FW_WR_OP(FW_SCSI_CMD_WR) | wr->op_immdlen = cpu_to_be32(FW_WR_OP_V(FW_SCSI_CMD_WR) |
FW_SCSI_CMD_WR_IMMDLEN(imm)); FW_SCSI_CMD_WR_IMMDLEN(imm));
wr->flowid_len16 = cpu_to_be32(FW_WR_FLOWID(rn->flowid) | wr->flowid_len16 = cpu_to_be32(FW_WR_FLOWID_V(rn->flowid) |
FW_WR_LEN16( FW_WR_LEN16_V(
DIV_ROUND_UP(size, 16))); DIV_ROUND_UP(size, 16)));
wr->cookie = (uintptr_t) req; wr->cookie = (uintptr_t) req;
...@@ -391,10 +391,10 @@ csio_scsi_init_read_wr(struct csio_ioreq *req, void *wrp, uint32_t size) ...@@ -391,10 +391,10 @@ csio_scsi_init_read_wr(struct csio_ioreq *req, void *wrp, uint32_t size)
uint8_t imm = csio_hw_to_scsim(hw)->proto_cmd_len; uint8_t imm = csio_hw_to_scsim(hw)->proto_cmd_len;
struct scsi_cmnd *scmnd = csio_scsi_cmnd(req); struct scsi_cmnd *scmnd = csio_scsi_cmnd(req);
wr->op_immdlen = cpu_to_be32(FW_WR_OP(FW_SCSI_READ_WR) | wr->op_immdlen = cpu_to_be32(FW_WR_OP_V(FW_SCSI_READ_WR) |
FW_SCSI_READ_WR_IMMDLEN(imm)); FW_SCSI_READ_WR_IMMDLEN(imm));
wr->flowid_len16 = cpu_to_be32(FW_WR_FLOWID(rn->flowid) | wr->flowid_len16 = cpu_to_be32(FW_WR_FLOWID_V(rn->flowid) |
FW_WR_LEN16(DIV_ROUND_UP(size, 16))); FW_WR_LEN16_V(DIV_ROUND_UP(size, 16)));
wr->cookie = (uintptr_t)req; wr->cookie = (uintptr_t)req;
wr->iqid = cpu_to_be16(csio_q_physiqid(hw, req->iq_idx)); wr->iqid = cpu_to_be16(csio_q_physiqid(hw, req->iq_idx));
wr->tmo_val = (uint8_t)(req->tmo); wr->tmo_val = (uint8_t)(req->tmo);
...@@ -444,10 +444,10 @@ csio_scsi_init_write_wr(struct csio_ioreq *req, void *wrp, uint32_t size) ...@@ -444,10 +444,10 @@ csio_scsi_init_write_wr(struct csio_ioreq *req, void *wrp, uint32_t size)
uint8_t imm = csio_hw_to_scsim(hw)->proto_cmd_len; uint8_t imm = csio_hw_to_scsim(hw)->proto_cmd_len;
struct scsi_cmnd *scmnd = csio_scsi_cmnd(req); struct scsi_cmnd *scmnd = csio_scsi_cmnd(req);
wr->op_immdlen = cpu_to_be32(FW_WR_OP(FW_SCSI_WRITE_WR) | wr->op_immdlen = cpu_to_be32(FW_WR_OP_V(FW_SCSI_WRITE_WR) |
FW_SCSI_WRITE_WR_IMMDLEN(imm)); FW_SCSI_WRITE_WR_IMMDLEN(imm));
wr->flowid_len16 = cpu_to_be32(FW_WR_FLOWID(rn->flowid) | wr->flowid_len16 = cpu_to_be32(FW_WR_FLOWID_V(rn->flowid) |
FW_WR_LEN16(DIV_ROUND_UP(size, 16))); FW_WR_LEN16_V(DIV_ROUND_UP(size, 16)));
wr->cookie = (uintptr_t)req; wr->cookie = (uintptr_t)req;
wr->iqid = cpu_to_be16(csio_q_physiqid(hw, req->iq_idx)); wr->iqid = cpu_to_be16(csio_q_physiqid(hw, req->iq_idx));
wr->tmo_val = (uint8_t)(req->tmo); wr->tmo_val = (uint8_t)(req->tmo);
...@@ -674,9 +674,9 @@ csio_scsi_init_abrt_cls_wr(struct csio_ioreq *req, void *addr, uint32_t size, ...@@ -674,9 +674,9 @@ csio_scsi_init_abrt_cls_wr(struct csio_ioreq *req, void *addr, uint32_t size,
struct csio_rnode *rn = req->rnode; struct csio_rnode *rn = req->rnode;
struct fw_scsi_abrt_cls_wr *wr = (struct fw_scsi_abrt_cls_wr *)addr; struct fw_scsi_abrt_cls_wr *wr = (struct fw_scsi_abrt_cls_wr *)addr;
wr->op_immdlen = cpu_to_be32(FW_WR_OP(FW_SCSI_ABRT_CLS_WR)); wr->op_immdlen = cpu_to_be32(FW_WR_OP_V(FW_SCSI_ABRT_CLS_WR));
wr->flowid_len16 = cpu_to_be32(FW_WR_FLOWID(rn->flowid) | wr->flowid_len16 = cpu_to_be32(FW_WR_FLOWID_V(rn->flowid) |
FW_WR_LEN16( FW_WR_LEN16_V(
DIV_ROUND_UP(size, 16))); DIV_ROUND_UP(size, 16)));
wr->cookie = (uintptr_t) req; wr->cookie = (uintptr_t) req;
......
drivers/scsi/csiostor/csio_wr.h
View file @ c42e2533
...@@ -101,7 +101,7 @@ ...@@ -101,7 +101,7 @@
/* WR status is at the same position as retval in a CMD header */ /* WR status is at the same position as retval in a CMD header */
#define csio_wr_status(_wr) \ #define csio_wr_status(_wr) \
(FW_CMD_RETVAL_GET(ntohl(((struct fw_cmd_hdr *)(_wr))->lo))) (FW_CMD_RETVAL_G(ntohl(((struct fw_cmd_hdr *)(_wr))->lo)))
struct csio_hw; struct csio_hw;
......
drivers/scsi/cxgbi/cxgb4i/cxgb4i.c
View file @ c42e2533
...@@ -499,10 +499,10 @@ static inline void send_tx_flowc_wr(struct cxgbi_sock *csk) ...@@ -499,10 +499,10 @@ static inline void send_tx_flowc_wr(struct cxgbi_sock *csk)
skb = alloc_wr(flowclen, 0, GFP_ATOMIC); skb = alloc_wr(flowclen, 0, GFP_ATOMIC);
flowc = (struct fw_flowc_wr *)skb->head; flowc = (struct fw_flowc_wr *)skb->head;
flowc->op_to_nparams = flowc->op_to_nparams =
htonl(FW_WR_OP(FW_FLOWC_WR) | FW_FLOWC_WR_NPARAMS(8)); htonl(FW_WR_OP_V(FW_FLOWC_WR) | FW_FLOWC_WR_NPARAMS_V(8));
flowc->flowid_len16 = flowc->flowid_len16 =
htonl(FW_WR_LEN16(DIV_ROUND_UP(72, 16)) | htonl(FW_WR_LEN16_V(DIV_ROUND_UP(72, 16)) |
FW_WR_FLOWID(csk->tid)); FW_WR_FLOWID_V(csk->tid));
flowc->mnemval[0].mnemonic = FW_FLOWC_MNEM_PFNVFN; flowc->mnemval[0].mnemonic = FW_FLOWC_MNEM_PFNVFN;
flowc->mnemval[0].val = htonl(csk->cdev->pfvf); flowc->mnemval[0].val = htonl(csk->cdev->pfvf);
flowc->mnemval[1].mnemonic = FW_FLOWC_MNEM_CH; flowc->mnemval[1].mnemonic = FW_FLOWC_MNEM_CH;
...@@ -542,30 +542,31 @@ static inline void make_tx_data_wr(struct cxgbi_sock *csk, struct sk_buff *skb, ...@@ -542,30 +542,31 @@ static inline void make_tx_data_wr(struct cxgbi_sock *csk, struct sk_buff *skb,
{ {
struct fw_ofld_tx_data_wr *req; struct fw_ofld_tx_data_wr *req;
unsigned int submode = cxgbi_skcb_ulp_mode(skb) & 3; unsigned int submode = cxgbi_skcb_ulp_mode(skb) & 3;
unsigned int wr_ulp_mode = 0; unsigned int wr_ulp_mode = 0, val;
req = (struct fw_ofld_tx_data_wr *)__skb_push(skb, sizeof(*req)); req = (struct fw_ofld_tx_data_wr *)__skb_push(skb, sizeof(*req));
if (is_ofld_imm(skb)) { if (is_ofld_imm(skb)) {
req->op_to_immdlen = htonl(FW_WR_OP(FW_OFLD_TX_DATA_WR) | req->op_to_immdlen = htonl(FW_WR_OP_V(FW_OFLD_TX_DATA_WR) |
FW_WR_COMPL(1) | FW_WR_COMPL_F |
FW_WR_IMMDLEN(dlen)); FW_WR_IMMDLEN_V(dlen));
req->flowid_len16 = htonl(FW_WR_FLOWID(csk->tid) | req->flowid_len16 = htonl(FW_WR_FLOWID_V(csk->tid) |
FW_WR_LEN16(credits)); FW_WR_LEN16_V(credits));
} else { } else {
req->op_to_immdlen = req->op_to_immdlen =
cpu_to_be32(FW_WR_OP(FW_OFLD_TX_DATA_WR) | cpu_to_be32(FW_WR_OP_V(FW_OFLD_TX_DATA_WR) |
FW_WR_COMPL(1) | FW_WR_COMPL_F |
FW_WR_IMMDLEN(0)); FW_WR_IMMDLEN_V(0));
req->flowid_len16 = req->flowid_len16 =
cpu_to_be32(FW_WR_FLOWID(csk->tid) | cpu_to_be32(FW_WR_FLOWID_V(csk->tid) |
FW_WR_LEN16(credits)); FW_WR_LEN16_V(credits));
} }
if (submode) if (submode)
wr_ulp_mode = FW_OFLD_TX_DATA_WR_ULPMODE(ULP2_MODE_ISCSI) | wr_ulp_mode = FW_OFLD_TX_DATA_WR_ULPMODE_V(ULP2_MODE_ISCSI) |
FW_OFLD_TX_DATA_WR_ULPSUBMODE(submode); FW_OFLD_TX_DATA_WR_ULPSUBMODE_V(submode);
val = skb_peek(&csk->write_queue) ? 0 : 1;
req->tunnel_to_proxy = htonl(wr_ulp_mode | req->tunnel_to_proxy = htonl(wr_ulp_mode |
FW_OFLD_TX_DATA_WR_SHOVE(skb_peek(&csk->write_queue) ? 0 : 1)); FW_OFLD_TX_DATA_WR_SHOVE_V(val));
req->plen = htonl(len); req->plen = htonl(len);
if (!cxgbi_sock_flag(csk, CTPF_TX_DATA_SENT)) if (!cxgbi_sock_flag(csk, CTPF_TX_DATA_SENT))
cxgbi_sock_set_flag(csk, CTPF_TX_DATA_SENT); cxgbi_sock_set_flag(csk, CTPF_TX_DATA_SENT);
......
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