Commit c8cb5f77 authored by Srinivas Kandagatla's avatar Srinivas Kandagatla Committed by Mark Brown

ASoC: wcd9335: add CLASS-H Controller support

CLASS-H controller/Amplifier is common accorss Qualcomm WCD codec series.
This patchset adds basic CLASS-H controller apis for WCD codecs after
wcd9335 to use.
Signed-off-by: default avatarSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: default avatarVinod Koul <vkoul@kernel.org>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent e57d4ca8
......@@ -192,7 +192,7 @@ snd-soc-twl4030-objs := twl4030.o
snd-soc-twl6040-objs := twl6040.o
snd-soc-uda134x-objs := uda134x.o
snd-soc-uda1380-objs := uda1380.o
snd-soc-wcd9335-objs := wcd9335.o
snd-soc-wcd9335-objs := wcd-clsh.o wcd9335.o
snd-soc-wl1273-objs := wl1273.o
snd-soc-wm-adsp-objs := wm_adsp.o
snd-soc-wm0010-objs := wm0010.o
......
This diff is collapsed.
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _WCD_CLSH_V2_H_
#define _WCD_CLSH_V2_H_
#include <sound/soc.h>
enum wcd_clsh_event {
WCD_CLSH_EVENT_PRE_DAC = 1,
WCD_CLSH_EVENT_POST_PA,
};
/*
* Basic states for Class H state machine.
* represented as a bit mask within a u8 data type
* bit 0: EAR mode
* bit 1: HPH Left mode
* bit 2: HPH Right mode
* bit 3: Lineout mode
*/
#define WCD_CLSH_STATE_IDLE 0
#define WCD_CLSH_STATE_EAR BIT(0)
#define WCD_CLSH_STATE_HPHL BIT(1)
#define WCD_CLSH_STATE_HPHR BIT(2)
#define WCD_CLSH_STATE_LO BIT(3)
#define WCD_CLSH_STATE_MAX 4
#define NUM_CLSH_STATES_V2 BIT(WCD_CLSH_STATE_MAX)
enum wcd_clsh_mode {
CLS_H_NORMAL = 0, /* Class-H Default */
CLS_H_HIFI, /* Class-H HiFi */
CLS_H_LP, /* Class-H Low Power */
CLS_AB, /* Class-AB */
CLS_H_LOHIFI, /* LoHIFI */
CLS_NONE, /* None of the above modes */
};
struct wcd_clsh_ctrl;
extern struct wcd_clsh_ctrl *wcd_clsh_ctrl_alloc(
struct snd_soc_component *component,
int version);
extern void wcd_clsh_ctrl_free(struct wcd_clsh_ctrl *ctrl);
extern int wcd_clsh_ctrl_get_state(struct wcd_clsh_ctrl *ctrl);
extern int wcd_clsh_ctrl_set_state(struct wcd_clsh_ctrl *ctrl,
enum wcd_clsh_event event,
int state,
enum wcd_clsh_mode mode);
#endif /* _WCD_CLSH_V2_H_ */
......@@ -21,6 +21,7 @@
#include <dt-bindings/mfd/wcd9335.h>
#include <linux/mfd/wcd9335/wcd9335.h>
#include <linux/mfd/wcd9335/registers.h>
#include "wcd-clsh.h"
#define WCD9335_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
......@@ -181,6 +182,7 @@ struct wcd9335_codec {
int sido_ccl_cnt;
enum wcd_clock_type clk_type;
struct wcd_clsh_ctrl *clsh_ctrl;
u32 hph_mode;
};
......@@ -1066,6 +1068,13 @@ static int wcd9335_codec_probe(struct snd_soc_component *component)
int i;
snd_soc_component_init_regmap(component, wcd->regmap);
/* Class-H Init*/
wcd->clsh_ctrl = wcd_clsh_ctrl_alloc(component, wcd->version);
if (IS_ERR(wcd->clsh_ctrl))
return PTR_ERR(wcd->clsh_ctrl);
/* Default HPH Mode to Class-H HiFi */
wcd->hph_mode = CLS_H_HIFI;
wcd->component = component;
wcd9335_codec_init(component);
......@@ -1080,6 +1089,7 @@ static void wcd9335_codec_remove(struct snd_soc_component *comp)
{
struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
wcd_clsh_ctrl_free(wcd->clsh_ctrl);
free_irq(regmap_irq_get_virq(wcd->irq_data, WCD9335_IRQ_SLIMBUS), wcd);
}
......
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