Commit c9068eb2 authored by Alex Deucher's avatar Alex Deucher Committed by Dave Airlie

drm/radeon/kms: add r1xx/r2xx support for CS_KEEP_TILING_FLAGS

Previous patch only updates r3xx+.  It's not likely
anyone will use this on r1xx/r2xx, but add it for consistency.
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent 9292f37e
...@@ -87,23 +87,27 @@ int r100_reloc_pitch_offset(struct radeon_cs_parser *p, ...@@ -87,23 +87,27 @@ int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
r100_cs_dump_packet(p, pkt); r100_cs_dump_packet(p, pkt);
return r; return r;
} }
value = radeon_get_ib_value(p, idx); value = radeon_get_ib_value(p, idx);
tmp = value & 0x003fffff; tmp = value & 0x003fffff;
tmp += (((u32)reloc->lobj.gpu_offset) >> 10); tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
tile_flags |= RADEON_DST_TILE_MACRO; if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) { tile_flags |= RADEON_DST_TILE_MACRO;
if (reg == RADEON_SRC_PITCH_OFFSET) { if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
DRM_ERROR("Cannot src blit from microtiled surface\n"); if (reg == RADEON_SRC_PITCH_OFFSET) {
r100_cs_dump_packet(p, pkt); DRM_ERROR("Cannot src blit from microtiled surface\n");
return -EINVAL; r100_cs_dump_packet(p, pkt);
return -EINVAL;
}
tile_flags |= RADEON_DST_TILE_MICRO;
} }
tile_flags |= RADEON_DST_TILE_MICRO;
}
tmp |= tile_flags; tmp |= tile_flags;
p->ib->ptr[idx] = (value & 0x3fc00000) | tmp; p->ib->ptr[idx] = (value & 0x3fc00000) | tmp;
} else
p->ib->ptr[idx] = (value & 0xffc00000) | tmp;
return 0; return 0;
} }
...@@ -1625,15 +1629,17 @@ static int r100_packet0_check(struct radeon_cs_parser *p, ...@@ -1625,15 +1629,17 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
r100_cs_dump_packet(p, pkt); r100_cs_dump_packet(p, pkt);
return r; return r;
} }
if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
tile_flags |= RADEON_COLOR_TILE_ENABLE; tile_flags |= RADEON_COLOR_TILE_ENABLE;
if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
tmp = idx_value & ~(0x7 << 16); tmp = idx_value & ~(0x7 << 16);
tmp |= tile_flags; tmp |= tile_flags;
ib[idx] = tmp; ib[idx] = tmp;
} else
ib[idx] = idx_value;
track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
track->cb_dirty = true; track->cb_dirty = true;
......
...@@ -277,14 +277,17 @@ int r200_packet0_check(struct radeon_cs_parser *p, ...@@ -277,14 +277,17 @@ int r200_packet0_check(struct radeon_cs_parser *p,
return r; return r;
} }
if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
tile_flags |= RADEON_COLOR_TILE_ENABLE; if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) tile_flags |= RADEON_COLOR_TILE_ENABLE;
tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
tmp = idx_value & ~(0x7 << 16); tmp = idx_value & ~(0x7 << 16);
tmp |= tile_flags; tmp |= tile_flags;
ib[idx] = tmp; ib[idx] = tmp;
} else
ib[idx] = idx_value;
track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
track->cb_dirty = true; track->cb_dirty = true;
......
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