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Commit ca36f40d authored by Russell King's avatar Russell King
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[ARM] Resurect EBSA110 machine class. 

This fixes build errors in EBSA110, and updates the default
configuration.
parent efe00e6a
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Showing with 419 additions and 345 deletions
arch/arm/Kconfig
View file @ ca36f40d
......@@ -581,7 +581,7 @@ config LEDS_CPU
config ALIGNMENT_TRAP
bool
depends on CPU_32
default y
default y if !ARCH_EBSA110
help
ARM processors can not fetch/store information which is not
naturally aligned on the bus, i.e., a 4 byte fetch must start at an
......
arch/arm/configs/ebsa110_defconfig
View file @ ca36f40d
This diff is collapsed.
arch/arm/mach-ebsa110/io.c
View file @ ca36f40d
......@@ -67,9 +67,9 @@ u8 __readb(void *addr)
u32 ret, a = __isamem_convert_addr(addr);
if ((int)addr & 1)
ret = __raw_getl(a);
ret = __raw_readl(a);
else
ret = __raw_getb(a);
ret = __raw_readb(a);
return ret;
}
......@@ -80,7 +80,7 @@ u16 __readw(void *addr)
if ((int)addr & 1)
BUG();
return __raw_getw(a);
return __raw_readw(a);
}
u32 __readl(void *addr)
......@@ -90,8 +90,8 @@ u32 __readl(void *addr)
if ((int)addr & 3)
BUG();
ret = __raw_getw(a);
ret |= __raw_getw(a + 4) << 16;
ret = __raw_readw(a);
ret |= __raw_readw(a + 4) << 16;
return ret;
}
......@@ -104,9 +104,9 @@ void __writeb(u8 val, void *addr)
u32 a = __isamem_convert_addr(addr);
if ((int)addr & 1)
__raw_putl(val, a);
__raw_writel(val, a);
else
__raw_putb(val, a);
__raw_writeb(val, a);
}
void __writew(u16 val, void *addr)
......@@ -116,7 +116,7 @@ void __writew(u16 val, void *addr)
if ((int)addr & 1)
BUG();
__raw_putw(val, a);
__raw_writew(val, a);
}
void __writel(u32 val, void *addr)
......@@ -126,8 +126,8 @@ void __writel(u32 val, void *addr)
if ((int)addr & 3)
BUG();
__raw_putw(val, a);
__raw_putw(val >> 16, a + 4);
__raw_writew(val, a);
__raw_writew(val >> 16, a + 4);
}
EXPORT_SYMBOL(__writeb);
......@@ -147,7 +147,7 @@ u8 __inb(int port)
* The SuperIO registers use sane addressing techniques...
*/
if (SUPERIO_PORT(port))
ret = __raw_getb(ISAIO_BASE + (port << 2));
ret = __raw_readb(ISAIO_BASE + (port << 2));
else {
u32 a = ISAIO_BASE + ((port & ~1) << 1);
......@@ -155,9 +155,9 @@ u8 __inb(int port)
* Shame nothing else does
*/
if (port & 1)
ret = __raw_getl(a);
ret = __raw_readl(a);
else
ret = __raw_getb(a);
ret = __raw_readb(a);
}
return ret;
}
......@@ -170,7 +170,7 @@ u16 __inw(int port)
* The SuperIO registers use sane addressing techniques...
*/
if (SUPERIO_PORT(port))
ret = __raw_getw(ISAIO_BASE + (port << 2));
ret = __raw_readw(ISAIO_BASE + (port << 2));
else {
u32 a = ISAIO_BASE + ((port & ~1) << 1);
......@@ -180,7 +180,7 @@ u16 __inw(int port)
if (port & 1)
BUG();
ret = __raw_getw(a);
ret = __raw_readw(a);
}
return ret;
}
......@@ -201,7 +201,7 @@ void __outb(u8 val, int port)
* The SuperIO registers use sane addressing techniques...
*/
if (SUPERIO_PORT(port))
__raw_putb(val, ISAIO_BASE + (port << 2));
__raw_writeb(val, ISAIO_BASE + (port << 2));
else {
u32 a = ISAIO_BASE + ((port & ~1) << 1);
......@@ -209,9 +209,9 @@ void __outb(u8 val, int port)
* Shame nothing else does
*/
if (port & 1)
__raw_putl(val, a);
__raw_writel(val, a);
else
__raw_putb(val, a);
__raw_writeb(val, a);
}
}
......@@ -230,7 +230,7 @@ void __outw(u16 val, int port)
BUG();
}
__raw_putw(val, ISAIO_BASE + off);
__raw_writew(val, ISAIO_BASE + off);
}
void __outl(u32 val, int port)
......
drivers/net/arm/am79c961a.c
View file @ ca36f40d
......@@ -53,25 +53,31 @@ static const char version[] =
#ifdef __arm__
static void write_rreg(u_long base, u_int reg, u_int val)
{
__asm__("str%?h %1, [%2] @ NET_RAP
str%?h %0, [%2, #-4] @ NET_RDP
" : : "r" (val), "r" (reg), "r" (ISAIO_BASE + 0x0464));
__asm__(
"str%?h %1, [%2] @ NET_RAP\n\t"
"str%?h %0, [%2, #-4] @ NET_RDP"
:
: "r" (val), "r" (reg), "r" (ISAIO_BASE + 0x0464));
}
static inline unsigned short read_rreg(u_long base_addr, u_int reg)
{
unsigned short v;
__asm__("str%?h %1, [%2] @ NET_RAP
ldr%?h %0, [%2, #-4] @ NET_RDP
" : "=r" (v): "r" (reg), "r" (ISAIO_BASE + 0x0464));
__asm__(
"str%?h %1, [%2] @ NET_RAP\n\t"
"ldr%?h %0, [%2, #-4] @ NET_RDP"
: "=r" (v)
: "r" (reg), "r" (ISAIO_BASE + 0x0464));
return v;
}
static inline void write_ireg(u_long base, u_int reg, u_int val)
{
__asm__("str%?h %1, [%2] @ NET_RAP
str%?h %0, [%2, #8] @ NET_IDP
" : : "r" (val), "r" (reg), "r" (ISAIO_BASE + 0x0464));
__asm__(
"str%?h %1, [%2] @ NET_RAP\n\t"
"str%?h %0, [%2, #8] @ NET_IDP"
:
: "r" (val), "r" (reg), "r" (ISAIO_BASE + 0x0464));
}
static inline unsigned short read_ireg(u_long base_addr, u_int reg)
......@@ -101,16 +107,16 @@ am_writebuffer(struct net_device *dev, u_int offset, unsigned char *buf, unsigne
}
while (length > 8) {
unsigned int tmp, tmp2;
__asm__ __volatile__("
ldm%?ia %1!, {%2, %3}
str%?h %2, [%0], #4
mov%? %2, %2, lsr #16
str%?h %2, [%0], #4
str%?h %3, [%0], #4
mov%? %3, %3, lsr #16
str%?h %3, [%0], #4
" : "=&r" (offset), "=&r" (buf), "=r" (tmp), "=r" (tmp2)
: "0" (offset), "1" (buf));
__asm__ __volatile__(
"ldm%?ia %1!, {%2, %3}\n\t"
"str%?h %2, [%0], #4\n\t"
"mov%? %2, %2, lsr #16\n\t"
"str%?h %2, [%0], #4\n\t"
"str%?h %3, [%0], #4\n\t"
"mov%? %3, %3, lsr #16\n\t"
"str%?h %3, [%0], #4"
: "=&r" (offset), "=&r" (buf), "=r" (tmp), "=r" (tmp2)
: "0" (offset), "1" (buf));
length -= 8;
}
while (length > 0) {
......@@ -128,36 +134,36 @@ am_readbuffer(struct net_device *dev, u_int offset, unsigned char *buf, unsigned
length = (length + 1) & ~1;
if ((int)buf & 2) {
unsigned int tmp;
__asm__ __volatile__("
ldr%?h %2, [%0], #4
str%?b %2, [%1], #1
mov%? %2, %2, lsr #8
str%?b %2, [%1], #1
" : "=&r" (offset), "=&r" (buf), "=r" (tmp): "0" (offset), "1" (buf));
__asm__ __volatile__(
"ldr%?h %2, [%0], #4\n\t"
"str%?b %2, [%1], #1\n\t"
"mov%? %2, %2, lsr #8\n\t"
"str%?b %2, [%1], #1"
: "=&r" (offset), "=&r" (buf), "=r" (tmp): "0" (offset), "1" (buf));
length -= 2;
}
while (length > 8) {
unsigned int tmp, tmp2, tmp3;
__asm__ __volatile__("
ldr%?h %2, [%0], #4
ldr%?h %3, [%0], #4
orr%? %2, %2, %3, lsl #16
ldr%?h %3, [%0], #4
ldr%?h %4, [%0], #4
orr%? %3, %3, %4, lsl #16
stm%?ia %1!, {%2, %3}
" : "=&r" (offset), "=&r" (buf), "=r" (tmp), "=r" (tmp2), "=r" (tmp3)
: "0" (offset), "1" (buf));
__asm__ __volatile__(
"ldr%?h %2, [%0], #4\n\t"
"ldr%?h %3, [%0], #4\n\t"
"orr%? %2, %2, %3, lsl #16\n\t"
"ldr%?h %3, [%0], #4\n\t"
"ldr%?h %4, [%0], #4\n\t"
"orr%? %3, %3, %4, lsl #16\n\t"
"stm%?ia %1!, {%2, %3}"
: "=&r" (offset), "=&r" (buf), "=r" (tmp), "=r" (tmp2), "=r" (tmp3)
: "0" (offset), "1" (buf));
length -= 8;
}
while (length > 0) {
unsigned int tmp;
__asm__ __volatile__("
ldr%?h %2, [%0], #4
str%?b %2, [%1], #1
mov%? %2, %2, lsr #8
str%?b %2, [%1], #1
" : "=&r" (offset), "=&r" (buf), "=r" (tmp) : "0" (offset), "1" (buf));
__asm__ __volatile__(
"ldr%?h %2, [%0], #4\n\t"
"str%?b %2, [%1], #1\n\t"
"mov%? %2, %2, lsr #8\n\t"
"str%?b %2, [%1], #1"
: "=&r" (offset), "=&r" (buf), "=r" (tmp) : "0" (offset), "1" (buf));
length -= 2;
}
}
......@@ -618,6 +624,7 @@ am79c961_interrupt(int irq, void *dev_id, struct pt_regs *regs)
if (status & CSR0_CERR) {
handled = 1;
mod_timer(&priv->timer, jiffies);
}
} while (--n && status & (CSR0_RINT | CSR0_TINT));
return IRQ_RETVAL(handled);
......
include/asm-arm/arch-ebsa110/io.h
View file @ ca36f40d
......@@ -50,7 +50,7 @@ void __writel(u32 val, void *addr);
#define writew(v,b) __writew(v,b)
#define writel(v,b) __writel(v,b)
#define __arch_ioremap(cookie,sz,c) ((void *)(cookie))
#define __arch_ioremap(cookie,sz,c,a) ((void *)(cookie))
#define __arch_iounmap(cookie) do { } while (0)
#endif
include/asm-arm/arch-ebsa110/system.h
View file @ ca36f40d
......@@ -25,13 +25,13 @@ static inline void arch_idle(void)
const char *irq_stat = (char *)0xff000000;
/* disable clock switching */
asm volatile ("mcr%? p15, 0, ip, c15, c2, 2");
asm volatile ("mcr p15, 0, ip, c15, c2, 2" : : : "cc");
/* wait for an interrupt to occur */
while (!*irq_stat);
/* enable clock switching */
asm volatile ("mcr%? p15, 0, ip, c15, c1, 2");
asm volatile ("mcr p15, 0, ip, c15, c1, 2" : : : "cc");
}
#define arch_reset(mode) cpu_reset(0x80000000)
......
include/asm-arm/arch-ebsa110/timex.h
View file @ ca36f40d
......@@ -15,5 +15,5 @@
* This is therefore not used to calculate the
* divisor.
*/
//#define CLOCK_TICK_RATE 2000000
#define CLOCK_TICK_RATE 47894000
include/asm-arm/arch-ebsa110/uncompress.h
View file @ ca36f40d
......@@ -13,26 +13,26 @@
*/
static void puts(const char *s)
{
__asm__ __volatile__("
ldrb %0, [%2], #1
teq %0, #0
beq 3f
1: strb %0, [%3]
2: ldrb %1, [%3, #0x14]
and %1, %1, #0x60
teq %1, #0x60
bne 2b
teq %0, #'\n'
moveq %0, #'\r'
beq 1b
ldrb %0, [%2], #1
teq %0, #0
bne 1b
3: ldrb %1, [%3, #0x14]
and %1, %1, #0x60
teq %1, #0x60
bne 3b
" : : "r" (0), "r" (0), "r" (s), "r" (0xf0000be0) : "cc");
__asm__ __volatile__(
"ldrb %0, [%2], #1\n"
" teq %0, #0\n"
" beq 3f\n"
"1: strb %0, [%3]\n"
"2: ldrb %1, [%3, #0x14]\n"
" and %1, %1, #0x60\n"
" teq %1, #0x60\n"
" bne 2b\n"
" teq %0, #'\n'\n"
" moveq %0, #'\r'\n"
" beq 1b\n"
" ldrb %0, [%2], #1\n"
" teq %0, #0\n"
" bne 1b\n"
"3: ldrb %1, [%3, #0x14]\n"
" and %1, %1, #0x60\n"
" teq %1, #0x60\n"
" bne 3b"
: : "r" (0), "r" (0), "r" (s), "r" (0xf0000be0) : "cc");
}
/*
......
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