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Commit cb44ec31 authored by Scott Feldman's avatar Scott Feldman Committed by Jeff Garzik
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[netdrvr] e100 version 3 (complete rewrite)

parent 02a38ad0
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Showing with 2306 additions and 9247 deletions
drivers/net/Kconfig
View file @ cb44ec31
......@@ -1341,8 +1341,9 @@ config EEPRO100_PIO
say N.
config E100
tristate "EtherExpressPro/100 support (e100, Alternate Intel driver)"
tristate "Intel(R) PRO/100+ support"
depends on NET_PCI && PCI
select MII
---help---
This driver supports Intel(R) PRO/100 family of adapters, which
includes:
......@@ -1415,6 +1416,10 @@ config E100
<file:Documentation/networking/net-modules.txt>. The module
will be called e100.
config E100_NAPI
bool "Use Rx Polling (NAPI)"
depends on E100
config LNE390
tristate "Mylex EISA LNE390A/B support (EXPERIMENTAL)"
depends on NET_PCI && EISA && EXPERIMENTAL
......
drivers/net/Makefile
View file @ cb44ec31
......@@ -8,7 +8,6 @@ ifeq ($(CONFIG_ISDN_PPP),y)
obj-$(CONFIG_ISDN) += slhc.o
endif
obj-$(CONFIG_E100) += e100/
obj-$(CONFIG_E1000) += e1000/
obj-$(CONFIG_IXGB) += ixgb/
obj-$(CONFIG_BONDING) += bonding/
......@@ -39,6 +38,7 @@ obj-$(CONFIG_TYPHOON) += typhoon.o
obj-$(CONFIG_NE2K_PCI) += ne2k-pci.o 8390.o
obj-$(CONFIG_PCNET32) += pcnet32.o
obj-$(CONFIG_EEPRO100) += eepro100.o
obj-$(CONFIG_E100) += e100.o
obj-$(CONFIG_TLAN) += tlan.o
obj-$(CONFIG_EPIC100) += epic100.o
obj-$(CONFIG_SIS190) += sis190.o
......
drivers/net/e100.c 0 → 100644
View file @ cb44ec31
/*******************************************************************************
Copyright(c) 1999 - 2003 Intel Corporation. All rights reserved.
This program is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the Free
Software Foundation; either version 2 of the License, or (at your option)
any later version.
This program is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
this program; if not, write to the Free Software Foundation, Inc., 59
Temple Place - Suite 330, Boston, MA 02111-1307, USA.
The full GNU General Public License is included in this distribution in the
file called LICENSE.
Contact Information:
Linux NICS <linux.nics@intel.com>
Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
*******************************************************************************/
/*
* e100.c: Intel(R) PRO/100 ethernet driver
*
* (Re)written 2003 by scott.feldman@intel.com. Based loosely on
* original e100 driver, but better described as a munging of
* e100, e1000, eepro100, tg3, 8139cp, and other drivers.
*
* References:
* Intel 8255x 10/100 Mbps Ethernet Controller Family,
* Open Source Software Developers Manual,
* http://sourceforge.net/projects/e1000
*
*
* Theory of Operation
*
* I. General
*
* The driver supports Intel(R) 10/100 Mbps PCI Fast Ethernet
* controller family, which includes the 82557, 82558, 82559, 82550,
* 82551, and 82562 devices. 82558 and greater controllers
* integrate the Intel 82555 PHY. The controllers are used in
* server and client network interface cards, as well as in
* LAN-On-Motherboard (LOM), CardBus, MiniPCI, and ICHx
* configurations. 8255x supports a 32-bit linear addressing
* mode and operates at 33Mhz PCI clock rate.
*
* II. Driver Operation
*
* Memory-mapped mode is used exclusively to access the device's
* shared-memory structure, the Control/Status Registers (CSR). All
* setup, configuration, and control of the device, including queuing
* of Tx, Rx, and configuration commands is through the CSR.
* cmd_lock serializes accesses to the CSR command register. cb_lock
* protects the shared Command Block List (CBL).
*
* 8255x is highly MII-compliant and all access to the PHY go
* through the Management Data Interface (MDI). Consequently, the
* driver leverages the mii.c library shared with other MII-compliant
* devices.
*
* Big- and Little-Endian byte order as well as 32- and 64-bit
* archs are supported. Weak-ordered memory and non-cache-coherent
* archs are supported.
*
* III. Transmit
*
* A Tx skb is mapped and hangs off of a TCB. TCBs are linked
* together in a fixed-size ring (CBL) thus forming the flexible mode
* memory structure. A TCB marked with the suspend-bit indicates
* the end of the ring. The last TCB processed suspends the
* controller, and the controller can be restarted by issue a CU
* resume command to continue from the suspend point, or a CU start
* command to start at a given position in the ring.
*
* Non-Tx commands (config, multicast setup, etc) are linked
* into the CBL ring along with Tx commands. The common structure
* used for both Tx and non-Tx commands is the Command Block (CB).
*
* cb_to_use is the next CB to use for queuing a command; cb_to_clean
* is the next CB to check for completion; cb_to_send is the first
* CB to start on in case of a previous failure to resume. CB clean
* up happens in interrupt context in response to a CU interrupt, or
* in dev->poll in the case where NAPI is enabled. cbs_avail keeps
* track of number of free CB resources available.
*
* Hardware padding of short packets to minimum packet size is
* enabled. 82557 pads with 7Eh, while the later controllers pad
* with 00h.
*
* IV. Recieve
*
* The Receive Frame Area (RFA) comprises a ring of Receive Frame
* Descriptors (RFD) + data buffer, thus forming the simplified mode
* memory structure. Rx skbs are allocated to contain both the RFD
* and the data buffer, but the RFD is pulled off before the skb is
* indicated. The data buffer is aligned such that encapsulated
* protocol headers are u32-aligned. Since the RFD is part of the
* mapped shared memory, and completion status is contained within
* the RFD, the RFD must be dma_sync'ed to maintain a consistent
* view from software and hardware.
*
* Under typical operation, the receive unit (RU) is start once,
* and the controller happily fills RFDs as frames arrive. If
* replacement RFDs cannot be allocated, or the RU goes non-active,
* the RU must be restarted. Frame arrival generates an interrupt,
* and Rx indication and re-allocation happen in the same context,
* therefore no locking is required. If NAPI is enabled, this work
* happens in dev->poll. A software-generated interrupt is gen-
* erated from the watchdog to recover from a failed allocation
* senario where all Rx resources have been indicated and none re-
* placed.
*
* V. Miscellaneous
*
* VLAN offload support of tagging, stripping and filtering is not
* supported, but driver will accommodate the extra 4-byte VLAN tag
* for processing by upper layers. Tx/Rx Checksum offloading is not
* supported. Tx Scatter/Gather is not supported. Jumbo Frames is
* not supported.
*
* NAPI support is enabled with CONFIG_E100_NAPI.
*
* MagicPacket(tm) WoL support is enabled/disabled via ethtool.
*
* Thanks to JC (jchapman@katalix.com) for helping with
* testing/troubleshooting the development driver.
*/
#include <linux/config.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/list.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/mii.h>
#include <linux/if_vlan.h>
#include <linux/skbuff.h>
#include <linux/ethtool.h>
#include <asm/unaligned.h>
#define DRV_NAME "e100"
#define DRV_VERSION "3.0.9_dev"
#define DRV_DESCRIPTION "Intel(R) PRO/100 Network Driver"
#define DRV_COPYRIGHT "Copyright(c) 1999-2003 Intel Corporation"
#define PFX DRV_NAME ": "
#define E100_WATCHDOG_PERIOD 2 * HZ
#define E100_NAPI_WEIGHT 16
MODULE_DESCRIPTION(DRV_DESCRIPTION);
MODULE_AUTHOR(DRV_COPYRIGHT);
MODULE_LICENSE("GPL");
static int debug = 3;
MODULE_PARM(debug, "i");
MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
#define DPRINTK(nlevel, klevel, fmt, args...) \
(void)((NETIF_MSG_##nlevel & nic->msg_enable) && \
printk(KERN_##klevel PFX "%s: %s: " fmt, nic->netdev->name, \
__FUNCTION__ , ## args))
#define INTEL_8255X_ETHERNET_DEVICE(device_id, ich) {\
PCI_VENDOR_ID_INTEL, device_id, PCI_ANY_ID, PCI_ANY_ID, \
PCI_CLASS_NETWORK_ETHERNET << 8, 0xFFFF00, ich }
static struct pci_device_id e100_id_table[] = {
INTEL_8255X_ETHERNET_DEVICE(0x1029, 0),
INTEL_8255X_ETHERNET_DEVICE(0x1030, 0),
INTEL_8255X_ETHERNET_DEVICE(0x1031, 3),
INTEL_8255X_ETHERNET_DEVICE(0x1032, 3),
INTEL_8255X_ETHERNET_DEVICE(0x1033, 3),
INTEL_8255X_ETHERNET_DEVICE(0x1034, 3),
INTEL_8255X_ETHERNET_DEVICE(0x1038, 3),
INTEL_8255X_ETHERNET_DEVICE(0x1039, 4),
INTEL_8255X_ETHERNET_DEVICE(0x103A, 4),
INTEL_8255X_ETHERNET_DEVICE(0x103B, 4),
INTEL_8255X_ETHERNET_DEVICE(0x103C, 4),
INTEL_8255X_ETHERNET_DEVICE(0x103D, 4),
INTEL_8255X_ETHERNET_DEVICE(0x103E, 4),
INTEL_8255X_ETHERNET_DEVICE(0x1050, 5),
INTEL_8255X_ETHERNET_DEVICE(0x1051, 5),
INTEL_8255X_ETHERNET_DEVICE(0x1052, 5),
INTEL_8255X_ETHERNET_DEVICE(0x1053, 5),
INTEL_8255X_ETHERNET_DEVICE(0x1054, 5),
INTEL_8255X_ETHERNET_DEVICE(0x1055, 5),
INTEL_8255X_ETHERNET_DEVICE(0x1059, 0),
INTEL_8255X_ETHERNET_DEVICE(0x1209, 0),
INTEL_8255X_ETHERNET_DEVICE(0x1229, 0),
INTEL_8255X_ETHERNET_DEVICE(0x2449, 2),
INTEL_8255X_ETHERNET_DEVICE(0x2459, 2),
INTEL_8255X_ETHERNET_DEVICE(0x245D, 2),
{ 0, }
};
MODULE_DEVICE_TABLE(pci, e100_id_table);
enum mac {
mac_82557_D100_A = 0,
mac_82557_D100_B = 1,
mac_82557_D100_C = 2,
mac_82558_D101_A4 = 4,
mac_82558_D101_B0 = 5,
mac_82559_D101M = 8,
mac_82559_D101S = 9,
mac_82550_D102 = 12,
mac_82550_D102_C = 13,
mac_82550_D102_E = 15,
mac_unknown = 0xFF,
};
enum phy {
phy_100a = 0x000003E0,
phy_100c = 0x035002A8,
phy_82555_tx = 0x015002A8,
phy_nsc_tx = 0x5C002000,
phy_82562_et = 0x033002A8,
phy_82562_em = 0x032002A8,
phy_82562_eh = 0x017002A8,
phy_unknown = 0xFFFFFFFF,
};
/* CSR (Control/Status Registers) */
struct csr {
struct {
u8 status;
u8 stat_ack;
u8 cmd_lo;
u8 cmd_hi;
u32 gen_ptr;
} scb;
u32 port;
u16 flash_ctrl;
u8 eeprom_ctrl_lo;
u8 eeprom_ctrl_hi;
u32 mdi_ctrl;
u32 rx_dma_count;
};
enum scb_status {
rus_idle = 0x00,
rus_suspended = 0x04,
rus_no_resources = 0x08,
rus_ready = 0x10,
rus_mask = 0x3C,
cus_idle = 0x00,
cus_suspended = 0x40,
cus_active = 0x80,
cus_mask = 0xC0,
};
enum scb_stat_ack {
stat_ack_sw_gen = 0x04,
stat_ack_rnr = 0x10,
stat_ack_cu_idle = 0x20,
stat_ack_frame_rx = 0x40,
stat_ack_cu_cmd_done = 0x80,
stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
};
enum scb_cmd_hi {
irq_mask_none = 0x00,
irq_mask_all = 0x01,
irq_sw_gen = 0x02,
};
enum scb_cmd_lo {
ruc_start = 0x01,
ruc_load_base = 0x06,
cuc_start = 0x10,
cuc_resume = 0x20,
cuc_dump_addr = 0x40,
cuc_dump_stats = 0x50,
cuc_load_base = 0x60,
cuc_dump_reset = 0x70,
};
enum port {
software_reset = 0x0000,
selftest = 0x0001,
selective_reset = 0x0002,
};
enum eeprom_ctrl_lo {
eesk = 0x01,
eecs = 0x02,
eedi = 0x04,
eedo = 0x08,
};
enum mdi_ctrl {
mdi_write = 0x04000000,
mdi_read = 0x08000000,
mdi_ready = 0x10000000,
};
enum eeprom_op {
op_write = 0x05,
op_read = 0x06,
op_ewds = 0x10,
op_ewen = 0x13,
};
enum eeprom_offsets {
eeprom_id = 0x0A,
eeprom_config_asf = 0x0D,
eeprom_smbus_addr = 0x90,
};
enum eeprom_id {
eeprom_id_wol = 0x0020,
};
enum eeprom_config_asf {
eeprom_asf = 0x8000,
eeprom_gcl = 0x4000,
};
enum cb_status {
cb_complete = 0x8000,
cb_ok = 0x2000,
};
enum cb_command {
cb_iaaddr = 0x0001,
cb_config = 0x0002,
cb_multi = 0x0003,
cb_tx = 0x0004,
cb_dump = 0x0006,
cb_tx_sf = 0x0008,
cb_cid = 0x1f00,
cb_i = 0x2000,
cb_s = 0x4000,
cb_el = 0x8000,
};
struct rfd {
u16 status;
u16 command;
u32 link;
u32 rbd;
u16 actual_size;
u16 size;
};
struct rx_list {
struct list_head list;
struct sk_buff *skb;
dma_addr_t dma_addr;
unsigned int length;
};
#if defined(__BIG_ENDIAN_BITFIELD)
#define X(a,b) b,a
#else
#define X(a,b) a,b
#endif
struct config {
/*0*/ u8 X(byte_count:6, pad0:2);
/*1*/ u8 X(X(rx_fifo_limit:4, tx_fifo_limit:3), pad1:1);
/*2*/ u8 adaptive_ifs;
/*3*/ u8 X(X(X(X(mwi_enable:1, type_enable:1), read_align_enable:1),
term_write_cache_line:1), pad3:4);
/*4*/ u8 X(rx_dma_max_count:7, pad4:1);
/*5*/ u8 X(tx_dma_max_count:7, dma_max_count_enable:1);
/*6*/ u8 X(X(X(X(X(X(X(late_scb_update:1, direct_rx_dma:1),
tno_intr:1), cna_intr:1), standard_tcb:1), standard_stat_counter:1),
rx_discard_overruns:1), rx_save_bad_frames:1);
/*7*/ u8 X(X(X(X(X(rx_discard_short_frames:1, tx_underrun_retry:2),
pad7:2), rx_extended_rfd:1), tx_two_frames_in_fifo:1),
tx_dynamic_tbd:1);
/*8*/ u8 X(X(mii_mode:1, pad8:6), csma_disabled:1);
/*9*/ u8 X(X(X(X(X(rx_tcpudp_checksum:1, pad9:3), vlan_arp_tco:1),
link_status_wake:1), arp_wake:1), mcmatch_wake:1);
/*10*/ u8 X(X(X(pad10:3, no_source_addr_insertion:1), preamble_length:2),
loopback:2);
/*11*/ u8 X(linear_priority:3, pad11:5);
/*12*/ u8 X(X(linear_priority_mode:1, pad12:3), ifs:4);
/*13*/ u8 ip_addr_lo;
/*14*/ u8 ip_addr_hi;
/*15*/ u8 X(X(X(X(X(X(X(promiscuous_mode:1, broadcast_disabled:1),
wait_after_win:1), pad15_1:1), ignore_ul_bit:1), crc_16_bit:1),
pad15_2:1), crs_or_cdt:1);
/*16*/ u8 fc_delay_lo;
/*17*/ u8 fc_delay_hi;
/*18*/ u8 X(X(X(X(X(rx_stripping:1, tx_padding:1), rx_crc_transfer:1),
rx_long_ok:1), fc_priority_threshold:3), pad18:1);
/*19*/ u8 X(X(X(X(X(X(X(addr_wake:1, magic_packet_disable:1),
fc_disable:1), fc_restop:1), fc_restart:1), fc_reject:1),
full_duplex_force:1), full_duplex_pin:1);
/*20*/ u8 X(X(X(pad20_1:5, fc_priority_location:1), multi_ia:1), pad20_2:1);
/*21*/ u8 X(X(pad21_1:3, multicast_all:1), pad21_2:4);
/*22*/ u8 X(X(rx_d102_mode:1, rx_vlan_drop:1), pad22:6);
u8 pad_d102[9];
};
#define E100_MAX_MULTICAST_ADDRS 64
struct multi {
u16 count;
u8 addr[E100_MAX_MULTICAST_ADDRS * ETH_ALEN + 2/*pad*/];
};
/* Important: keep total struct u32-aligned */
struct cb {
u16 status;
u16 command;
u32 link;
union {
u8 iaaddr[ETH_ALEN];
struct config config;
struct multi multi;
struct {
u32 tbd_array;
u16 tcb_byte_count;
u8 threshold;
u8 tbd_count;
struct {
u32 buf_addr;
u16 size;
u16 eol;
} tbd;
} tcb;
u32 dump_buffer_addr;
} u;
struct cb *next, *prev;
dma_addr_t dma_addr;
struct sk_buff *skb;
};
enum loopback {
lb_none = 0, lb_mac = 1, lb_phy = 3,
};
struct stats {
u32 tx_good_frames, tx_max_collisions, tx_late_collisions,
tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
tx_multiple_collisions, tx_total_collisions;
u32 rx_good_frames, rx_crc_errors, rx_alignment_errors,
rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
rx_short_frame_errors;
u32 fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
u16 xmt_tco_frames, rcv_tco_frames;
u32 complete;
};
struct mem {
struct {
u32 signature;
u32 result;
} selftest;
struct stats stats;
u8 dump_buf[596];
};
struct param_range {
u32 min;
u32 max;
u32 count;
};
struct params {
struct param_range rfds;
struct param_range cbs;
};
struct nic {
/* Begin: frequently used values: keep adjacent for cache effect */
u32 msg_enable ____cacheline_aligned;
struct net_device *netdev;
struct pci_dev *pdev;
struct list_head rx_list_head ____cacheline_aligned;
struct rx_list *rx_list;
struct rfd blank_rfd;
spinlock_t cb_lock ____cacheline_aligned;
spinlock_t cmd_lock;
struct csr *csr;
enum scb_cmd_lo cuc_cmd;
unsigned int cbs_avail;
struct cb *cbs;
struct cb *cb_to_use;
struct cb *cb_to_send;
struct cb *cb_to_clean;
u16 tx_command;
/* End: frequently used values: keep adjacent for cache effect */
enum {
ich = (1 << 0),
promiscuous = (1 << 1),
multicast_all = (1 << 2),
wol_magic = (1 << 3),
} flags ____cacheline_aligned;
enum mac mac;
enum phy phy;
struct params params;
struct net_device_stats net_stats;
struct timer_list watchdog;
struct timer_list blink_timer;
struct mii_if_info mii;
enum loopback loopback;
struct mem *mem;
dma_addr_t dma_addr;
dma_addr_t cbs_dma_addr;
u8 adaptive_ifs;
u8 tx_threshold;
u32 tx_frames;
u32 tx_collisions;
u32 tx_deferred;
u32 tx_single_collisions;
u32 tx_multiple_collisions;
u32 tx_fc_pause;
u32 tx_tco_frames;
u32 rx_fc_pause;
u32 rx_fc_unsupported;
u32 rx_tco_frames;
u8 rev_id;
u16 leds;
u16 eeprom_wc;
u16 eeprom[256];
u32 pm_state[16];
};
static void e100_get_defaults(struct nic *nic)
{
struct param_range rfds = { .min = 64, .max = 256, .count = 64 };
struct param_range cbs = { .min = 64, .max = 256, .count = 64 };
pci_read_config_byte(nic->pdev, PCI_REVISION_ID, &nic->rev_id);
/* MAC type is encoded as rev ID; exception: ICH is treated as 82559 */
nic->mac = (nic->flags & ich) ? mac_82559_D101M : nic->rev_id;
if(nic->mac == mac_unknown)
nic->mac = mac_82557_D100_A;
nic->params.rfds = rfds;
nic->params.cbs = cbs;
/* Quadwords to DMA into FIFO before starting frame transmit */
nic->tx_threshold = 0xE0;
nic->tx_command = cpu_to_le16(cb_tx | cb_i | cb_tx_sf |
((nic->mac >= mac_82558_D101_A4) ? cb_cid : 0));
/* Template for a freshly allocated RFD */
nic->blank_rfd.status = 0;
nic->blank_rfd.command = cpu_to_le16(cb_el);
nic->blank_rfd.link = 0;
nic->blank_rfd.rbd = 0xFFFFFFFF;
nic->blank_rfd.actual_size = 0;
nic->blank_rfd.size = cpu_to_le16(VLAN_ETH_FRAME_LEN);
}
static inline void e100_write_flush(struct nic *nic)
{
/* Flush previous PCI writes through intermediate bridges
* by doing a benign read */
(void)readb(&nic->csr->scb.status);
}
static inline void e100_enable_irq(struct nic *nic)
{
writeb(irq_mask_none, &nic->csr->scb.cmd_hi);
e100_write_flush(nic);
}
static inline void e100_disable_irq(struct nic *nic)
{
writeb(irq_mask_all, &nic->csr->scb.cmd_hi);
e100_write_flush(nic);
}
static void e100_hw_reset(struct nic *nic)
{
/* Put CU and RU into idle with a selective reset to get
* device off of PCI bus */
writel(selective_reset, &nic->csr->port);
e100_write_flush(nic); udelay(20);
/* Now fully reset device */
writel(software_reset, &nic->csr->port);
e100_write_flush(nic); udelay(20);
/* TCO workaround - 82559 and greater */
if(nic->mac >= mac_82559_D101M) {
/* Issue a redundant CU load base without setting
* general pointer, and without waiting for scb to
* clear. This gets us into post-driver. Finally,
* wait 20 msec for reset to take effect. */
writeb(cuc_load_base, &nic->csr->scb.cmd_lo);
mdelay(20);
}
/* Mask off our interrupt line - it's unmasked after reset */
e100_disable_irq(nic);
}
static int e100_self_test(struct nic *nic)
{
u32 dma_addr = nic->dma_addr + offsetof(struct mem, selftest);
/* Passing the self-test is a pretty good indication
* that the device can DMA to/from host memory */
nic->mem->selftest.signature = 0;
nic->mem->selftest.result = 0xFFFFFFFF;
writel(selftest | dma_addr, &nic->csr->port);
e100_write_flush(nic);
/* Wait 10 msec for self-test to complete */
set_current_state(TASK_UNINTERRUPTIBLE);
schedule_timeout(HZ / 100 + 1);
/* Interrupts are enabled after self-test */
e100_disable_irq(nic);
/* Check results of self-test */
if(nic->mem->selftest.result != 0) {
DPRINTK(HW, ERR, "Self-test failed: result=0x%08X\n",
nic->mem->selftest.result);
return -ETIMEDOUT;
}
if(nic->mem->selftest.signature == 0) {
DPRINTK(HW, ERR, "Self-test failed: timed out\n");
return -ETIMEDOUT;
}
return 0;
}
static void e100_eeprom_write(struct nic *nic, u16 addr_len, u16 addr, u16 data)
{
u32 cmd_addr_data[3];
u8 ctrl;
int i, j;
/* Three cmds: write/erase enable, write data, write/erase disable */
cmd_addr_data[0] = op_ewen << (addr_len - 2);
cmd_addr_data[1] = (((op_write << addr_len) | addr) << 16) | data;
cmd_addr_data[2] = op_ewds << (addr_len - 2);
/* Bit-bang cmds to write word to eeprom */
for(j = 0; j < 3; j++) {
/* Chip select */
writeb(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
e100_write_flush(nic); udelay(4);
for(i = 31; i >= 0; i--) {
ctrl = (cmd_addr_data[j] & (1 << i)) ?
eecs | eedi : eecs;
writeb(ctrl, &nic->csr->eeprom_ctrl_lo);
e100_write_flush(nic); udelay(4);
writeb(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
e100_write_flush(nic); udelay(4);
}
/* Wait 10 msec for cmd to complete */
set_current_state(TASK_UNINTERRUPTIBLE);
schedule_timeout(HZ / 100 + 1);
/* Chip deselect */
writeb(0, &nic->csr->eeprom_ctrl_lo);
e100_write_flush(nic); udelay(4);
}
};
/* General technique stolen from the eepro100 driver - very clever */
static u16 e100_eeprom_read(struct nic *nic, u16 *addr_len, u16 addr)
{
u32 cmd_addr_data;
u16 data = 0;
u8 ctrl;
int i;
cmd_addr_data = ((op_read << *addr_len) | addr) << 16;
/* Chip select */
writeb(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
e100_write_flush(nic); udelay(4);
/* Bit-bang to read word from eeprom */
for(i = 31; i >= 0; i--) {
ctrl = (cmd_addr_data & (1 << i)) ? eecs | eedi : eecs;
writeb(ctrl, &nic->csr->eeprom_ctrl_lo);
e100_write_flush(nic); udelay(4);
writeb(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
e100_write_flush(nic); udelay(4);
/* Eeprom drives a dummy zero to EEDO after receiving
* complete address. Use this to adjust addr_len. */
ctrl = readb(&nic->csr->eeprom_ctrl_lo);
if(!(ctrl & eedo) && i > 16) {
*addr_len -= (i - 16);
i = 17;
}
data = (data << 1) | (ctrl & eedo ? 1 : 0);
}
/* Chip deselect */
writeb(0, &nic->csr->eeprom_ctrl_lo);
e100_write_flush(nic); udelay(4);
return data;
};
/* Load entire EEPROM image into driver cache and validate checksum */
static int e100_eeprom_load(struct nic *nic)
{
u16 addr, addr_len = 8, checksum = 0;
/* Try reading with an 8-bit addr len to discover actual addr len */
e100_eeprom_read(nic, &addr_len, 0);
nic->eeprom_wc = 1 << addr_len;
for(addr = 0; addr < nic->eeprom_wc; addr++) {
nic->eeprom[addr] = e100_eeprom_read(nic, &addr_len, addr);
if(addr < nic->eeprom_wc - 1)
checksum += nic->eeprom[addr];
}
/* The checksum, stored in the last word, is calculated such that
* the sum of words should be 0xBABA */
checksum = 0xBABA - checksum;
if(checksum != nic->eeprom[nic->eeprom_wc - 1]) {
DPRINTK(PROBE, ERR, "EEPROM corrupted\n");
return -EAGAIN;
}
return 0;
}
/* Save (portion of) driver EEPROM cache to device and update checksum */
static int e100_eeprom_save(struct nic *nic, u16 start, u16 count)
{
u16 addr, addr_len = 8, checksum = 0;
/* Try reading with an 8-bit addr len to discover actual addr len */
e100_eeprom_read(nic, &addr_len, 0);
nic->eeprom_wc = 1 << addr_len;
if(start + count >= nic->eeprom_wc)
return -EINVAL;
for(addr = start; addr < start + count; addr++)
e100_eeprom_write(nic, addr_len, addr, nic->eeprom[addr]);
/* The checksum, stored in the last word, is calculated such that
* the sum of words should be 0xBABA */
for(addr = 0; addr < nic->eeprom_wc - 1; addr++)
checksum += nic->eeprom[addr];
nic->eeprom[nic->eeprom_wc - 1] = 0xBABA - checksum;
e100_eeprom_write(nic, addr_len, nic->eeprom_wc - 1, 0xBABA - checksum);
return 0;
}
#define E100_WAIT_SCB_TIMEOUT 40
static inline int e100_exec_cmd(struct nic *nic, u8 cmd, dma_addr_t dma_addr)
{
unsigned long flags;
unsigned int i;
int err = 0;
spin_lock_irqsave(&nic->cmd_lock, flags);
/* Previous command is accepted when SCB clears */
for(i = 0; i < E100_WAIT_SCB_TIMEOUT; i++) {
if(likely(!readb(&nic->csr->scb.cmd_lo)))
break;
cpu_relax();
if(unlikely(i > (E100_WAIT_SCB_TIMEOUT >> 1)))
udelay(5);
}
if(unlikely(i == E100_WAIT_SCB_TIMEOUT)) {
err = -EAGAIN;
goto err_unlock;
}
if(unlikely(cmd != cuc_resume))
writel(dma_addr, &nic->csr->scb.gen_ptr);
writeb(cmd, &nic->csr->scb.cmd_lo);
err_unlock:
spin_unlock_irqrestore(&nic->cmd_lock, flags);
return err;
}
static inline int e100_exec_cb(struct nic *nic, struct sk_buff *skb,
void (*cb_prepare)(struct nic *, struct cb *, struct sk_buff *))
{
struct cb *cb;
unsigned long flags;
int err = 0;
spin_lock_irqsave(&nic->cb_lock, flags);
if(unlikely(!nic->cbs_avail)) {
err = -ENOMEM;
goto err_unlock;
}
cb = nic->cb_to_use;
nic->cb_to_use = cb->next;
nic->cbs_avail--;
cb->skb = skb;
if(unlikely(!nic->cbs_avail))
err = -ENOSPC;
cb_prepare(nic, cb, skb);
/* Order is important otherwise we'll be in a race with h/w:
* set S-bit in current first, then clear S-bit in previous. */
cb->command |= cpu_to_le16(cb_s);
cb->prev->command &= cpu_to_le16(~cb_s);
while(nic->cb_to_send != nic->cb_to_use) {
if(unlikely((err = e100_exec_cmd(nic, nic->cuc_cmd,
nic->cb_to_send->dma_addr)))) {
/* Ok, here's where things get sticky. It's
* possible that we can't schedule the command
* because the controller is too busy, so
* let's just queue the command and try again
* when another command is scheduled. */
break;
} else {
nic->cuc_cmd = cuc_resume;
nic->cb_to_send = nic->cb_to_send->next;
}
}
err_unlock:
spin_unlock_irqrestore(&nic->cb_lock, flags);
return err;
}
static u16 mdio_ctrl(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data)
{
u32 data_out = 0;
unsigned int i;
writel((reg << 16) | (addr << 21) | dir | data, &nic->csr->mdi_ctrl);
for(i = 0; i < 100; i++) {
udelay(20);
if((data_out = readl(&nic->csr->mdi_ctrl)) & mdi_ready)
break;
}
DPRINTK(HW, DEBUG,
"%s:addr=%d, reg=%d, data_in=0x%04X, data_out=0x%04X\n",
dir == mdi_read ? "READ" : "WRITE", addr, reg, data, data_out);
return (u16)data_out;
}
static int mdio_read(struct net_device *netdev, int addr, int reg)
{
return mdio_ctrl(netdev->priv, addr, mdi_read, reg, 0);
}
static void mdio_write(struct net_device *netdev, int addr, int reg, int data)
{
mdio_ctrl(netdev->priv, addr, mdi_write, reg, data);
}
static void e100_configure(struct nic *nic, struct cb *cb, struct sk_buff *skb)
{
struct config *config = &cb->u.config;
u8 *c = (u8 *)config;
cb->command = cpu_to_le16(cb_config);
memset(config, 0, sizeof(struct config));
config->byte_count = 0x16; /* bytes in this struct */
config->rx_fifo_limit = 0x8; /* bytes in FIFO before DMA */
config->direct_rx_dma = 0x1; /* reserved */
config->standard_tcb = 0x1; /* 1=standard, 0=extended */
config->standard_stat_counter = 0x1; /* 1=standard, 0=extended */
config->rx_discard_short_frames = 0x1; /* 1=discard, 0=pass */
config->tx_underrun_retry = 0x3; /* # of underrun retries */
config->mii_mode = 0x1; /* 1=MII mode, 0=503 mode */
config->pad10 = 0x6;
config->no_source_addr_insertion = 0x1; /* 1=no, 0=yes */
config->preamble_length = 0x2; /* 0=1, 1=3, 2=7, 3=15 bytes */
config->ifs = 0x6; /* x16 = inter frame spacing */
config->ip_addr_hi = 0xF2; /* ARP IP filter - not used */
config->pad15_1 = 0x1;
config->pad15_2 = 0x1;
config->crs_or_cdt = 0x0; /* 0=CRS only, 1=CRS or CDT */
config->fc_delay_hi = 0x40; /* time delay for fc frame */
config->tx_padding = 0x1; /* 1=pad short frames */
config->fc_priority_threshold = 0x7; /* 7=priority fc disabled */
config->pad18 = 0x1;
config->full_duplex_pin = 0x1; /* 1=examine FDX# pin */
config->pad20_1 = 0x1F;
config->fc_priority_location = 0x1; /* 1=byte#31, 0=byte#19 */
config->pad21_1 = 0x5;
config->adaptive_ifs = nic->adaptive_ifs;
config->loopback = nic->loopback;
if(nic->mii.force_media && nic->mii.full_duplex)
config->full_duplex_force = 0x1; /* 1=force, 0=auto */
if(nic->flags & promiscuous || nic->loopback) {
config->rx_save_bad_frames = 0x1; /* 1=save, 0=discard */
config->rx_discard_short_frames = 0x0; /* 1=discard, 0=save */
config->promiscuous_mode = 0x1; /* 1=on, 0=off */
}
if(nic->flags & multicast_all)
config->multicast_all = 0x1; /* 1=accept, 0=no */
if(!(nic->flags & wol_magic))
config->magic_packet_disable = 0x1; /* 1=off, 0=on */
if(nic->mac >= mac_82558_D101_A4) {
config->fc_disable = 0x1; /* 1=Tx fc off, 0=Tx fc on */
config->mwi_enable = 0x1; /* 1=enable, 0=disable */
config->standard_tcb = 0x0; /* 1=standard, 0=extended */
config->rx_long_ok = 0x1; /* 1=VLANs ok, 0=standard */
if(nic->mac >= mac_82559_D101M)
config->tno_intr = 0x1; /* TCO stats enable */
else
config->standard_stat_counter = 0x0;
}
DPRINTK(HW, DEBUG, "[00-07]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
c[0], c[1], c[2], c[3], c[4], c[5], c[6], c[7]);
DPRINTK(HW, DEBUG, "[08-15]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
c[8], c[9], c[10], c[11], c[12], c[13], c[14], c[15]);
DPRINTK(HW, DEBUG, "[16-23]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
c[16], c[17], c[18], c[19], c[20], c[21], c[22], c[23]);
}
static void e100_setup_iaaddr(struct nic *nic, struct cb *cb,
struct sk_buff *skb)
{
u8 *dev_addr = nic->netdev->dev_addr;
DPRINTK(HW, DEBUG, "dev_addr=%02X:%02X:%02X:%02X:%02X:%02X\n",
dev_addr[0], dev_addr[1], dev_addr[2],
dev_addr[3], dev_addr[4], dev_addr[5]);
cb->command = cpu_to_le16(cb_iaaddr);
memcpy(cb->u.iaaddr, dev_addr, ETH_ALEN);
}
static void e100_dump(struct nic *nic, struct cb *cb, struct sk_buff *skb)
{
cb->command = cpu_to_le16(cb_dump);
cb->u.dump_buffer_addr = cpu_to_le32(nic->dma_addr +
offsetof(struct mem, dump_buf));
}
#define NCONFIG_AUTO_SWITCH 0x0080
#define MII_NSC_CONG MII_RESV1
#define NSC_CONG_ENABLE 0x0100
#define NSC_CONG_TXREADY 0x0400
#define ADVERTISE_FC_SUPPORTED 0x0400
static int e100_phy_init(struct nic *nic)
{
struct net_device *netdev = nic->netdev;
u32 addr;
u16 bmcr, stat, id_lo, id_hi, cong;
nic->mii.phy_id = 0;
nic->mii.advertising = 0;
nic->mii.phy_id_mask = 0x1F;
nic->mii.reg_num_mask = 0x1F;
nic->mii.dev = netdev;
nic->mii.full_duplex = 0;
nic->mii.force_media = 0;
nic->mii.mdio_read = mdio_read;
nic->mii.mdio_write = mdio_write;
/* Discover phy addr by searching addrs in order {1,0,2,..., 31} */
for(addr = 0; addr < 32; addr++) {
nic->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr;
bmcr = mdio_read(netdev, nic->mii.phy_id, MII_BMCR);
stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
if(!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
break;
}
DPRINTK(HW, DEBUG, "phy_addr = %d\n", nic->mii.phy_id);
if(addr == 32)
return -EAGAIN;
/* Selected the phy and isolate the rest */
for(addr = 0; addr < 32; addr++) {
if(addr != nic->mii.phy_id) {
mdio_write(netdev, addr, MII_BMCR, BMCR_ISOLATE);
} else {
bmcr = mdio_read(netdev, addr, MII_BMCR);
mdio_write(netdev, addr, MII_BMCR,
bmcr & ~BMCR_ISOLATE);
}
}
/* Get phy ID */
id_lo = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID1);
id_hi = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID2);
nic->phy = (u32)id_hi << 16 | (u32)id_lo;
DPRINTK(HW, DEBUG, "phy ID = 0x%08X\n", nic->phy);
/* Handle National tx phy */
if(nic->phy == phy_nsc_tx) {
/* Disable congestion control */
cong = mdio_read(netdev, nic->mii.phy_id, MII_NSC_CONG);
cong |= NSC_CONG_TXREADY;
cong &= ~NSC_CONG_ENABLE;
mdio_write(netdev, nic->mii.phy_id, MII_NSC_CONG, cong);
}
/* enable MDI/MDI-X auto-switching */
if(nic->mac >= mac_82550_D102)
mdio_write(netdev, nic->mii.phy_id, MII_NCONFIG,
NCONFIG_AUTO_SWITCH);
return 0;
}
static int e100_hw_init(struct nic *nic)
{
int err;
e100_hw_reset(nic);
DPRINTK(HW, ERR, "e100_hw_init\n");
if(!in_interrupt() && (err = e100_self_test(nic)))
return err;
if((err = e100_phy_init(nic)))
return err;
if((err = e100_exec_cmd(nic, cuc_load_base, 0)))
return err;
if((err = e100_exec_cmd(nic, ruc_load_base, 0)))
return err;
if((err = e100_exec_cb(nic, NULL, e100_configure)))
return err;
if((err = e100_exec_cb(nic, NULL, e100_setup_iaaddr)))
return err;
if((err = e100_exec_cmd(nic, cuc_dump_addr,
nic->dma_addr + offsetof(struct mem, stats))))
return err;
if((err = e100_exec_cmd(nic, cuc_dump_reset, 0)))
return err;
e100_disable_irq(nic);
return 0;
}
static void e100_multi(struct nic *nic, struct cb *cb, struct sk_buff *skb)
{
struct net_device *netdev = nic->netdev;
struct dev_mc_list *list = netdev->mc_list;
u16 i, count = min(netdev->mc_count, E100_MAX_MULTICAST_ADDRS);
cb->command = cpu_to_le16(cb_multi);
cb->u.multi.count = cpu_to_le16(count * ETH_ALEN);
for(i = 0; list && i < count; i++, list = list->next)
memcpy(&cb->u.multi.addr[i*ETH_ALEN], &list->dmi_addr,
ETH_ALEN);
}
static void e100_set_multicast_list(struct net_device *netdev)
{
struct nic *nic = netdev->priv;
DPRINTK(HW, DEBUG, "mc_count=%d, flags=0x%04X\n",
netdev->mc_count, netdev->flags);
if(netdev->flags & IFF_PROMISC)
nic->flags |= promiscuous;
else
nic->flags &= ~promiscuous;
if(netdev->flags & IFF_ALLMULTI ||
netdev->mc_count > E100_MAX_MULTICAST_ADDRS)
nic->flags |= multicast_all;
else
nic->flags &= ~multicast_all;
e100_exec_cb(nic, NULL, e100_configure);
e100_exec_cb(nic, NULL, e100_multi);
}
static void e100_update_stats(struct nic *nic)
{
struct net_device_stats *ns = &nic->net_stats;
struct stats *s = &nic->mem->stats;
u32 *complete = (nic->mac < mac_82558_D101_A4) ? &s->fc_xmt_pause :
(nic->mac < mac_82559_D101M) ? (u32 *)&s->xmt_tco_frames :
&s->complete;
/* Device's stats reporting may take several microseconds to
* complete, so where always waiting for results of the
* previous command. */
if(*complete == le32_to_cpu(0x0000A007)) {
*complete = 0;
nic->tx_frames = le32_to_cpu(s->tx_good_frames);
nic->tx_collisions = le32_to_cpu(s->tx_total_collisions);
ns->tx_aborted_errors += le32_to_cpu(s->tx_max_collisions);
ns->tx_window_errors += le32_to_cpu(s->tx_late_collisions);
ns->tx_carrier_errors += le32_to_cpu(s->tx_lost_crs);
ns->tx_fifo_errors += le32_to_cpu(s->tx_underruns);
ns->collisions += nic->tx_collisions;
ns->tx_errors += le32_to_cpu(s->tx_max_collisions) +
le32_to_cpu(s->tx_lost_crs);
ns->rx_dropped += le32_to_cpu(s->rx_resource_errors);
ns->rx_length_errors += le32_to_cpu(s->rx_short_frame_errors);
ns->rx_over_errors += le32_to_cpu(s->rx_resource_errors);
ns->rx_crc_errors += le32_to_cpu(s->rx_crc_errors);
ns->rx_frame_errors += le32_to_cpu(s->rx_alignment_errors);
ns->rx_fifo_errors += le32_to_cpu(s->rx_overrun_errors);
ns->rx_errors += le32_to_cpu(s->rx_crc_errors) +
le32_to_cpu(s->rx_alignment_errors) +
le32_to_cpu(s->rx_short_frame_errors) +
le32_to_cpu(s->rx_cdt_errors);
nic->tx_deferred += le32_to_cpu(s->tx_deferred);
nic->tx_single_collisions +=
le32_to_cpu(s->tx_single_collisions);
nic->tx_multiple_collisions +=
le32_to_cpu(s->tx_multiple_collisions);
if(nic->mac >= mac_82558_D101_A4) {
nic->tx_fc_pause += le32_to_cpu(s->fc_xmt_pause);
nic->rx_fc_pause += le32_to_cpu(s->fc_rcv_pause);
nic->rx_fc_unsupported +=
le32_to_cpu(s->fc_rcv_unsupported);
if(nic->mac >= mac_82559_D101M) {
nic->tx_tco_frames +=
le16_to_cpu(s->xmt_tco_frames);
nic->rx_tco_frames +=
le16_to_cpu(s->rcv_tco_frames);
}
}
}
e100_exec_cmd(nic, cuc_dump_reset, 0);
}
static void e100_adjust_adaptive_ifs(struct nic *nic, int speed, int duplex)
{
/* Adjust inter-frame-spacing (IFS) between two transmits if
* we're getting collisions on a half-duplex connection. */
if(duplex == DUPLEX_HALF) {
u32 prev = nic->adaptive_ifs;
u32 min_frames = (speed == SPEED_100) ? 1000 : 100;
if((nic->tx_frames / 32 < nic->tx_collisions) &&
(nic->tx_frames > min_frames)) {
if(nic->adaptive_ifs < 60)
nic->adaptive_ifs += 5;
} else if (nic->tx_frames < min_frames) {
if(nic->adaptive_ifs >= 5)
nic->adaptive_ifs -= 5;
}
if(nic->adaptive_ifs != prev)
e100_exec_cb(nic, NULL, e100_configure);
}
}
static void e100_watchdog(unsigned long data)
{
struct nic *nic = (struct nic *)data;
struct ethtool_cmd cmd;
DPRINTK(TIMER, DEBUG, "right now = %ld\n", jiffies);
/* mii library handles link maintenance tasks */
mii_ethtool_gset(&nic->mii, &cmd);
if(mii_link_ok(&nic->mii) && !netif_carrier_ok(nic->netdev)) {
DPRINTK(LINK, INFO, "link up, %sMbps, %s-duplex\n",
cmd.speed == SPEED_100 ? "100" : "10",
cmd.duplex == DUPLEX_FULL ? "full" : "half");
} else if(!mii_link_ok(&nic->mii) && netif_carrier_ok(nic->netdev)) {
DPRINTK(LINK, INFO, "link down\n");
}
mii_check_link(&nic->mii);
/* Software generated interrupt to recover from (rare) Rx
* allocation failure */
writeb(irq_sw_gen, &nic->csr->scb.cmd_hi);
e100_write_flush(nic);
e100_update_stats(nic);
e100_adjust_adaptive_ifs(nic, cmd.speed, cmd.duplex);
if(nic->mac <= mac_82557_D100_C)
/* Issue a multicast command to workaround a 557 lock up */
e100_set_multicast_list(nic->netdev);
mod_timer(&nic->watchdog, jiffies + E100_WATCHDOG_PERIOD);
}
static inline void e100_xmit_prepare(struct nic *nic, struct cb *cb,
struct sk_buff *skb)
{
cb->command = nic->tx_command;
cb->u.tcb.tbd_array = cb->dma_addr + offsetof(struct cb, u.tcb.tbd);
cb->u.tcb.tcb_byte_count = 0;
cb->u.tcb.threshold = nic->tx_threshold;
cb->u.tcb.tbd_count = 1;
cb->u.tcb.tbd.buf_addr = cpu_to_le32(pci_map_single(nic->pdev,
skb->data, skb->len, PCI_DMA_TODEVICE));
cb->u.tcb.tbd.size = cpu_to_le16(skb->len);
}
static int e100_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
{
struct nic *nic = netdev->priv;
int err = e100_exec_cb(nic, skb, e100_xmit_prepare);
switch(err) {
case -ENOSPC:
/* We queued the skb, but now we're out of space, so
* stop the queue before we completely run out. */
netif_stop_queue(netdev);
break;
case -ENOMEM:
/* This is a hard error - log it. */
DPRINTK(TX_ERR, DEBUG, "Out of Tx resources, returning skb\n");
netif_stop_queue(netdev);
return 1;
}
netdev->trans_start = jiffies;
return 0;
}
static inline int e100_tx_clean(struct nic *nic)
{
struct cb *cb;
int tx_cleaned = 0;
spin_lock(&nic->cb_lock);
DPRINTK(TX_DONE, DEBUG, "cb->status = 0x%04X\n",
nic->cb_to_clean->status);
/* Clean CBs marked complete */
for(cb = nic->cb_to_clean;
cb->status & cpu_to_le16(cb_complete);
cb = nic->cb_to_clean = cb->next) {
if(likely(cb->skb != NULL)) {
nic->net_stats.tx_packets++;
nic->net_stats.tx_bytes += cb->skb->len;
pci_unmap_single(nic->pdev,
le32_to_cpu(cb->u.tcb.tbd.buf_addr),
le16_to_cpu(cb->u.tcb.tbd.size),
PCI_DMA_TODEVICE);
dev_kfree_skb_any(cb->skb);
tx_cleaned = 1;
}
cb->status = 0;
nic->cbs_avail++;
}
spin_unlock(&nic->cb_lock);
/* Recover from running out of Tx resources in xmit_frame */
if(unlikely(tx_cleaned && netif_queue_stopped(nic->netdev)))
netif_wake_queue(nic->netdev);
return tx_cleaned;
}
static void e100_clean_cbs(struct nic *nic, int free_mem)
{
if(nic->cbs) {
while(nic->cb_to_clean != nic->cb_to_use) {
struct cb *cb = nic->cb_to_clean;
if(cb->skb) {
pci_unmap_single(nic->pdev,
le32_to_cpu(cb->u.tcb.tbd.buf_addr),
le16_to_cpu(cb->u.tcb.tbd.size),
PCI_DMA_TODEVICE);
dev_kfree_skb(cb->skb);
}
nic->cb_to_clean = nic->cb_to_clean->next;
}
nic->cbs_avail = nic->params.cbs.count;
if(free_mem) {
pci_free_consistent(nic->pdev,
sizeof(struct cb) * nic->params.cbs.count,
nic->cbs, nic->cbs_dma_addr);
nic->cbs = NULL;
nic->cbs_avail = 0;
}
}
nic->cuc_cmd = cuc_start;
nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean =
nic->cbs;
}
static int e100_alloc_cbs(struct nic *nic)
{
struct cb *cb;
unsigned int i, count = nic->params.cbs.count;
nic->cuc_cmd = cuc_start;
nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = NULL;
nic->cbs_avail = 0;
nic->cbs = pci_alloc_consistent(nic->pdev,
sizeof(struct cb) * count, &nic->cbs_dma_addr);
if(!nic->cbs)
return -ENOMEM;
for(cb = nic->cbs, i = 0; i < count; cb++, i++) {
cb->next = (i + 1 < count) ? cb + 1 : nic->cbs;
cb->prev = (i == 0) ? nic->cbs + count - 1 : cb - 1;
cb->dma_addr = nic->cbs_dma_addr + i * sizeof(struct cb);
cb->link = cpu_to_le32(nic->cbs_dma_addr +
((i+1) % count) * sizeof(struct cb));
}
nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = nic->cbs;
nic->cbs_avail = count;
return 0;
}
static inline void e100_start_receiver(struct nic *nic)
{
/* (Re)start RU if suspended or idle and RFA is fully allocated */
struct rx_list *curr =
list_entry(nic->rx_list_head.next, struct rx_list, list);
if(curr->skb) {
u8 status = readb(&nic->csr->scb.status);
if(unlikely((status & rus_mask) != rus_ready))
e100_exec_cmd(nic, ruc_start, curr->dma_addr);
}
}
static inline int e100_rx_alloc_skb(struct nic *nic, struct rx_list *curr)
{
unsigned int rx_offset = 2; /* u32 align protocol headers */
curr->dma_addr = 0;
curr->length = sizeof(struct rfd) + VLAN_ETH_FRAME_LEN;
if(!(curr->skb = dev_alloc_skb(curr->length + rx_offset)))
return -ENOMEM;
skb_reserve(curr->skb, rx_offset);
curr->skb->dev = nic->netdev;
curr->dma_addr = pci_map_single(nic->pdev, curr->skb->data,
curr->length, PCI_DMA_FROMDEVICE);
return 0;
}
static inline void e100_rx_rfa_add_tail(struct nic *nic, struct rx_list *curr)
{
struct rfd *rfd = (struct rfd *)curr->skb->data;
*rfd = nic->blank_rfd;
pci_dma_sync_single(nic->pdev, curr->dma_addr,
sizeof(struct rfd), PCI_DMA_TODEVICE);
if(likely(curr->list.prev != &nic->rx_list_head)) {
struct rx_list *prev = (struct rx_list *)curr->list.prev;
if(likely(prev->skb != NULL)) {
struct rfd *prev_rfd = (struct rfd *)prev->skb->data;
put_unaligned(cpu_to_le32(curr->dma_addr),
(u32 *)&prev_rfd->link);
prev_rfd->command = 0;
pci_dma_sync_single(nic->pdev, prev->dma_addr,
sizeof(struct rfd), PCI_DMA_TODEVICE);
}
}
}
static inline int e100_rx_indicate(struct nic *nic, struct rx_list *curr,
unsigned int *work_done, unsigned int work_to_do)
{
struct sk_buff *skb = curr->skb;
struct rfd *rfd = (struct rfd *)skb->data;
u16 rfd_status, actual_size;
if(unlikely(work_done && *work_done >= work_to_do))
return -EAGAIN;
/* Need to sync before taking a peek at cb_complete bit */
pci_dma_sync_single(nic->pdev, curr->dma_addr,
sizeof(struct rfd), PCI_DMA_FROMDEVICE);
rfd_status = le16_to_cpu(rfd->status);
DPRINTK(RX_STATUS, DEBUG, "status=0x%04X\n", rfd_status);
/* If data isn't ready, nothing to indicate */
if(unlikely(!(rfd_status & cb_complete)))
return -EAGAIN;
/* Get actual data size */
actual_size = le16_to_cpu(rfd->actual_size) & 0x3FFF;
if(unlikely(actual_size > curr->length - sizeof(struct rfd)))
actual_size = curr->length - sizeof(struct rfd);
/* Get data */
pci_dma_sync_single(nic->pdev, curr->dma_addr,
sizeof(struct rfd) + actual_size,
PCI_DMA_FROMDEVICE);
pci_unmap_single(nic->pdev, curr->dma_addr,
curr->length, PCI_DMA_FROMDEVICE);
/* Pull off the RFD and put the actual data (minus eth hdr) */
skb_reserve(skb, sizeof(struct rfd));
skb_put(skb, actual_size);
skb->protocol = eth_type_trans(skb, nic->netdev);
if(unlikely(!(rfd_status & cb_ok)) ||
actual_size > nic->netdev->mtu + VLAN_ETH_HLEN) {
/* Don't indicate if errors */
dev_kfree_skb_any(skb);
} else {
nic->net_stats.rx_packets++;
nic->net_stats.rx_bytes += actual_size;
nic->netdev->last_rx = jiffies;
#ifdef CONFIG_E100_NAPI
netif_receive_skb(skb);
#else
netif_rx(skb);
#endif
if(work_done)
(*work_done)++;
}
curr->length = 0;
curr->dma_addr = 0;
curr->skb = NULL;
return 0;
}
static inline void e100_rx_clean(struct nic *nic, unsigned int *work_done,
unsigned int work_to_do)
{
struct list_head *list, *tmp;
struct rx_list *curr;
/* Indicate newly arrived packets */
list_for_each(list, &nic->rx_list_head) {
curr = list_entry(list, struct rx_list, list);
if(likely(curr->skb != NULL))
if(e100_rx_indicate(nic, curr, work_done, work_to_do))
break;
}
/* Alloc new skbs to refill list */
list_for_each_safe(list, tmp, &nic->rx_list_head) {
curr = list_entry(list, struct rx_list, list);
if(unlikely(curr->skb != NULL))
break; /* List is full, done */
if(unlikely(e100_rx_alloc_skb(nic, curr)))
break; /* Better luck next time (see watchdog) */
list_del(&curr->list);
list_add_tail(&curr->list, &nic->rx_list_head);
e100_rx_rfa_add_tail(nic, curr);
}
e100_start_receiver(nic);
}
static void e100_rx_clean_list(struct nic *nic)
{
struct list_head *list;
if(!nic->rx_list)
return;
list_for_each(list, &nic->rx_list_head) {
struct rx_list *curr = list_entry(list,
struct rx_list, list);
if(curr->skb) {
pci_unmap_single(nic->pdev, curr->dma_addr,
curr->length, PCI_DMA_FROMDEVICE);
dev_kfree_skb(curr->skb);
}
}
kfree(nic->rx_list);
nic->rx_list = NULL;
}
static int e100_rx_alloc_list(struct nic *nic)
{
struct rx_list *curr;
unsigned int i, count = nic->params.rfds.count;
INIT_LIST_HEAD(&nic->rx_list_head);
if(!(nic->rx_list = kmalloc(sizeof(struct rx_list)*count, GFP_ATOMIC)))
return -ENOMEM;
for(curr = nic->rx_list, i = 0; i < count; curr++, i++) {
if(e100_rx_alloc_skb(nic, curr)) {
e100_rx_clean_list(nic);
return -ENOMEM;
}
list_add_tail(&curr->list, &nic->rx_list_head);
e100_rx_rfa_add_tail(nic, curr);
}
return 0;
}
static irqreturn_t e100_intr(int irq, void *dev_id, struct pt_regs *regs)
{
struct net_device *netdev = dev_id;
struct nic *nic = netdev->priv;
u8 stat_ack = readb(&nic->csr->scb.stat_ack);
DPRINTK(INTR, DEBUG, "stat_ack = 0x%02X\n", stat_ack);
if(stat_ack == 0x00 || /* Not our interurpt */
stat_ack == 0xFF) /* Hardware is ejected (cardbus, hotswap) */
return IRQ_NONE;
/* Ack interrupts */
writeb(stat_ack, &nic->csr->scb.stat_ack);
e100_write_flush(nic);
#ifdef CONFIG_E100_NAPI
e100_disable_irq(nic);
netif_rx_schedule(netdev);
#else
if(stat_ack & stat_ack_rx)
e100_rx_clean(nic, NULL, 0);
if(stat_ack & stat_ack_tx)
e100_tx_clean(nic);
#endif
return IRQ_HANDLED;
}
#ifdef CONFIG_E100_NAPI
static int e100_poll(struct net_device *netdev, int *budget)
{
struct nic *nic = netdev->priv;
unsigned int work_to_do = min(netdev->quota, *budget);
unsigned int work_done = 0;
int tx_cleaned;
e100_rx_clean(nic, &work_done, work_to_do);
tx_cleaned = e100_tx_clean(nic);
/* If no Rx and Tx cleanup work was done, exit polling mode. */
if((!tx_cleaned && (work_done == 0)) || !netif_running(netdev)) {
netif_rx_complete(netdev);
e100_enable_irq(nic);
return 0;
}
*budget -= work_done;
netdev->quota -= work_done;
return 1;
}
#endif
static struct net_device_stats *e100_get_stats(struct net_device *netdev)
{
struct nic *nic = netdev->priv;
return &nic->net_stats;
}
static int e100_set_mac_address(struct net_device *netdev, void *p)
{
struct nic *nic = netdev->priv;
struct sockaddr *addr = p;
if (!is_valid_ether_addr(addr->sa_data))
return -EADDRNOTAVAIL;
memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
e100_exec_cb(nic, NULL, e100_setup_iaaddr);
return 0;
}
static int e100_change_mtu(struct net_device *netdev, int new_mtu)
{
if(new_mtu < ETH_ZLEN || new_mtu > ETH_DATA_LEN)
return -EINVAL;
netdev->mtu = new_mtu;
return 0;
}
static int e100_asf(struct nic *nic)
{
/* ASF can be enabled from eeprom */
return((nic->pdev->device >= 0x1050) && (nic->pdev->device <= 0x1055) &&
(nic->eeprom[eeprom_config_asf] & eeprom_asf) &&
!(nic->eeprom[eeprom_config_asf] & eeprom_gcl) &&
((nic->eeprom[eeprom_smbus_addr] & 0xFF) != 0xFE));
}
static int e100_up(struct nic *nic)
{
int err;
if((err = e100_rx_alloc_list(nic)))
return err;
if((err = e100_alloc_cbs(nic)))
goto err_rx_clean_list;
if((err = e100_hw_init(nic)))
goto err_clean_cbs;
e100_set_multicast_list(nic->netdev);
e100_start_receiver(nic);
netif_start_queue(nic->netdev);
mod_timer(&nic->watchdog, jiffies);
if((err = request_irq(nic->pdev->irq, e100_intr, SA_SHIRQ,
nic->netdev->name, nic->netdev)))
goto err_no_irq;
e100_enable_irq(nic);
return 0;
err_no_irq:
del_timer_sync(&nic->watchdog);
netif_stop_queue(nic->netdev);
err_clean_cbs:
e100_clean_cbs(nic, 1);
err_rx_clean_list:
e100_rx_clean_list(nic);
return err;
}
static void e100_down(struct nic *nic)
{
e100_disable_irq(nic);
free_irq(nic->pdev->irq, nic->netdev);
del_timer_sync(&nic->watchdog);
netif_carrier_off(nic->netdev);
netif_stop_queue(nic->netdev);
e100_clean_cbs(nic, 1);
e100_rx_clean_list(nic);
}
static void e100_tx_timeout(struct net_device *netdev)
{
struct nic *nic = netdev->priv;
DPRINTK(TX_ERR, DEBUG, "scb.status=0x%02X\n",
readb(&nic->csr->scb.status));
e100_down(netdev->priv);
e100_up(netdev->priv);
}
static int e100_loopback_test(struct nic *nic, enum loopback loopback_mode)
{
int err;
struct sk_buff *skb;
struct rx_list *rx;
/* Use driver resources to perform internal MAC or PHY
* loopback test. A single packet is prepared and transmitted
* in loopback mode, and the test passes if the received
* packet compares byte-for-byte to the transmitted packet. */
if((err = e100_rx_alloc_list(nic)))
return err;
if((err = e100_alloc_cbs(nic)))
goto err_clean_rx;
/* ICH PHY loopback is broken so do MAC loopback instead */
if(nic->flags & ich && loopback_mode == lb_phy)
loopback_mode = lb_mac;
nic->loopback = loopback_mode;
if((err = e100_hw_init(nic)))
goto err_loopback_none;
if(loopback_mode == lb_phy)
mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR,
BMCR_LOOPBACK);
e100_start_receiver(nic);
if(!(skb = dev_alloc_skb(ETH_DATA_LEN))) {
err = -ENOMEM;
goto err_loopback_none;
}
skb_put(skb, ETH_DATA_LEN);
memset(skb->data, 0xFF, ETH_DATA_LEN);
e100_xmit_frame(skb, nic->netdev);
set_current_state(TASK_UNINTERRUPTIBLE);
schedule_timeout(HZ / 100 + 1);
rx = list_entry(nic->rx_list_head.next, struct rx_list, list);
if(memcmp(rx->skb->data + sizeof(struct rfd), skb->data, ETH_DATA_LEN))
err = -EAGAIN;
err_loopback_none:
mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR, 0);
nic->loopback = lb_none;
e100_hw_init(nic);
e100_clean_cbs(nic, 1);
err_clean_rx:
e100_rx_clean_list(nic);
return err;
}
#define MII_LED_CONTROL 0x1B
static void e100_blink_led(unsigned long data)
{
struct nic *nic = (struct nic *)data;
enum led_state {
led_on = 0x01,
led_off = 0x04,
led_on_559 = 0x05,
led_on_557 = 0x07,
};
nic->leds = (nic->leds & led_on) ? led_off :
(nic->mac < mac_82559_D101M) ? led_on_557 : led_on_559;
mdio_write(nic->netdev, nic->mii.phy_id, MII_LED_CONTROL, nic->leds);
mod_timer(&nic->blink_timer, jiffies + HZ / 4);
}
static int e100_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
{
struct nic *nic = netdev->priv;
return mii_ethtool_gset(&nic->mii, cmd);
}
static int e100_set_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
{
struct nic *nic = netdev->priv;
return mii_ethtool_sset(&nic->mii, cmd);
}
static void e100_get_drvinfo(struct net_device *netdev,
struct ethtool_drvinfo *info)
{
struct nic *nic = netdev->priv;
strcpy(info->driver, DRV_NAME);
strcpy(info->version, DRV_VERSION);
strcpy(info->fw_version, "N/A");
strcpy(info->bus_info, pci_name(nic->pdev));
}
static int e100_get_regs_len(struct net_device *netdev)
{
struct nic *nic = netdev->priv;
#define E100_PHY_REGS 0x1C
#define E100_REGS_LEN 1 + E100_PHY_REGS + \
sizeof(nic->mem->dump_buf) / sizeof(u32)
return E100_REGS_LEN * sizeof(u32);
}
static void e100_get_regs(struct net_device *netdev,
struct ethtool_regs *regs, void *p)
{
struct nic *nic = netdev->priv;
u32 *buff = p;
int i;
regs->version = (1 << 24) | nic->rev_id;
buff[0] = readb(&nic->csr->scb.cmd_hi) << 24 |
readb(&nic->csr->scb.cmd_lo) << 16 |
readw(&nic->csr->scb.status);
for(i = E100_PHY_REGS; i >= 0; i--)
buff[1 + E100_PHY_REGS - i] =
mdio_read(netdev, nic->mii.phy_id, i);
memset(nic->mem->dump_buf, 0, sizeof(nic->mem->dump_buf));
e100_exec_cb(nic, NULL, e100_dump);
set_current_state(TASK_UNINTERRUPTIBLE);
schedule_timeout(HZ / 100 + 1);
memcpy(&buff[2 + E100_PHY_REGS], nic->mem->dump_buf,
sizeof(nic->mem->dump_buf));
}
static void e100_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
{
struct nic *nic = netdev->priv;
wol->supported = (nic->mac >= mac_82558_D101_A4) ? WAKE_MAGIC : 0;
wol->wolopts = (nic->flags & wol_magic) ? WAKE_MAGIC : 0;
}
static int e100_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
{
struct nic *nic = netdev->priv;
if(wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
return -EOPNOTSUPP;
if(wol->wolopts)
nic->flags |= wol_magic;
else
nic->flags &= ~wol_magic;
pci_enable_wake(nic->pdev, 0, nic->flags & (wol_magic | e100_asf(nic)));
e100_exec_cb(nic, NULL, e100_configure);
return 0;
}
static u32 e100_get_msglevel(struct net_device *netdev)
{
struct nic *nic = netdev->priv;
return nic->msg_enable;
}
static void e100_set_msglevel(struct net_device *netdev, u32 value)
{
struct nic *nic = netdev->priv;
nic->msg_enable = value;
}
static int e100_nway_reset(struct net_device *netdev)
{
struct nic *nic = netdev->priv;
return mii_nway_restart(&nic->mii);
}
static u32 e100_get_link(struct net_device *netdev)
{
struct nic *nic = netdev->priv;
return mii_link_ok(&nic->mii);
}
static int e100_get_eeprom_len(struct net_device *netdev)
{
struct nic *nic = netdev->priv;
return nic->eeprom_wc << 1;
}
#define E100_EEPROM_MAGIC 0x1234
static int e100_get_eeprom(struct net_device *netdev,
struct ethtool_eeprom *eeprom, u8 *bytes)
{
struct nic *nic = netdev->priv;
eeprom->magic = E100_EEPROM_MAGIC;
memcpy(bytes, &((u8 *)nic->eeprom)[eeprom->offset], eeprom->len);
return 0;
}
static int e100_set_eeprom(struct net_device *netdev,
struct ethtool_eeprom *eeprom, u8 *bytes)
{
struct nic *nic = netdev->priv;
if(eeprom->magic != E100_EEPROM_MAGIC)
return -EINVAL;
memcpy(&((u8 *)nic->eeprom)[eeprom->offset], bytes, eeprom->len);
return e100_eeprom_save(nic, eeprom->offset >> 1,
(eeprom->len >> 1) + 1);
}
static void e100_get_ringparam(struct net_device *netdev,
struct ethtool_ringparam *ring)
{
struct nic *nic = netdev->priv;
struct param_range *rfds = &nic->params.rfds;
struct param_range *cbs = &nic->params.cbs;
ring->rx_max_pending = rfds->max;
ring->tx_max_pending = cbs->max;
ring->rx_mini_max_pending = 0;
ring->rx_jumbo_max_pending = 0;
ring->rx_pending = rfds->count;
ring->tx_pending = cbs->count;
ring->rx_mini_pending = 0;
ring->rx_jumbo_pending = 0;
}
static int e100_set_ringparam(struct net_device *netdev,
struct ethtool_ringparam *ring)
{
struct nic *nic = netdev->priv;
struct param_range *rfds = &nic->params.rfds;
struct param_range *cbs = &nic->params.cbs;
if(netif_running(netdev))
e100_down(nic);
rfds->count = max(ring->rx_pending, rfds->min);
rfds->count = min(rfds->count, rfds->max);
cbs->count = max(ring->tx_pending, cbs->min);
cbs->count = min(cbs->count, cbs->max);
if(netif_running(netdev))
e100_up(nic);
return 0;
}
static char e100_gstrings_test[][ETH_GSTRING_LEN] = {
"Link test (on/offline)",
"Eeprom test (on/offline)",
"Self test (offline)",
"Mac loopback (offline)",
"Phy loopback (offline)",
};
#define E100_TEST_LEN sizeof(e100_gstrings_test) / ETH_GSTRING_LEN
static int e100_diag_test_count(struct net_device *netdev)
{
return E100_TEST_LEN;
}
static void e100_diag_test(struct net_device *netdev,
struct ethtool_test *test, u64 *data)
{
struct nic *nic = netdev->priv;
int i;
memset(data, 0, E100_TEST_LEN * sizeof(u64));
data[0] = !mii_link_ok(&nic->mii);
data[1] = e100_eeprom_load(nic);
if(test->flags & ETH_TEST_FL_OFFLINE) {
if(netif_running(netdev))
e100_down(nic);
data[2] = e100_self_test(nic);
data[3] = e100_loopback_test(nic, lb_mac);
data[4] = e100_loopback_test(nic, lb_phy);
if(netif_running(netdev))
e100_up(nic);
}
for(i = 0; i < E100_TEST_LEN; i++)
test->flags |= data[i] ? ETH_TEST_FL_FAILED : 0;
}
static int e100_phys_id(struct net_device *netdev, u32 data)
{
struct nic *nic = netdev->priv;
if(!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
mod_timer(&nic->blink_timer, jiffies);
set_current_state(TASK_INTERRUPTIBLE);
schedule_timeout(data * HZ);
del_timer_sync(&nic->blink_timer);
mdio_write(netdev, nic->mii.phy_id, MII_LED_CONTROL, 0);
return 0;
}
static char e100_gstrings_stats[][ETH_GSTRING_LEN] = {
"rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
"tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
"rx_length_errors", "rx_over_errors", "rx_crc_errors",
"rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
"tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
"tx_heartbeat_errors", "tx_window_errors",
/* device-specific stats */
"tx_deferred", "tx_single_collisions", "tx_multi_collisions",
"tx_flow_control_pause", "rx_flow_control_pause",
"rx_flow_control_unsupported", "tx_tco_packets", "rx_tco_packets",
};
#define E100_NET_STATS_LEN 21
#define E100_STATS_LEN sizeof(e100_gstrings_stats) / ETH_GSTRING_LEN
static int e100_get_stats_count(struct net_device *netdev)
{
return E100_STATS_LEN;
}
static void e100_get_ethtool_stats(struct net_device *netdev,
struct ethtool_stats *stats, u64 *data)
{
struct nic *nic = netdev->priv;
int i;
for(i = 0; i < E100_NET_STATS_LEN; i++)
data[i] = ((unsigned long *)&nic->net_stats)[i];
data[i++] = nic->tx_deferred;
data[i++] = nic->tx_single_collisions;
data[i++] = nic->tx_multiple_collisions;
data[i++] = nic->tx_fc_pause;
data[i++] = nic->rx_fc_pause;
data[i++] = nic->rx_fc_unsupported;
data[i++] = nic->tx_tco_frames;
data[i++] = nic->rx_tco_frames;
}
static void e100_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
{
switch(stringset) {
case ETH_SS_TEST:
memcpy(data, *e100_gstrings_test, sizeof(e100_gstrings_test));
break;
case ETH_SS_STATS:
memcpy(data, *e100_gstrings_stats, sizeof(e100_gstrings_stats));
break;
}
}
static struct ethtool_ops e100_ethtool_ops = {
.get_settings = e100_get_settings,
.set_settings = e100_set_settings,
.get_drvinfo = e100_get_drvinfo,
.get_regs_len = e100_get_regs_len,
.get_regs = e100_get_regs,
.get_wol = e100_get_wol,
.set_wol = e100_set_wol,
.get_msglevel = e100_get_msglevel,
.set_msglevel = e100_set_msglevel,
.nway_reset = e100_nway_reset,
.get_link = e100_get_link,
.get_eeprom_len = e100_get_eeprom_len,
.get_eeprom = e100_get_eeprom,
.set_eeprom = e100_set_eeprom,
.get_ringparam = e100_get_ringparam,
.set_ringparam = e100_set_ringparam,
.self_test_count = e100_diag_test_count,
.self_test = e100_diag_test,
.get_strings = e100_get_strings,
.phys_id = e100_phys_id,
.get_stats_count = e100_get_stats_count,
.get_ethtool_stats = e100_get_ethtool_stats,
};
static int e100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
{
struct nic *nic = netdev->priv;
struct mii_ioctl_data *mii = (struct mii_ioctl_data *)&ifr->ifr_data;
return generic_mii_ioctl(&nic->mii, mii, cmd, NULL);
}
static int e100_alloc(struct nic *nic)
{
nic->mem = pci_alloc_consistent(nic->pdev, sizeof(struct mem),
&nic->dma_addr);
return nic->mem ? 0 : -ENOMEM;
}
static void e100_free(struct nic *nic)
{
if(nic->mem) {
pci_free_consistent(nic->pdev, sizeof(struct mem),
nic->mem, nic->dma_addr);
nic->mem = NULL;
}
}
static int e100_open(struct net_device *netdev)
{
struct nic *nic = netdev->priv;
int err = 0;
netif_carrier_off(netdev);
if((err = e100_up(nic)))
DPRINTK(IFUP, ERR, "Cannot open interface, aborting.\n");
return err;
}
static int e100_close(struct net_device *netdev)
{
e100_down(netdev->priv);
return 0;
}
static int __devinit e100_probe(struct pci_dev *pdev,
const struct pci_device_id *ent)
{
struct net_device *netdev;
struct nic *nic;
int err;
if(!(netdev = alloc_etherdev(sizeof(struct nic)))) {
if(((1 << debug) - 1) & NETIF_MSG_PROBE)
printk(KERN_ERR PFX "Etherdev alloc failed, abort.\n");
return -ENOMEM;
}
netdev->open = e100_open;
netdev->stop = e100_close;
netdev->hard_start_xmit = e100_xmit_frame;
netdev->get_stats = e100_get_stats;
netdev->set_multicast_list = e100_set_multicast_list;
netdev->set_mac_address = e100_set_mac_address;
netdev->change_mtu = e100_change_mtu;
netdev->do_ioctl = e100_do_ioctl;
SET_ETHTOOL_OPS(netdev, &e100_ethtool_ops);
netdev->tx_timeout = e100_tx_timeout;
netdev->watchdog_timeo = E100_WATCHDOG_PERIOD;
#ifdef CONFIG_E100_NAPI
netdev->poll = e100_poll;
netdev->weight = E100_NAPI_WEIGHT;
#endif
nic = netdev->priv;
nic->netdev = netdev;
nic->pdev = pdev;
nic->msg_enable = (1 << debug) - 1;
pci_set_drvdata(pdev, netdev);
if((err = pci_enable_device(pdev))) {
DPRINTK(PROBE, ERR, "Cannot enable PCI device, aborting.\n");
goto err_out_free_dev;
}
if(!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
DPRINTK(PROBE, ERR, "Cannot find proper PCI device "
"base address, aborting.\n");
err = -ENODEV;
goto err_out_disable_pdev;
}
if((err = pci_request_regions(pdev, DRV_NAME))) {
DPRINTK(PROBE, ERR, "Cannot obtain PCI resources, aborting.\n");
goto err_out_disable_pdev;
}
pci_set_master(pdev);
if((err = pci_set_dma_mask(pdev, 0xFFFFFFFFULL))) {
DPRINTK(PROBE, ERR, "No usable DMA configuration, aborting.\n");
goto err_out_free_res;
}
SET_MODULE_OWNER(netdev);
SET_NETDEV_DEV(netdev, &pdev->dev);
nic->csr = ioremap(pci_resource_start(pdev, 0), sizeof(struct csr));
if(!nic->csr) {
DPRINTK(PROBE, ERR, "Cannot map device registers, aborting.\n");
err = -ENOMEM;
goto err_out_free_res;
}
if(ent->driver_data)
nic->flags |= ich;
else
nic->flags &= ~ich;
spin_lock_init(&nic->cb_lock);
spin_lock_init(&nic->cmd_lock);
init_timer(&nic->watchdog);
nic->watchdog.function = e100_watchdog;
nic->watchdog.data = (unsigned long)nic;
init_timer(&nic->blink_timer);
nic->blink_timer.function = e100_blink_led;
nic->blink_timer.data = (unsigned long)nic;
if((err = e100_alloc(nic))) {
DPRINTK(PROBE, ERR, "Cannot alloc driver memory, aborting.\n");
goto err_out_iounmap;
}
e100_get_defaults(nic);
e100_hw_reset(nic);
e100_phy_init(nic);
if((err = e100_eeprom_load(nic)))
goto err_out_free;
((u16 *)nic->netdev->dev_addr)[0] = le16_to_cpu(nic->eeprom[0]);
((u16 *)nic->netdev->dev_addr)[1] = le16_to_cpu(nic->eeprom[1]);
((u16 *)nic->netdev->dev_addr)[2] = le16_to_cpu(nic->eeprom[2]);
if(!is_valid_ether_addr(nic->netdev->dev_addr)) {
DPRINTK(PROBE, ERR, "Invalid MAC address from "
"EEPROM, aborting.\n");
err = -EAGAIN;
goto err_out_free;
}
/* Wol magic packet can be enabled from eeprom */
if((nic->mac >= mac_82558_D101_A4) &&
(nic->eeprom[eeprom_id] & eeprom_id_wol))
nic->flags |= wol_magic;
pci_enable_wake(pdev, 0, nic->flags & (wol_magic | e100_asf(nic)));
if((err = register_netdev(netdev))) {
DPRINTK(PROBE, ERR, "Cannot register net device, aborting.\n");
goto err_out_free;
}
return 0;
err_out_free:
e100_free(nic);
err_out_iounmap:
iounmap(nic->csr);
err_out_free_res:
pci_release_regions(pdev);
err_out_disable_pdev:
pci_disable_device(pdev);
err_out_free_dev:
pci_set_drvdata(pdev, NULL);
free_netdev(netdev);
return err;
}
static void __devexit e100_remove(struct pci_dev *pdev)
{
struct net_device *netdev = pci_get_drvdata(pdev);
if(netdev) {
struct nic *nic = netdev->priv;
unregister_netdev(netdev);
e100_free(nic);
iounmap(nic->csr);
free_netdev(netdev);
pci_release_regions(pdev);
pci_disable_device(pdev);
pci_set_drvdata(pdev, NULL);
}
}
#ifdef CONFIG_PM
static int e100_suspend(struct pci_dev *pdev, u32 state)
{
struct net_device *netdev = pci_get_drvdata(pdev);
struct nic *nic = netdev->priv;
if(netif_running(netdev))
e100_down(nic);
e100_hw_reset(nic);
netif_device_detach(netdev);
pci_save_state(pdev, nic->pm_state);
pci_enable_wake(pdev, state, nic->flags & (wol_magic | e100_asf(nic)));
pci_disable_device(pdev);
pci_set_power_state(pdev, state);
return 0;
}
static int e100_resume(struct pci_dev *pdev)
{
struct net_device *netdev = pci_get_drvdata(pdev);
struct nic *nic = netdev->priv;
pci_set_power_state(pdev, 0);
pci_restore_state(pdev, nic->pm_state);
e100_hw_init(nic);
netif_device_attach(netdev);
if(netif_running(netdev))
e100_up(nic);
return 0;
}
#endif
static struct pci_driver e100_driver = {
.name = DRV_NAME,
.id_table = e100_id_table,
.probe = e100_probe,
.remove = __devexit_p(e100_remove),
#ifdef CONFIG_PM
.suspend = e100_suspend,
.resume = e100_resume,
#endif
};
static int __init e100_init_module(void)
{
if(((1 << debug) - 1) & NETIF_MSG_DRV) {
printk(KERN_INFO PFX "%s, %s\n", DRV_DESCRIPTION, DRV_VERSION);
printk(KERN_INFO PFX "%s\n", DRV_COPYRIGHT);
}
return pci_module_init(&e100_driver);
}
static void __exit e100_cleanup_module(void)
{
pci_unregister_driver(&e100_driver);
}
module_init(e100_init_module);
module_exit(e100_cleanup_module);
drivers/net/e100/LICENSE deleted 100644 → 0
View file @ 02a38ad0
"This software program is licensed subject to the GNU General Public License
(GPL). Version 2, June 1991, available at
<http://www.fsf.org/copyleft/gpl.html>"
GNU General Public License
Version 2, June 1991
Copyright (C) 1989, 1991 Free Software Foundation, Inc.
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
Everyone is permitted to copy and distribute verbatim copies of this license
document, but changing it is not allowed.
Preamble
The licenses for most software are designed to take away your freedom to
share and change it. By contrast, the GNU General Public License is intended
to guarantee your freedom to share and change free software--to make sure
the software is free for all its users. This General Public License applies
to most of the Free Software Foundation's software and to any other program
whose authors commit to using it. (Some other Free Software Foundation
software is covered by the GNU Library General Public License instead.) You
can apply it to your programs, too.
When we speak of free software, we are referring to freedom, not price. Our
General Public Licenses are designed to make sure that you have the freedom
to distribute copies of free software (and charge for this service if you
wish), that you receive source code or can get it if you want it, that you
can change the software or use pieces of it in new free programs; and that
you know you can do these things.
To protect your rights, we need to make restrictions that forbid anyone to
deny you these rights or to ask you to surrender the rights. These
restrictions translate to certain responsibilities for you if you distribute
copies of the software, or if you modify it.
For example, if you distribute copies of such a program, whether gratis or
for a fee, you must give the recipients all the rights that you have. You
must make sure that they, too, receive or can get the source code. And you
must show them these terms so they know their rights.
We protect your rights with two steps: (1) copyright the software, and (2)
offer you this license which gives you legal permission to copy, distribute
and/or modify the software.
Also, for each author's protection and ours, we want to make certain that
everyone understands that there is no warranty for this free software. If
the software is modified by someone else and passed on, we want its
recipients to know that what they have is not the original, so that any
problems introduced by others will not reflect on the original authors'
reputations.
Finally, any free program is threatened constantly by software patents. We
wish to avoid the danger that redistributors of a free program will
individually obtain patent licenses, in effect making the program
proprietary. To prevent this, we have made it clear that any patent must be
licensed for everyone's free use or not licensed at all.
The precise terms and conditions for copying, distribution and modification
follow.
TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
0. This License applies to any program or other work which contains a notice
placed by the copyright holder saying it may be distributed under the
terms of this General Public License. The "Program", below, refers to any
such program or work, and a "work based on the Program" means either the
Program or any derivative work under copyright law: that is to say, a
work containing the Program or a portion of it, either verbatim or with
modifications and/or translated into another language. (Hereinafter,
translation is included without limitation in the term "modification".)
Each licensee is addressed as "you".
Activities other than copying, distribution and modification are not
covered by this License; they are outside its scope. The act of running
the Program is not restricted, and the output from the Program is covered
only if its contents constitute a work based on the Program (independent
of having been made by running the Program). Whether that is true depends
on what the Program does.
1. You may copy and distribute verbatim copies of the Program's source code
as you receive it, in any medium, provided that you conspicuously and
appropriately publish on each copy an appropriate copyright notice and
disclaimer of warranty; keep intact all the notices that refer to this
License and to the absence of any warranty; and give any other recipients
of the Program a copy of this License along with the Program.
You may charge a fee for the physical act of transferring a copy, and you
may at your option offer warranty protection in exchange for a fee.
2. You may modify your copy or copies of the Program or any portion of it,
thus forming a work based on the Program, and copy and distribute such
modifications or work under the terms of Section 1 above, provided that
you also meet all of these conditions:
* a) You must cause the modified files to carry prominent notices stating
that you changed the files and the date of any change.
* b) You must cause any work that you distribute or publish, that in
whole or in part contains or is derived from the Program or any part
thereof, to be licensed as a whole at no charge to all third parties
under the terms of this License.
* c) If the modified program normally reads commands interactively when
run, you must cause it, when started running for such interactive
use in the most ordinary way, to print or display an announcement
including an appropriate copyright notice and a notice that there is
no warranty (or else, saying that you provide a warranty) and that
users may redistribute the program under these conditions, and
telling the user how to view a copy of this License. (Exception: if
the Program itself is interactive but does not normally print such
an announcement, your work based on the Program is not required to
print an announcement.)
These requirements apply to the modified work as a whole. If identifiable
sections of that work are not derived from the Program, and can be
reasonably considered independent and separate works in themselves, then
this License, and its terms, do not apply to those sections when you
distribute them as separate works. But when you distribute the same
sections as part of a whole which is a work based on the Program, the
distribution of the whole must be on the terms of this License, whose
permissions for other licensees extend to the entire whole, and thus to
each and every part regardless of who wrote it.
Thus, it is not the intent of this section to claim rights or contest
your rights to work written entirely by you; rather, the intent is to
exercise the right to control the distribution of derivative or
collective works based on the Program.
In addition, mere aggregation of another work not based on the Program
with the Program (or with a work based on the Program) on a volume of a
storage or distribution medium does not bring the other work under the
scope of this License.
3. You may copy and distribute the Program (or a work based on it, under
Section 2) in object code or executable form under the terms of Sections
1 and 2 above provided that you also do one of the following:
* a) Accompany it with the complete corresponding machine-readable source
code, which must be distributed under the terms of Sections 1 and 2
above on a medium customarily used for software interchange; or,
* b) Accompany it with a written offer, valid for at least three years,
to give any third party, for a charge no more than your cost of
physically performing source distribution, a complete machine-
readable copy of the corresponding source code, to be distributed
under the terms of Sections 1 and 2 above on a medium customarily
used for software interchange; or,
* c) Accompany it with the information you received as to the offer to
distribute corresponding source code. (This alternative is allowed
only for noncommercial distribution and only if you received the
program in object code or executable form with such an offer, in
accord with Subsection b above.)
The source code for a work means the preferred form of the work for
making modifications to it. For an executable work, complete source code
means all the source code for all modules it contains, plus any
associated interface definition files, plus the scripts used to control
compilation and installation of the executable. However, as a special
exception, the source code distributed need not include anything that is
normally distributed (in either source or binary form) with the major
components (compiler, kernel, and so on) of the operating system on which
the executable runs, unless that component itself accompanies the
executable.
If distribution of executable or object code is made by offering access
to copy from a designated place, then offering equivalent access to copy
the source code from the same place counts as distribution of the source
code, even though third parties are not compelled to copy the source
along with the object code.
4. You may not copy, modify, sublicense, or distribute the Program except as
expressly provided under this License. Any attempt otherwise to copy,
modify, sublicense or distribute the Program is void, and will
automatically terminate your rights under this License. However, parties
who have received copies, or rights, from you under this License will not
have their licenses terminated so long as such parties remain in full
compliance.
5. You are not required to accept this License, since you have not signed
it. However, nothing else grants you permission to modify or distribute
the Program or its derivative works. These actions are prohibited by law
if you do not accept this License. Therefore, by modifying or
distributing the Program (or any work based on the Program), you
indicate your acceptance of this License to do so, and all its terms and
conditions for copying, distributing or modifying the Program or works
based on it.
6. Each time you redistribute the Program (or any work based on the
Program), the recipient automatically receives a license from the
original licensor to copy, distribute or modify the Program subject to
these terms and conditions. You may not impose any further restrictions
on the recipients' exercise of the rights granted herein. You are not
responsible for enforcing compliance by third parties to this License.
7. If, as a consequence of a court judgment or allegation of patent
infringement or for any other reason (not limited to patent issues),
conditions are imposed on you (whether by court order, agreement or
otherwise) that contradict the conditions of this License, they do not
excuse you from the conditions of this License. If you cannot distribute
so as to satisfy simultaneously your obligations under this License and
any other pertinent obligations, then as a consequence you may not
distribute the Program at all. For example, if a patent license would
not permit royalty-free redistribution of the Program by all those who
receive copies directly or indirectly through you, then the only way you
could satisfy both it and this License would be to refrain entirely from
distribution of the Program.
If any portion of this section is held invalid or unenforceable under any
particular circumstance, the balance of the section is intended to apply
and the section as a whole is intended to apply in other circumstances.
It is not the purpose of this section to induce you to infringe any
patents or other property right claims or to contest validity of any
such claims; this section has the sole purpose of protecting the
integrity of the free software distribution system, which is implemented
by public license practices. Many people have made generous contributions
to the wide range of software distributed through that system in
reliance on consistent application of that system; it is up to the
author/donor to decide if he or she is willing to distribute software
through any other system and a licensee cannot impose that choice.
This section is intended to make thoroughly clear what is believed to be
a consequence of the rest of this License.
8. If the distribution and/or use of the Program is restricted in certain
countries either by patents or by copyrighted interfaces, the original
copyright holder who places the Program under this License may add an
explicit geographical distribution limitation excluding those countries,
so that distribution is permitted only in or among countries not thus
excluded. In such case, this License incorporates the limitation as if
written in the body of this License.
9. The Free Software Foundation may publish revised and/or new versions of
the General Public License from time to time. Such new versions will be
similar in spirit to the present version, but may differ in detail to
address new problems or concerns.
Each version is given a distinguishing version number. If the Program
specifies a version number of this License which applies to it and "any
later version", you have the option of following the terms and
conditions either of that version or of any later version published by
the Free Software Foundation. If the Program does not specify a version
number of this License, you may choose any version ever published by the
Free Software Foundation.
10. If you wish to incorporate parts of the Program into other free programs
whose distribution conditions are different, write to the author to ask
for permission. For software which is copyrighted by the Free Software
Foundation, write to the Free Software Foundation; we sometimes make
exceptions for this. Our decision will be guided by the two goals of
preserving the free status of all derivatives of our free software and
of promoting the sharing and reuse of software generally.
NO WARRANTY
11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY
FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN
OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES
PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE
ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH
YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL
NECESSARY SERVICING, REPAIR OR CORRECTION.
12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR
REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR
DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL
DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PROGRAM
(INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED
INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF
THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH HOLDER OR
OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
END OF TERMS AND CONDITIONS
How to Apply These Terms to Your New Programs
If you develop a new program, and you want it to be of the greatest
possible use to the public, the best way to achieve this is to make it free
software which everyone can redistribute and change under these terms.
To do so, attach the following notices to the program. It is safest to
attach them to the start of each source file to most effectively convey the
exclusion of warranty; and each file should have at least the "copyright"
line and a pointer to where the full notice is found.
one line to give the program's name and an idea of what it does.
Copyright (C) yyyy name of author
This program is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the Free
Software Foundation; either version 2 of the License, or (at your option)
any later version.
This program is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
this program; if not, write to the Free Software Foundation, Inc., 59
Temple Place - Suite 330, Boston, MA 02111-1307, USA.
Also add information on how to contact you by electronic and paper mail.
If the program is interactive, make it output a short notice like this when
it starts in an interactive mode:
Gnomovision version 69, Copyright (C) year name of author Gnomovision comes
with ABSOLUTELY NO WARRANTY; for details type 'show w'. This is free
software, and you are welcome to redistribute it under certain conditions;
type 'show c' for details.
The hypothetical commands 'show w' and 'show c' should show the appropriate
parts of the General Public License. Of course, the commands you use may be
called something other than 'show w' and 'show c'; they could even be
mouse-clicks or menu items--whatever suits your program.
You should also get your employer (if you work as a programmer) or your
school, if any, to sign a "copyright disclaimer" for the program, if
necessary. Here is a sample; alter the names:
Yoyodyne, Inc., hereby disclaims all copyright interest in the program
'Gnomovision' (which makes passes at compilers) written by James Hacker.
signature of Ty Coon, 1 April 1989
Ty Coon, President of Vice
This General Public License does not permit incorporating your program into
proprietary programs. If your program is a subroutine library, you may
consider it more useful to permit linking proprietary applications with the
library. If this is what you want to do, use the GNU Library General Public
License instead of this License.
drivers/net/e100/Makefile deleted 100644 → 0
View file @ 02a38ad0
#
# Makefile for the Intel's E100 ethernet driver
#
obj-$(CONFIG_E100) += e100.o
e100-objs := e100_main.o e100_config.o e100_phy.o \
e100_eeprom.o e100_test.o
drivers/net/e100/e100.h deleted 100644 → 0
View file @ 02a38ad0
/*******************************************************************************
Copyright(c) 1999 - 2003 Intel Corporation. All rights reserved.
This program is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the Free
Software Foundation; either version 2 of the License, or (at your option)
any later version.
This program is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
this program; if not, write to the Free Software Foundation, Inc., 59
Temple Place - Suite 330, Boston, MA 02111-1307, USA.
The full GNU General Public License is included in this distribution in the
file called LICENSE.
Contact Information:
Linux NICS <linux.nics@intel.com>
Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
*******************************************************************************/
#ifndef _E100_INC_
#define _E100_INC_
#include <linux/module.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/errno.h>
#include <linux/ioport.h>
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/delay.h>
#include <linux/timer.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/string.h>
#include <linux/wait.h>
#include <linux/reboot.h>
#include <asm/io.h>
#include <asm/unaligned.h>
#include <asm/processor.h>
#include <linux/ethtool.h>
#include <linux/inetdevice.h>
#include <linux/bitops.h>
#include <linux/if.h>
#include <asm/uaccess.h>
#include <linux/ip.h>
#include <linux/if_vlan.h>
#include <linux/mii.h>
#define E100_CABLE_UNKNOWN 0
#define E100_CABLE_OK 1
#define E100_CABLE_OPEN_NEAR 2 /* Open Circuit Near End */
#define E100_CABLE_OPEN_FAR 3 /* Open Circuit Far End */
#define E100_CABLE_SHORT_NEAR 4 /* Short Circuit Near End */
#define E100_CABLE_SHORT_FAR 5 /* Short Circuit Far End */
#define E100_REGS_LEN 2
/*
* Configure parameters for buffers per controller.
* If the machine this is being used on is a faster machine (i.e. > 150MHz)
* and running on a 10MBS network then more queueing of data occurs. This
* may indicate the some of the numbers below should be adjusted. Here are
* some typical numbers:
* MAX_TCB 64
* MAX_RFD 64
* The default numbers give work well on most systems tests so no real
* adjustments really need to take place. Also, if the machine is connected
* to a 100MBS network the numbers described above can be lowered from the
* defaults as considerably less data will be queued.
*/
#define TX_FRAME_CNT 8 /* consecutive transmit frames per interrupt */
/* TX_FRAME_CNT must be less than MAX_TCB */
#define E100_DEFAULT_TCB 64
#define E100_MIN_TCB 2*TX_FRAME_CNT + 3 /* make room for at least 2 interrupts */
#define E100_MAX_TCB 1024
#define E100_DEFAULT_RFD 64
#define E100_MIN_RFD 8
#define E100_MAX_RFD 1024
#define E100_DEFAULT_XSUM true
#define E100_DEFAULT_BER ZLOCK_MAX_ERRORS
#define E100_DEFAULT_SPEED_DUPLEX 0
#define E100_DEFAULT_FC 0
#define E100_DEFAULT_IFS true
#define E100_DEFAULT_UCODE true
#define TX_THRSHLD 8
/* IFS parameters */
#define MIN_NUMBER_OF_TRANSMITS_100 1000
#define MIN_NUMBER_OF_TRANSMITS_10 100
#define E100_MAX_NIC 16
#define E100_MAX_SCB_WAIT 100 /* Max udelays in wait_scb */
#define E100_MAX_CU_IDLE_WAIT 50 /* Max udelays in wait_cus_idle */
/* HWI feature related constant */
#define HWI_REGISTER_GRANULARITY 80 /* register granularity = 80 Cm */
#define HWI_NEAR_END_BOUNDARY 1000 /* Near end is defined as < 10 meters */
/* CPUSAVER_BUNDLE_MAX: Sets the maximum number of frames that will be bundled.
* In some situations, such as the TCP windowing algorithm, it may be
* better to limit the growth of the bundle size than let it go as
* high as it can, because that could cause too much added latency.
* The default is six, because this is the number of packets in the
* default TCP window size. A value of 1 would make CPUSaver indicate
* an interrupt for every frame received. If you do not want to put
* a limit on the bundle size, set this value to xFFFF.
*/
#define E100_DEFAULT_CPUSAVER_BUNDLE_MAX 6
#define E100_DEFAULT_CPUSAVER_INTERRUPT_DELAY 0x600
#define E100_DEFAULT_BUNDLE_SMALL_FR false
/* end of configurables */
/* ====================================================================== */
/* hw */
/* ====================================================================== */
/* timeout for command completion */
#define E100_CMD_WAIT 100 /* iterations */
struct driver_stats {
struct net_device_stats net_stats;
unsigned long tx_late_col;
unsigned long tx_ok_defrd;
unsigned long tx_one_retry;
unsigned long tx_mt_one_retry;
unsigned long rcv_cdt_frames;
unsigned long xmt_fc_pkts;
unsigned long rcv_fc_pkts;
unsigned long rcv_fc_unsupported;
unsigned long xmt_tco_pkts;
unsigned long rcv_tco_pkts;
unsigned long rx_intr_pkts;
};
/* TODO: kill me when we can do C99 */
#define false (0)
#define true (1)
/* Changed for 82558 and 82559 enhancements */
/* defines for 82558/9 flow control CSR values */
#define DFLT_FC_THLD 0x00 /* Rx FIFO threshold of 0.5KB free */
#define DFLT_FC_CMD 0x00 /* FC Command in CSR */
/* ====================================================================== */
/* equates */
/* ====================================================================== */
/*
* These are general purpose defines
*/
/* Bit Mask definitions */
#define BIT_0 0x0001
#define BIT_1 0x0002
#define BIT_2 0x0004
#define BIT_3 0x0008
#define BIT_4 0x0010
#define BIT_5 0x0020
#define BIT_6 0x0040
#define BIT_7 0x0080
#define BIT_8 0x0100
#define BIT_9 0x0200
#define BIT_10 0x0400
#define BIT_11 0x0800
#define BIT_12 0x1000
#define BIT_13 0x2000
#define BIT_14 0x4000
#define BIT_15 0x8000
#define BIT_28 0x10000000
#define BIT_0_2 0x0007
#define BIT_0_3 0x000F
#define BIT_0_4 0x001F
#define BIT_0_5 0x003F
#define BIT_0_6 0x007F
#define BIT_0_7 0x00FF
#define BIT_0_8 0x01FF
#define BIT_0_13 0x3FFF
#define BIT_0_15 0xFFFF
#define BIT_1_2 0x0006
#define BIT_1_3 0x000E
#define BIT_2_5 0x003C
#define BIT_3_4 0x0018
#define BIT_4_5 0x0030
#define BIT_4_6 0x0070
#define BIT_4_7 0x00F0
#define BIT_5_7 0x00E0
#define BIT_5_12 0x1FE0
#define BIT_5_15 0xFFE0
#define BIT_6_7 0x00c0
#define BIT_7_11 0x0F80
#define BIT_8_10 0x0700
#define BIT_9_13 0x3E00
#define BIT_12_15 0xF000
#define BIT_8_15 0xFF00
#define BIT_16_20 0x001F0000
#define BIT_21_25 0x03E00000
#define BIT_26_27 0x0C000000
/* Transmit Threshold related constants */
#define DEFAULT_TX_PER_UNDERRUN 20000
#define MAX_MULTICAST_ADDRS 64
#define MAX_FILTER 16
#define FULL_DUPLEX 2
#define HALF_DUPLEX 1
/*
* These defines are specific to the 82557
*/
/* E100 PORT functions -- lower 4 bits */
#define PORT_SOFTWARE_RESET 0
#define PORT_SELFTEST 1
#define PORT_SELECTIVE_RESET 2
#define PORT_DUMP 3
/* SCB Status Word bit definitions */
/* Interrupt status/ack fields */
/* ER and FCP interrupts for 82558 masks */
#define SCB_STATUS_ACK_MASK BIT_8_15 /* Status Mask */
#define SCB_STATUS_ACK_CX BIT_15 /* CU Completed Action Cmd */
#define SCB_STATUS_ACK_FR BIT_14 /* RU Received A Frame */
#define SCB_STATUS_ACK_CNA BIT_13 /* CU Became Inactive (IDLE) */
#define SCB_STATUS_ACK_RNR BIT_12 /* RU Became Not Ready */
#define SCB_STATUS_ACK_MDI BIT_11 /* MDI read or write done */
#define SCB_STATUS_ACK_SWI BIT_10 /* S/W generated interrupt */
#define SCB_STATUS_ACK_ER BIT_9 /* Early Receive */
#define SCB_STATUS_ACK_FCP BIT_8 /* Flow Control Pause */
/*- CUS Fields */
#define SCB_CUS_MASK (BIT_6 | BIT_7) /* CUS 2-bit Mask */
#define SCB_CUS_IDLE 0 /* CU Idle */
#define SCB_CUS_SUSPEND BIT_6 /* CU Suspended */
#define SCB_CUS_ACTIVE BIT_7 /* CU Active */
/*- RUS Fields */
#define SCB_RUS_IDLE 0 /* RU Idle */
#define SCB_RUS_MASK BIT_2_5 /* RUS 3-bit Mask */
#define SCB_RUS_SUSPEND BIT_2 /* RU Suspended */
#define SCB_RUS_NO_RESOURCES BIT_3 /* RU Out Of Resources */
#define SCB_RUS_READY BIT_4 /* RU Ready */
#define SCB_RUS_SUSP_NO_RBDS (BIT_2 | BIT_5) /* RU No More RBDs */
#define SCB_RUS_NO_RBDS (BIT_3 | BIT_5) /* RU No More RBDs */
#define SCB_RUS_READY_NO_RBDS (BIT_4 | BIT_5) /* RU Ready, No RBDs */
/* SCB Command Word bit definitions */
/*- CUC fields */
/* Changing mask to 4 bits */
#define SCB_CUC_MASK BIT_4_7 /* CUC 4-bit Mask */
#define SCB_CUC_NOOP 0
#define SCB_CUC_START BIT_4 /* CU Start */
#define SCB_CUC_RESUME BIT_5 /* CU Resume */
#define SCB_CUC_UNKNOWN BIT_7 /* CU unknown command */
/* Changed for 82558 enhancements */
#define SCB_CUC_STATIC_RESUME (BIT_5 | BIT_7) /* 82558/9 Static Resume */
#define SCB_CUC_DUMP_ADDR BIT_6 /* CU Dump Counters Address */
#define SCB_CUC_DUMP_STAT (BIT_4 | BIT_6) /* CU Dump stat. counters */
#define SCB_CUC_LOAD_BASE (BIT_5 | BIT_6) /* Load the CU base */
/* Below was defined as BIT_4_7 */
#define SCB_CUC_DUMP_RST_STAT BIT_4_6 /* CU Dump & reset statistics cntrs */
/*- RUC fields */
#define SCB_RUC_MASK BIT_0_2 /* RUC 3-bit Mask */
#define SCB_RUC_START BIT_0 /* RU Start */
#define SCB_RUC_RESUME BIT_1 /* RU Resume */
#define SCB_RUC_ABORT BIT_2 /* RU Abort */
#define SCB_RUC_LOAD_HDS (BIT_0 | BIT_2) /* Load RFD Header Data Size */
#define SCB_RUC_LOAD_BASE (BIT_1 | BIT_2) /* Load the RU base */
#define SCB_RUC_RBD_RESUME BIT_0_2 /* RBD resume */
/* Interrupt fields (assuming byte addressing) */
#define SCB_INT_MASK BIT_0 /* Mask interrupts */
#define SCB_SOFT_INT BIT_1 /* Generate a S/W interrupt */
/* Specific Interrupt Mask Bits (upper byte of SCB Command word) */
#define SCB_FCP_INT_MASK BIT_2 /* Flow Control Pause */
#define SCB_ER_INT_MASK BIT_3 /* Early Receive */
#define SCB_RNR_INT_MASK BIT_4 /* RU Not Ready */
#define SCB_CNA_INT_MASK BIT_5 /* CU Not Active */
#define SCB_FR_INT_MASK BIT_6 /* Frame Received */
#define SCB_CX_INT_MASK BIT_7 /* CU eXecution w/ I-bit done */
#define SCB_BACHELOR_INT_MASK BIT_2_7 /* 82558 interrupt mask bits */
#define SCB_GCR2_EEPROM_ACCESS_SEMAPHORE BIT_7
/* EEPROM bit definitions */
/*- EEPROM control register bits */
#define EEPROM_FLAG_ASF 0x8000
#define EEPROM_FLAG_GCL 0x4000
#define EN_TRNF 0x10 /* Enable turnoff */
#define EEDO 0x08 /* EEPROM data out */
#define EEDI 0x04 /* EEPROM data in (set for writing data) */
#define EECS 0x02 /* EEPROM chip select (1=hi, 0=lo) */
#define EESK 0x01 /* EEPROM shift clock (1=hi, 0=lo) */
/*- EEPROM opcodes */
#define EEPROM_READ_OPCODE 06
#define EEPROM_WRITE_OPCODE 05
#define EEPROM_ERASE_OPCODE 07
#define EEPROM_EWEN_OPCODE 19 /* Erase/write enable */
#define EEPROM_EWDS_OPCODE 16 /* Erase/write disable */
/*- EEPROM data locations */
#define EEPROM_NODE_ADDRESS_BYTE_0 0
#define EEPROM_COMPATIBILITY_WORD 3
#define EEPROM_PWA_NO 8
#define EEPROM_ID_WORD 0x0A
#define EEPROM_CONFIG_ASF 0x0D
#define EEPROM_SMBUS_ADDR 0x90
#define EEPROM_SUM 0xbaba
// Zero Locking Algorithm definitions:
#define ZLOCK_ZERO_MASK 0x00F0
#define ZLOCK_MAX_READS 50
#define ZLOCK_SET_ZERO 0x2010
#define ZLOCK_MAX_SLEEP 300 * HZ
#define ZLOCK_MAX_ERRORS 300
/* E100 Action Commands */
#define CB_IA_ADDRESS 1
#define CB_CONFIGURE 2
#define CB_MULTICAST 3
#define CB_TRANSMIT 4
#define CB_LOAD_MICROCODE 5
#define CB_LOAD_FILTER 8
#define CB_MAX_NONTX_CMD 9
#define CB_IPCB_TRANSMIT 9
/* Pre-defined Filter Bits */
#define CB_FILTER_EL 0x80000000
#define CB_FILTER_FIX 0x40000000
#define CB_FILTER_ARP 0x08000000
#define CB_FILTER_IA_MATCH 0x02000000
/* Command Block (CB) Field Definitions */
/*- CB Command Word */
#define CB_EL_BIT BIT_15 /* CB EL Bit */
#define CB_S_BIT BIT_14 /* CB Suspend Bit */
#define CB_I_BIT BIT_13 /* CB Interrupt Bit */
#define CB_TX_SF_BIT BIT_3 /* TX CB Flexible Mode */
#define CB_CMD_MASK BIT_0_3 /* CB 4-bit CMD Mask */
#define CB_CID_DEFAULT (0x1f << 8) /* CB 5-bit CID (max value) */
/*- CB Status Word */
#define CB_STATUS_MASK BIT_12_15 /* CB Status Mask (4-bits) */
#define CB_STATUS_COMPLETE BIT_15 /* CB Complete Bit */
#define CB_STATUS_OK BIT_13 /* CB OK Bit */
#define CB_STATUS_VLAN BIT_12 /* CB Valn detected Bit */
#define CB_STATUS_FAIL BIT_11 /* CB Fail (F) Bit */
/*misc command bits */
#define CB_TX_EOF_BIT BIT_15 /* TX CB/TBD EOF Bit */
/* Config params */
#define CB_CFIG_BYTE_COUNT 22 /* 22 config bytes */
#define CB_CFIG_D102_BYTE_COUNT 10
/* Receive Frame Descriptor Fields */
/*- RFD Status Bits */
#define RFD_RECEIVE_COLLISION BIT_0 /* Collision detected on Receive */
#define RFD_IA_MATCH BIT_1 /* Indv Address Match Bit */
#define RFD_RX_ERR BIT_4 /* RX_ERR pin on Phy was set */
#define RFD_FRAME_TOO_SHORT BIT_7 /* Receive Frame Short */
#define RFD_DMA_OVERRUN BIT_8 /* Receive DMA Overrun */
#define RFD_NO_RESOURCES BIT_9 /* No Buffer Space */
#define RFD_ALIGNMENT_ERROR BIT_10 /* Alignment Error */
#define RFD_CRC_ERROR BIT_11 /* CRC Error */
#define RFD_STATUS_OK BIT_13 /* RFD OK Bit */
#define RFD_STATUS_COMPLETE BIT_15 /* RFD Complete Bit */
/*- RFD Command Bits*/
#define RFD_EL_BIT BIT_15 /* RFD EL Bit */
#define RFD_S_BIT BIT_14 /* RFD Suspend Bit */
#define RFD_H_BIT BIT_4 /* Header RFD Bit */
#define RFD_SF_BIT BIT_3 /* RFD Flexible Mode */
/*- RFD misc bits*/
#define RFD_EOF_BIT BIT_15 /* RFD End-Of-Frame Bit */
#define RFD_F_BIT BIT_14 /* RFD Buffer Fetch Bit */
#define RFD_ACT_COUNT_MASK BIT_0_13 /* RFD Actual Count Mask */
/* Receive Buffer Descriptor Fields*/
#define RBD_EOF_BIT BIT_15 /* RBD End-Of-Frame Bit */
#define RBD_F_BIT BIT_14 /* RBD Buffer Fetch Bit */
#define RBD_ACT_COUNT_MASK BIT_0_13 /* RBD Actual Count Mask */
#define SIZE_FIELD_MASK BIT_0_13 /* Size of the associated buffer */
#define RBD_EL_BIT BIT_15 /* RBD EL Bit */
/* Self Test Results*/
#define CB_SELFTEST_FAIL_BIT BIT_12
#define CB_SELFTEST_DIAG_BIT BIT_5
#define CB_SELFTEST_REGISTER_BIT BIT_3
#define CB_SELFTEST_ROM_BIT BIT_2
#define CB_SELFTEST_ERROR_MASK ( \
CB_SELFTEST_FAIL_BIT | CB_SELFTEST_DIAG_BIT | \
CB_SELFTEST_REGISTER_BIT | CB_SELFTEST_ROM_BIT)
/* adapter vendor & device ids */
#define PCI_OHIO_BOARD 0x10f0 /* subdevice ID, Ohio dual port nic */
/* Values for PCI_REV_ID_REGISTER values */
#define D101A4_REV_ID 4 /* 82558 A4 stepping */
#define D101B0_REV_ID 5 /* 82558 B0 stepping */
#define D101MA_REV_ID 8 /* 82559 A0 stepping */
#define D101S_REV_ID 9 /* 82559S A-step */
#define D102_REV_ID 12
#define D102C_REV_ID 13 /* 82550 step C */
#define D102E_REV_ID 15
/* ############Start of 82555 specific defines################## */
#define PHY_82555_LED_SWITCH_CONTROL 0x1b /* 82555 led switch control register */
/* 82555 led switch control reg. opcodes */
#define PHY_82555_LED_NORMAL_CONTROL 0 // control back to the 8255X
#define PHY_82555_LED_DRIVER_CONTROL BIT_2 // the driver is in control
#define PHY_82555_LED_OFF BIT_2 // activity LED is off
#define PHY_82555_LED_ON_559 (BIT_0 | BIT_2) // activity LED is on for 559 and later
#define PHY_82555_LED_ON_PRE_559 (BIT_0 | BIT_1 | BIT_2) // activity LED is on for 558 and before
// Describe the state of the phy led.
// needed for the function : 'e100_blink_timer'
enum led_state_e {
LED_OFF = 0,
LED_ON,
};
/* ############End of 82555 specific defines##################### */
#define RFD_PARSE_BIT BIT_3
#define RFD_TCP_PACKET 0x00
#define RFD_UDP_PACKET 0x01
#define TCPUDP_CHECKSUM_BIT_VALID BIT_4
#define TCPUDP_CHECKSUM_VALID BIT_5
#define CHECKSUM_PROTOCOL_MASK 0x03
#define VLAN_SIZE 4
#define CHKSUM_SIZE 2
#define RFD_DATA_SIZE (ETH_FRAME_LEN + CHKSUM_SIZE + VLAN_SIZE)
/* Bits for bdp->flags */
#define DF_LINK_FC_CAP 0x00000001 /* Link is flow control capable */
#define DF_CSUM_OFFLOAD 0x00000002
#define DF_UCODE_LOADED 0x00000004
#define USE_IPCB 0x00000008 /* set if using ipcb for transmits */
#define IS_BACHELOR 0x00000010 /* set if 82558 or newer board */
#define IS_ICH 0x00000020
#define DF_SPEED_FORCED 0x00000040 /* set if speed is forced */
#define LED_IS_ON 0x00000080 /* LED is turned ON by the driver */
#define DF_LINK_FC_TX_ONLY 0x00000100 /* Received PAUSE frames are honored*/
typedef struct net_device_stats net_dev_stats_t;
/* needed macros */
/* These macros use the bdp pointer. If you use them it better be defined */
#define PREV_TCB_USED(X) ((X).tail ? (X).tail - 1 : bdp->params.TxDescriptors - 1)
#define NEXT_TCB_TOUSE(X) ((((X) + 1) >= bdp->params.TxDescriptors) ? 0 : (X) + 1)
#define TCB_TO_USE(X) ((X).tail)
#define TCBS_AVAIL(X) (NEXT_TCB_TOUSE( NEXT_TCB_TOUSE((X).tail)) != (X).head)
#define RFD_POINTER(skb,bdp) ((rfd_t *) (((unsigned char *)((skb)->data))-((bdp)->rfd_size)))
#define SKB_RFD_STATUS(skb,bdp) ((RFD_POINTER((skb),(bdp)))->rfd_header.cb_status)
/* ====================================================================== */
/* 82557 */
/* ====================================================================== */
/* Changed for 82558 enhancement */
typedef struct _d101_scb_ext_t {
u32 scb_rx_dma_cnt; /* Rx DMA byte count */
u8 scb_early_rx_int; /* Early Rx DMA byte count */
u8 scb_fc_thld; /* Flow Control threshold */
u8 scb_fc_xon_xoff; /* Flow Control XON/XOFF values */
u8 scb_pmdr; /* Power Mgmt. Driver Reg */
} d101_scb_ext __attribute__ ((__packed__));
/* Changed for 82559 enhancement */
typedef struct _d101m_scb_ext_t {
u32 scb_rx_dma_cnt; /* Rx DMA byte count */
u8 scb_early_rx_int; /* Early Rx DMA byte count */
u8 scb_fc_thld; /* Flow Control threshold */
u8 scb_fc_xon_xoff; /* Flow Control XON/XOFF values */
u8 scb_pmdr; /* Power Mgmt. Driver Reg */
u8 scb_gen_ctrl; /* General Control */
u8 scb_gen_stat; /* General Status */
u16 scb_reserved; /* Reserved */
u32 scb_function_event; /* Cardbus Function Event */
u32 scb_function_event_mask; /* Cardbus Function Mask */
u32 scb_function_present_state; /* Cardbus Function state */
u32 scb_force_event; /* Cardbus Force Event */
} d101m_scb_ext __attribute__ ((__packed__));
/* Changed for 82550 enhancement */
typedef struct _d102_scb_ext_t {
u32 scb_rx_dma_cnt; /* Rx DMA byte count */
u8 scb_early_rx_int; /* Early Rx DMA byte count */
u8 scb_fc_thld; /* Flow Control threshold */
u8 scb_fc_xon_xoff; /* Flow Control XON/XOFF values */
u8 scb_pmdr; /* Power Mgmt. Driver Reg */
u8 scb_gen_ctrl; /* General Control */
u8 scb_gen_stat; /* General Status */
u8 scb_gen_ctrl2;
u8 scb_reserved; /* Reserved */
u32 scb_scheduling_reg;
u32 scb_reserved2;
u32 scb_function_event; /* Cardbus Function Event */
u32 scb_function_event_mask; /* Cardbus Function Mask */
u32 scb_function_present_state; /* Cardbus Function state */
u32 scb_force_event; /* Cardbus Force Event */
} d102_scb_ext __attribute__ ((__packed__));
/*
* 82557 status control block. this will be memory mapped & will hang of the
* the bdp, which hangs of the bdp. This is the brain of it.
*/
typedef struct _scb_t {
u16 scb_status; /* SCB Status register */
u8 scb_cmd_low; /* SCB Command register (low byte) */
u8 scb_cmd_hi; /* SCB Command register (high byte) */
u32 scb_gen_ptr; /* SCB General pointer */
u32 scb_port; /* PORT register */
u16 scb_flsh_cntrl; /* Flash Control register */
u16 scb_eprm_cntrl; /* EEPROM control register */
u32 scb_mdi_cntrl; /* MDI Control Register */
/* Changed for 82558 enhancement */
union {
u32 scb_rx_dma_cnt; /* Rx DMA byte count */
d101_scb_ext d101_scb; /* 82558/9 specific fields */
d101m_scb_ext d101m_scb; /* 82559 specific fields */
d102_scb_ext d102_scb;
} scb_ext;
} scb_t __attribute__ ((__packed__));
/* Self test
* This is used to dump results of the self test
*/
typedef struct _self_test_t {
u32 st_sign; /* Self Test Signature */
u32 st_result; /* Self Test Results */
} self_test_t __attribute__ ((__packed__));
/*
* Statistical Counters
*/
/* 82557 counters */
typedef struct _basic_cntr_t {
u32 xmt_gd_frames; /* Good frames transmitted */
u32 xmt_max_coll; /* Fatal frames -- had max collisions */
u32 xmt_late_coll; /* Fatal frames -- had a late coll. */
u32 xmt_uruns; /* Xmit underruns (fatal or re-transmit) */
u32 xmt_lost_crs; /* Frames transmitted without CRS */
u32 xmt_deferred; /* Deferred transmits */
u32 xmt_sngl_coll; /* Transmits that had 1 and only 1 coll. */
u32 xmt_mlt_coll; /* Transmits that had multiple coll. */
u32 xmt_ttl_coll; /* Transmits that had 1+ collisions. */
u32 rcv_gd_frames; /* Good frames received */
u32 rcv_crc_errs; /* Aligned frames that had a CRC error */
u32 rcv_algn_errs; /* Receives that had alignment errors */
u32 rcv_rsrc_err; /* Good frame dropped cuz no resources */
u32 rcv_oruns; /* Overrun errors - bus was busy */
u32 rcv_err_coll; /* Received frms. that encountered coll. */
u32 rcv_shrt_frames; /* Received frames that were to short */
} basic_cntr_t;
/* 82558 extended statistic counters */
typedef struct _ext_cntr_t {
u32 xmt_fc_frames;
u32 rcv_fc_frames;
u32 rcv_fc_unsupported;
} ext_cntr_t;
/* 82559 TCO statistic counters */
typedef struct _tco_cntr_t {
u16 xmt_tco_frames;
u16 rcv_tco_frames;
} tco_cntr_t;
/* Structures to access thet physical dump area */
/* Use one of these types, according to the statisitcal counters mode,
to cast the pointer to the physical dump area and access the cmd_complete
DWORD. */
/* 557-mode : only basic counters + cmd_complete */
typedef struct _err_cntr_557_t {
basic_cntr_t basic_stats;
u32 cmd_complete;
} err_cntr_557_t;
/* 558-mode : basic + extended counters + cmd_complete */
typedef struct _err_cntr_558_t {
basic_cntr_t basic_stats;
ext_cntr_t extended_stats;
u32 cmd_complete;
} err_cntr_558_t;
/* 559-mode : basic + extended + TCO counters + cmd_complete */
typedef struct _err_cntr_559_t {
basic_cntr_t basic_stats;
ext_cntr_t extended_stats;
tco_cntr_t tco_stats;
u32 cmd_complete;
} err_cntr_559_t;
/* This typedef defines the struct needed to hold the largest number of counters */
typedef err_cntr_559_t max_counters_t;
/* Different statistical-counters mode the controller may be in */
typedef enum _stat_mode_t {
E100_BASIC_STATS = 0, /* 82557 stats : 16 counters / 16 dw */
E100_EXTENDED_STATS, /* 82558 stats : 19 counters / 19 dw */
E100_TCO_STATS /* 82559 stats : 21 counters / 20 dw */
} stat_mode_t;
/* dump statistical counters complete codes */
#define DUMP_STAT_COMPLETED 0xA005
#define DUMP_RST_STAT_COMPLETED 0xA007
/* Command Block (CB) Generic Header Structure*/
typedef struct _cb_header_t {
u16 cb_status; /* Command Block Status */
u16 cb_cmd; /* Command Block Command */
u32 cb_lnk_ptr; /* Link To Next CB */
} cb_header_t __attribute__ ((__packed__));
//* Individual Address Command Block (IA_CB)*/
typedef struct _ia_cb_t {
cb_header_t ia_cb_hdr;
u8 ia_addr[ETH_ALEN];
} ia_cb_t __attribute__ ((__packed__));
/* Configure Command Block (CONFIG_CB)*/
typedef struct _config_cb_t {
cb_header_t cfg_cbhdr;
u8 cfg_byte[CB_CFIG_BYTE_COUNT + CB_CFIG_D102_BYTE_COUNT];
} config_cb_t __attribute__ ((__packed__));
/* MultiCast Command Block (MULTICAST_CB)*/
typedef struct _multicast_cb_t {
cb_header_t mc_cbhdr;
u16 mc_count; /* Number of multicast addresses */
u8 mc_addr[(ETH_ALEN * MAX_MULTICAST_ADDRS)];
} mltcst_cb_t __attribute__ ((__packed__));
#define UCODE_MAX_DWORDS 134
/* Load Microcode Command Block (LOAD_UCODE_CB)*/
typedef struct _load_ucode_cb_t {
cb_header_t load_ucode_cbhdr;
u32 ucode_dword[UCODE_MAX_DWORDS];
} load_ucode_cb_t __attribute__ ((__packed__));
/* Load Programmable Filter Data*/
typedef struct _filter_cb_t {
cb_header_t filter_cb_hdr;
u32 filter_data[MAX_FILTER];
} filter_cb_t __attribute__ ((__packed__));
/* NON_TRANSMIT_CB -- Generic Non-Transmit Command Block
*/
typedef struct _nxmit_cb_t {
union {
config_cb_t config;
ia_cb_t setup;
load_ucode_cb_t load_ucode;
mltcst_cb_t multicast;
filter_cb_t filter;
} ntcb;
} nxmit_cb_t __attribute__ ((__packed__));
/*Block for queuing for postponed execution of the non-transmit commands*/
typedef struct _nxmit_cb_entry_t {
struct list_head list_elem;
nxmit_cb_t *non_tx_cmd;
dma_addr_t dma_addr;
unsigned long expiration_time;
} nxmit_cb_entry_t;
/* States for postponed non tx commands execution */
typedef enum _non_tx_cmd_state_t {
E100_NON_TX_IDLE = 0, /* No queued NON-TX commands */
E100_WAIT_TX_FINISH, /* Wait for completion of the TX activities */
E100_WAIT_NON_TX_FINISH /* Wait for completion of the non TX command */
} non_tx_cmd_state_t;
/* some defines for the ipcb */
#define IPCB_IP_CHECKSUM_ENABLE BIT_4
#define IPCB_TCPUDP_CHECKSUM_ENABLE BIT_5
#define IPCB_TCP_PACKET BIT_6
#define IPCB_LARGESEND_ENABLE BIT_7
#define IPCB_HARDWAREPARSING_ENABLE BIT_0
#define IPCB_INSERTVLAN_ENABLE BIT_1
#define IPCB_IP_ACTIVATION_DEFAULT IPCB_HARDWAREPARSING_ENABLE
/* Transmit Buffer Descriptor (TBD)*/
typedef struct _tbd_t {
u32 tbd_buf_addr; /* Physical Transmit Buffer Address */
u16 tbd_buf_cnt; /* Actual Count Of Bytes */
u16 padd;
} tbd_t __attribute__ ((__packed__));
/* d102 specific fields */
typedef struct _tcb_ipcb_t {
u16 schedule_low;
u8 ip_schedule;
u8 ip_activation_high;
u16 vlan;
u8 ip_header_offset;
u8 tcp_header_offset;
union {
u32 sec_rec_phys_addr;
u32 tbd_zero_address;
} tbd_sec_addr;
union {
u16 sec_rec_size;
u16 tbd_zero_size;
} tbd_sec_size;
u16 total_tcp_payload;
} tcb_ipcb_t __attribute__ ((__packed__));
#define E100_TBD_ARRAY_SIZE (2+MAX_SKB_FRAGS)
/* Transmit Command Block (TCB)*/
struct _tcb_t {
cb_header_t tcb_hdr;
u32 tcb_tbd_ptr; /* TBD address */
u16 tcb_cnt; /* Data Bytes In TCB past header */
u8 tcb_thrshld; /* TX Threshold for FIFO Extender */
u8 tcb_tbd_num;
union {
tcb_ipcb_t ipcb; /* d102 ipcb fields */
tbd_t tbd_array[E100_TBD_ARRAY_SIZE];
} tcbu;
/* From here onward we can dump anything we want as long as the
* size of the total structure is a multiple of a paragraph
* boundary ( i.e. -16 bit aligned ).
*/
tbd_t *tbd_ptr;
u32 tcb_tbd_dflt_ptr; /* TBD address for non-segmented packet */
u32 tcb_tbd_expand_ptr; /* TBD address for segmented packet */
struct sk_buff *tcb_skb; /* the associated socket buffer */
dma_addr_t tcb_phys; /* phys addr of the TCB */
} __attribute__ ((__packed__));
#define _TCB_T_
typedef struct _tcb_t tcb_t;
/* Receive Frame Descriptor (RFD) - will be using the simple model*/
struct _rfd_t {
/* 8255x */
cb_header_t rfd_header;
u32 rfd_rbd_ptr; /* Receive Buffer Descriptor Addr */
u16 rfd_act_cnt; /* Number Of Bytes Received */
u16 rfd_sz; /* Number Of Bytes In RFD */
/* D102 aka Gamla */
u16 vlanid;
u8 rcvparserstatus;
u8 reserved;
u16 securitystatus;
u8 checksumstatus;
u8 zerocopystatus;
u8 pad[8]; /* data should be 16 byte aligned */
u8 data[RFD_DATA_SIZE];
} __attribute__ ((__packed__));
#define _RFD_T_
typedef struct _rfd_t rfd_t;
/* Receive Buffer Descriptor (RBD)*/
typedef struct _rbd_t {
u16 rbd_act_cnt; /* Number Of Bytes Received */
u16 rbd_filler;
u32 rbd_lnk_addr; /* Link To Next RBD */
u32 rbd_rcb_addr; /* Receive Buffer Address */
u16 rbd_sz; /* Receive Buffer Size */
u16 rbd_filler1;
} rbd_t __attribute__ ((__packed__));
/*
* This structure is used to maintain a FIFO access to a resource that is
* maintained as a circular queue. The resource to be maintained is pointed
* to by the "data" field in the structure below. In this driver the TCBs',
* TBDs' & RFDs' are maintained as a circular queue & are managed thru this
* structure.
*/
typedef struct _buf_pool_t {
unsigned int head; /* index to first used resource */
unsigned int tail; /* index to last used resource */
void *data; /* points to resource pool */
} buf_pool_t;
/*Rx skb holding structure*/
struct rx_list_elem {
struct list_head list_elem;
dma_addr_t dma_addr;
struct sk_buff *skb;
};
enum next_cu_cmd_e { RESUME_NO_WAIT = 0, RESUME_WAIT, START_WAIT };
enum zlock_state_e { ZLOCK_INITIAL, ZLOCK_READING, ZLOCK_SLEEPING };
enum tx_queue_stop_type { LONG_STOP = 0, SHORT_STOP };
/* 64 bit aligned size */
#define E100_SIZE_64A(X) ((sizeof(X) + 7) & ~0x7)
typedef struct _bd_dma_able_t {
char selftest[E100_SIZE_64A(self_test_t)];
char stats_counters[E100_SIZE_64A(max_counters_t)];
} bd_dma_able_t;
/* bit masks for bool parameters */
#define PRM_XSUMRX 0x00000001
#define PRM_UCODE 0x00000002
#define PRM_FC 0x00000004
#define PRM_IFS 0x00000008
#define PRM_BUNDLE_SMALL 0x00000010
struct cfg_params {
int e100_speed_duplex;
int RxDescriptors;
int TxDescriptors;
int IntDelay;
int BundleMax;
int ber;
u32 b_params;
};
struct ethtool_lpbk_data{
dma_addr_t dma_handle;
tcb_t *tcb;
rfd_t *rfd;
};
struct e100_private {
struct vlan_group *vlgrp;
u32 flags; /* board management flags */
u32 tx_per_underrun; /* number of good tx frames per underrun */
unsigned int tx_count; /* count of tx frames, so we can request an interrupt */
u8 tx_thld; /* stores transmit threshold */
u16 eeprom_size;
u32 pwa_no; /* PWA: xxxxxx-0xx */
u8 perm_node_address[ETH_ALEN];
struct list_head active_rx_list; /* list of rx buffers */
struct list_head rx_struct_pool; /* pool of rx buffer struct headers */
u16 rfd_size; /* size of the adapter's RFD struct */
int skb_req; /* number of skbs neede by the adapter */
u8 intr_mask; /* mask for interrupt status */
void *dma_able; /* dma allocated structs */
dma_addr_t dma_able_phys;
self_test_t *selftest; /* pointer to self test area */
dma_addr_t selftest_phys; /* phys addr of selftest */
max_counters_t *stats_counters; /* pointer to stats table */
dma_addr_t stat_cnt_phys; /* phys addr of stat counter area */
stat_mode_t stat_mode; /* statistics mode: extended, TCO, basic */
scb_t *scb; /* memory mapped ptr to 82557 scb */
tcb_t *last_tcb; /* pointer to last tcb sent */
buf_pool_t tcb_pool; /* adapter's TCB array */
dma_addr_t tcb_phys; /* phys addr of start of TCBs */
u16 cur_line_speed;
u16 cur_dplx_mode;
struct net_device *device;
struct pci_dev *pdev;
struct driver_stats drv_stats;
u8 rev_id; /* adapter PCI revision ID */
unsigned int phy_addr; /* address of PHY component */
unsigned int PhyId; /* ID of PHY component */
unsigned int PhyState; /* state for the fix squelch algorithm */
unsigned int PhyDelay; /* delay for the fix squelch algorithm */
/* Lock defintions for the driver */
spinlock_t bd_lock; /* board lock */
spinlock_t bd_non_tx_lock; /* Non transmit command lock */
spinlock_t config_lock; /* config block lock */
spinlock_t mdi_access_lock; /* mdi lock */
struct timer_list watchdog_timer; /* watchdog timer id */
/* non-tx commands parameters */
struct timer_list nontx_timer_id; /* non-tx timer id */
struct list_head non_tx_cmd_list;
non_tx_cmd_state_t non_tx_command_state;
nxmit_cb_entry_t *same_cmd_entry[CB_MAX_NONTX_CMD];
enum next_cu_cmd_e next_cu_cmd;
/* Zero Locking Algorithm data members */
enum zlock_state_e zlock_state;
u8 zlock_read_data[16]; /* number of times each value 0-15 was read */
u16 zlock_read_cnt; /* counts number of reads */
ulong zlock_sleep_cnt; /* keeps track of "sleep" time */
u8 config[CB_CFIG_BYTE_COUNT + CB_CFIG_D102_BYTE_COUNT];
/* IFS params */
u8 ifs_state;
u8 ifs_value;
struct cfg_params params; /* adapter's command line parameters */
u32 speed_duplex_caps; /* adapter's speed/duplex capabilities */
/* WOL params for ethtool */
u32 wolsupported;
u32 wolopts;
u16 ip_lbytes;
struct ethtool_lpbk_data loopback;
struct timer_list blink_timer; /* led blink timer id */
#ifdef CONFIG_PM
u32 pci_state[16];
#endif
#ifdef E100_CU_DEBUG
u8 last_cmd;
u8 last_sub_cmd;
#endif
};
#define E100_AUTONEG 0
#define E100_SPEED_10_HALF 1
#define E100_SPEED_10_FULL 2
#define E100_SPEED_100_HALF 3
#define E100_SPEED_100_FULL 4
/********* function prototypes *************/
extern int e100_open(struct net_device *);
extern int e100_close(struct net_device *);
extern void e100_isolate_driver(struct e100_private *bdp);
extern unsigned char e100_hw_init(struct e100_private *);
extern void e100_sw_reset(struct e100_private *bdp, u32 reset_cmd);
extern u8 e100_start_cu(struct e100_private *bdp, tcb_t *tcb);
extern void e100_free_non_tx_cmd(struct e100_private *bdp,
nxmit_cb_entry_t *non_tx_cmd);
extern nxmit_cb_entry_t *e100_alloc_non_tx_cmd(struct e100_private *bdp);
extern unsigned char e100_exec_non_cu_cmd(struct e100_private *bdp,
nxmit_cb_entry_t *cmd);
extern unsigned char e100_selftest(struct e100_private *bdp, u32 *st_timeout,
u32 *st_result);
extern unsigned char e100_get_link_state(struct e100_private *bdp);
extern unsigned char e100_wait_scb(struct e100_private *bdp);
extern void e100_deisolate_driver(struct e100_private *bdp, u8 full_reset);
extern unsigned char e100_configure_device(struct e100_private *bdp);
#ifdef E100_CU_DEBUG
extern unsigned char e100_cu_unknown_state(struct e100_private *bdp);
#endif
#define ROM_TEST_FAIL 0x01
#define REGISTER_TEST_FAIL 0x02
#define SELF_TEST_FAIL 0x04
#define TEST_TIMEOUT 0x08
enum test_offsets {
test_link,
test_eeprom,
test_self_test,
test_loopback_mac,
test_loopback_phy,
cable_diag,
max_test_res, /* must be last */
};
#endif
drivers/net/e100/e100_config.c deleted 100644 → 0
View file @ 02a38ad0
/*******************************************************************************
Copyright(c) 1999 - 2003 Intel Corporation. All rights reserved.
This program is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the Free
Software Foundation; either version 2 of the License, or (at your option)
any later version.
This program is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
this program; if not, write to the Free Software Foundation, Inc., 59
Temple Place - Suite 330, Boston, MA 02111-1307, USA.
The full GNU General Public License is included in this distribution in the
file called LICENSE.
Contact Information:
Linux NICS <linux.nics@intel.com>
Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
*******************************************************************************/
/**********************************************************************
* *
* INTEL CORPORATION *
* *
* This software is supplied under the terms of the license included *
* above. All use of this driver must be in accordance with the terms *
* of that license. *
* *
* Module Name: e100_config.c *
* *
* Abstract: Functions for configuring the network adapter. *
* *
* Environment: This file is intended to be specific to the Linux *
* operating system. *
* *
**********************************************************************/
#include "e100_config.h"
static void e100_config_long_rx(struct e100_private *bdp, unsigned char enable);
static const u8 def_config[] = {
CB_CFIG_BYTE_COUNT,
0x08, 0x00, 0x00, 0x00, 0x00, 0x32, 0x07, 0x01,
0x00, 0x2e, 0x00, 0x60, 0x00, 0xf2, 0xc8, 0x00,
0x40, 0xf2, 0x80, 0x3f, 0x05
};
/**
* e100_config_init_82557 - config the 82557 adapter
* @bdp: atapter's private data struct
*
* This routine will initialize the 82557 configure block.
* All other init functions will only set values that are
* different from the 82557 default.
*/
void
e100_config_init_82557(struct e100_private *bdp)
{
/* initialize config block */
memcpy(bdp->config, def_config, sizeof (def_config));
bdp->config[0] = CB_CFIG_BYTE_COUNT; /* just in case */
e100_config_ifs(bdp);
/*
* Enable extended statistical counters (82558 and up) and TCO counters
* (82559 and up) and set the statistical counters' mode in bdp
*
* stat. mode | TCO stat. bit (2) | Extended stat. bit (5)
* ------------------------------------------------------------------
* Basic (557) | 0 | 1
* ------------------------------------------------------------------
* Extended (558) | 0 | 0
* ------------------------------------------------------------------
* TCO (559) | 1 | 1
* ------------------------------------------------------------------
* Reserved | 1 | 0
* ------------------------------------------------------------------
*/
bdp->config[6] &= ~CB_CFIG_TCO_STAT;
bdp->config[6] |= CB_CFIG_EXT_STAT_DIS;
bdp->stat_mode = E100_BASIC_STATS;
/* Setup for MII or 503 operation. The CRS+CDT bit should only be set */
/* when operating in 503 mode. */
if (bdp->phy_addr == 32) {
bdp->config[8] &= ~CB_CFIG_503_MII;
bdp->config[15] |= CB_CFIG_CRS_OR_CDT;
} else {
bdp->config[8] |= CB_CFIG_503_MII;
bdp->config[15] &= ~CB_CFIG_CRS_OR_CDT;
}
e100_config_fc(bdp);
e100_config_force_dplx(bdp);
e100_config_promisc(bdp, false);
e100_config_mulcast_enbl(bdp, false);
}
static void
e100_config_init_82558(struct e100_private *bdp)
{
/* MWI enable. This should be turned on only if the adapter is a 82558/9
* and if the PCI command reg. has enabled the MWI bit. */
bdp->config[3] |= CB_CFIG_MWI_EN;
bdp->config[6] &= ~CB_CFIG_EXT_TCB_DIS;
if (bdp->rev_id >= D101MA_REV_ID) {
/* this is 82559 and up - enable TCO counters */
bdp->config[6] |= CB_CFIG_TCO_STAT;
bdp->config[6] |= CB_CFIG_EXT_STAT_DIS;
bdp->stat_mode = E100_TCO_STATS;
if ((bdp->rev_id < D102_REV_ID) &&
(bdp->params.b_params & PRM_XSUMRX) &&
(bdp->pdev->device != 0x1209)) {
bdp->flags |= DF_CSUM_OFFLOAD;
bdp->config[9] |= 1;
}
} else {
/* this is 82558 */
bdp->config[6] &= ~CB_CFIG_TCO_STAT;
bdp->config[6] &= ~CB_CFIG_EXT_STAT_DIS;
bdp->stat_mode = E100_EXTENDED_STATS;
}
e100_config_long_rx(bdp, true);
}
static void
e100_config_init_82550(struct e100_private *bdp)
{
/* The D102 chip allows for 32 config bytes. This value is
* supposed to be in Byte 0. Just add the extra bytes to
* what was already setup in the block. */
bdp->config[0] += CB_CFIG_D102_BYTE_COUNT;
/* now we need to enable the extended RFD. When this is
* enabled, the immediated receive data buffer starts at offset
* 32 from the RFD base address, instead of at offset 16. */
bdp->config[7] |= CB_CFIG_EXTENDED_RFD;
/* put the chip into D102 receive mode. This is necessary
* for any parsing and offloading features. */
bdp->config[22] = CB_CFIG_RECEIVE_GAMLA_MODE;
/* set the flag if checksum offloading was enabled */
if (bdp->params.b_params & PRM_XSUMRX) {
bdp->flags |= DF_CSUM_OFFLOAD;
}
}
/* Initialize the adapter's configure block */
void
e100_config_init(struct e100_private *bdp)
{
e100_config_init_82557(bdp);
if (bdp->flags & IS_BACHELOR)
e100_config_init_82558(bdp);
if (bdp->rev_id >= D102_REV_ID)
e100_config_init_82550(bdp);
}
/**
* e100_force_config - force a configure command
* @bdp: atapter's private data struct
*
* This routine will force a configure command to the adapter.
* The command will be executed in polled mode as interrupts
* are _disabled_ at this time.
*
* Returns:
* true: if the configure command was successfully issued and completed
* false: otherwise
*/
unsigned char
e100_force_config(struct e100_private *bdp)
{
spin_lock_bh(&(bdp->config_lock));
bdp->config[0] = CB_CFIG_BYTE_COUNT;
if (bdp->rev_id >= D102_REV_ID) {
/* The D102 chip allows for 32 config bytes. This value is
supposed to be in Byte 0. Just add the extra bytes to
what was already setup in the block. */
bdp->config[0] += CB_CFIG_D102_BYTE_COUNT;
}
spin_unlock_bh(&(bdp->config_lock));
// although we call config outside the lock, there is no
// race condition because config byte count has maximum value
return e100_config(bdp);
}
/**
* e100_config - issue a configure command
* @bdp: atapter's private data struct
*
* This routine will issue a configure command to the 82557.
* This command will be executed in polled mode as interrupts
* are _disabled_ at this time.
*
* Returns:
* true: if the configure command was successfully issued and completed
* false: otherwise
*/
unsigned char
e100_config(struct e100_private *bdp)
{
cb_header_t *pntcb_hdr;
unsigned char res = true;
nxmit_cb_entry_t *cmd;
if (bdp->config[0] == 0) {
goto exit;
}
if ((cmd = e100_alloc_non_tx_cmd(bdp)) == NULL) {
res = false;
goto exit;
}
pntcb_hdr = (cb_header_t *) cmd->non_tx_cmd;
pntcb_hdr->cb_cmd = __constant_cpu_to_le16(CB_CONFIGURE);
spin_lock_bh(&bdp->config_lock);
if (bdp->config[0] < CB_CFIG_MIN_PARAMS) {
bdp->config[0] = CB_CFIG_MIN_PARAMS;
}
/* Copy the device's config block to the device's memory */
memcpy(cmd->non_tx_cmd->ntcb.config.cfg_byte, bdp->config,
bdp->config[0]);
/* reset number of bytes to config next time */
bdp->config[0] = 0;
spin_unlock_bh(&bdp->config_lock);
res = e100_exec_non_cu_cmd(bdp, cmd);
exit:
if (netif_running(bdp->device))
netif_wake_queue(bdp->device);
return res;
}
/**
* e100_config_fc - config flow-control state
* @bdp: adapter's private data struct
*
* This routine will enable or disable flow control support in the adapter's
* config block. Flow control will be enable only if requested using the command
* line option, and if the link is flow-contorl capable (both us and the link
* partner). But, if link partner is capable of autoneg, but not capable of
* flow control, received PAUSE frames are still honored.
*/
void
e100_config_fc(struct e100_private *bdp)
{
unsigned char enable = false;
/* 82557 doesn't support fc. Don't touch this option */
if (!(bdp->flags & IS_BACHELOR))
return;
/* Enable fc if requested and if the link supports it */
if ((bdp->params.b_params & PRM_FC) && (bdp->flags &
(DF_LINK_FC_CAP | DF_LINK_FC_TX_ONLY))) {
enable = true;
}
spin_lock_bh(&(bdp->config_lock));
if (enable) {
if (bdp->flags & DF_LINK_FC_TX_ONLY) {
/* If link partner is capable of autoneg, but */
/* not capable of flow control, Received PAUSE */
/* frames are still honored, i.e., */
/* transmitted frames would be paused by */
/* incoming PAUSE frames */
bdp->config[16] = DFLT_NO_FC_DELAY_LSB;
bdp->config[17] = DFLT_NO_FC_DELAY_MSB;
bdp->config[19] &= ~(CB_CFIG_FC_RESTOP | CB_CFIG_FC_RESTART);
bdp->config[19] |= CB_CFIG_FC_REJECT;
bdp->config[19] &= ~CB_CFIG_TX_FC_DIS;
} else {
bdp->config[16] = DFLT_FC_DELAY_LSB;
bdp->config[17] = DFLT_FC_DELAY_MSB;
bdp->config[19] |= CB_CFIG_FC_OPTS;
bdp->config[19] &= ~CB_CFIG_TX_FC_DIS;
}
} else {
bdp->config[16] = DFLT_NO_FC_DELAY_LSB;
bdp->config[17] = DFLT_NO_FC_DELAY_MSB;
bdp->config[19] &= ~CB_CFIG_FC_OPTS;
bdp->config[19] |= CB_CFIG_TX_FC_DIS;
}
E100_CONFIG(bdp, 19);
spin_unlock_bh(&(bdp->config_lock));
return;
}
/**
* e100_config_promisc - configure promiscuous mode
* @bdp: atapter's private data struct
* @enable: should we enable this option or not
*
* This routine will enable or disable promiscuous mode
* in the adapter's config block.
*/
void
e100_config_promisc(struct e100_private *bdp, unsigned char enable)
{
spin_lock_bh(&(bdp->config_lock));
/* if in promiscuous mode, save bad frames */
if (enable) {
if (!(bdp->config[6] & CB_CFIG_SAVE_BAD_FRAMES)) {
bdp->config[6] |= CB_CFIG_SAVE_BAD_FRAMES;
E100_CONFIG(bdp, 6);
}
if (bdp->config[7] & (u8) BIT_0) {
bdp->config[7] &= (u8) (~BIT_0);
E100_CONFIG(bdp, 7);
}
if (!(bdp->config[15] & CB_CFIG_PROMISCUOUS)) {
bdp->config[15] |= CB_CFIG_PROMISCUOUS;
E100_CONFIG(bdp, 15);
}
} else { /* not in promiscuous mode */
if (bdp->config[6] & CB_CFIG_SAVE_BAD_FRAMES) {
bdp->config[6] &= ~CB_CFIG_SAVE_BAD_FRAMES;
E100_CONFIG(bdp, 6);
}
if (!(bdp->config[7] & (u8) BIT_0)) {
bdp->config[7] |= (u8) (BIT_0);
E100_CONFIG(bdp, 7);
}
if (bdp->config[15] & CB_CFIG_PROMISCUOUS) {
bdp->config[15] &= ~CB_CFIG_PROMISCUOUS;
E100_CONFIG(bdp, 15);
}
}
spin_unlock_bh(&(bdp->config_lock));
}
/**
* e100_config_mulcast_enbl - configure allmulti mode
* @bdp: atapter's private data struct
* @enable: should we enable this option or not
*
* This routine will enable or disable reception of all multicast packets
* in the adapter's config block.
*/
void
e100_config_mulcast_enbl(struct e100_private *bdp, unsigned char enable)
{
spin_lock_bh(&(bdp->config_lock));
/* this flag is used to enable receiving all multicast packet */
if (enable) {
if (!(bdp->config[21] & CB_CFIG_MULTICAST_ALL)) {
bdp->config[21] |= CB_CFIG_MULTICAST_ALL;
E100_CONFIG(bdp, 21);
}
} else {
if (bdp->config[21] & CB_CFIG_MULTICAST_ALL) {
bdp->config[21] &= ~CB_CFIG_MULTICAST_ALL;
E100_CONFIG(bdp, 21);
}
}
spin_unlock_bh(&(bdp->config_lock));
}
/**
* e100_config_ifs - configure the IFS parameter
* @bdp: atapter's private data struct
*
* This routine will configure the adaptive IFS value
* in the adapter's config block. IFS values are only
* relevant in half duplex, so set to 0 in full duplex.
*/
void
e100_config_ifs(struct e100_private *bdp)
{
u8 value = 0;
spin_lock_bh(&(bdp->config_lock));
/* IFS value is only needed to be specified at half-duplex mode */
if (bdp->cur_dplx_mode == HALF_DUPLEX) {
value = (u8) bdp->ifs_value;
}
if (bdp->config[2] != value) {
bdp->config[2] = value;
E100_CONFIG(bdp, 2);
}
spin_unlock_bh(&(bdp->config_lock));
}
/**
* e100_config_force_dplx - configure the forced full duplex mode
* @bdp: atapter's private data struct
*
* This routine will enable or disable force full duplex
* in the adapter's config block. If the PHY is 503, and
* the duplex is full, consider the adapter forced.
*/
void
e100_config_force_dplx(struct e100_private *bdp)
{
spin_lock_bh(&(bdp->config_lock));
/* We must force full duplex on if we are using PHY 0, and we are */
/* supposed to run in FDX mode. We do this because the e100 has only */
/* one FDX# input pin, and that pin will be connected to PHY 1. */
/* Changed the 'if' condition below to fix performance problem * at 10
* full. The Phy was getting forced to full duplex while the MAC * was
* not, because the cur_dplx_mode was not being set to 2 by SetupPhy. *
* This is how the condition was, initially. * This has been changed so
* that the MAC gets forced to full duplex * simply if the user has
* forced full duplex. * * if (( bdp->phy_addr == 0 ) && (
* bdp->cur_dplx_mode == 2 )) */
/* The rest of the fix is in the PhyDetect code. */
if ((bdp->params.e100_speed_duplex == E100_SPEED_10_FULL) ||
(bdp->params.e100_speed_duplex == E100_SPEED_100_FULL) ||
((bdp->phy_addr == 32) && (bdp->cur_dplx_mode == FULL_DUPLEX))) {
if (!(bdp->config[19] & (u8) CB_CFIG_FORCE_FDX)) {
bdp->config[19] |= (u8) CB_CFIG_FORCE_FDX;
E100_CONFIG(bdp, 19);
}
} else {
if (bdp->config[19] & (u8) CB_CFIG_FORCE_FDX) {
bdp->config[19] &= (u8) (~CB_CFIG_FORCE_FDX);
E100_CONFIG(bdp, 19);
}
}
spin_unlock_bh(&(bdp->config_lock));
}
/**
* e100_config_long_rx
* @bdp: atapter's private data struct
* @enable: should we enable this option or not
*
* This routine will enable or disable reception of larger packets.
* This is needed by VLAN implementations.
*/
static void
e100_config_long_rx(struct e100_private *bdp, unsigned char enable)
{
if (enable) {
if (!(bdp->config[18] & CB_CFIG_LONG_RX_OK)) {
bdp->config[18] |= CB_CFIG_LONG_RX_OK;
E100_CONFIG(bdp, 18);
}
} else {
if ((bdp->config[18] & CB_CFIG_LONG_RX_OK)) {
bdp->config[18] &= ~CB_CFIG_LONG_RX_OK;
E100_CONFIG(bdp, 18);
}
}
}
/**
* e100_config_wol
* @bdp: atapter's private data struct
*
* This sets configuration options for PHY and Magic Packet WoL
*/
void
e100_config_wol(struct e100_private *bdp)
{
spin_lock_bh(&(bdp->config_lock));
if (bdp->wolopts & WAKE_PHY) {
bdp->config[9] |= CB_LINK_STATUS_WOL;
}
else {
/* Disable PHY WoL */
bdp->config[9] &= ~CB_LINK_STATUS_WOL;
}
if (bdp->wolopts & WAKE_MAGIC) {
bdp->config[19] &= ~CB_DISABLE_MAGPAK_WAKE;
}
else {
/* Disable Magic Packet WoL */
bdp->config[19] |= CB_DISABLE_MAGPAK_WAKE;
}
E100_CONFIG(bdp, 19);
spin_unlock_bh(&(bdp->config_lock));
}
void
e100_config_vlan_drop(struct e100_private *bdp, unsigned char enable)
{
spin_lock_bh(&(bdp->config_lock));
if (enable) {
if (!(bdp->config[22] & CB_CFIG_VLAN_DROP_ENABLE)) {
bdp->config[22] |= CB_CFIG_VLAN_DROP_ENABLE;
E100_CONFIG(bdp, 22);
}
} else {
if ((bdp->config[22] & CB_CFIG_VLAN_DROP_ENABLE)) {
bdp->config[22] &= ~CB_CFIG_VLAN_DROP_ENABLE;
E100_CONFIG(bdp, 22);
}
}
spin_unlock_bh(&(bdp->config_lock));
}
/**
* e100_config_loopback_mode
* @bdp: atapter's private data struct
* @mode: loopback mode(phy/mac/none)
*
*/
unsigned char
e100_config_loopback_mode(struct e100_private *bdp, u8 mode)
{
unsigned char bc_changed = false;
u8 config_byte;
spin_lock_bh(&(bdp->config_lock));
switch (mode) {
case NO_LOOPBACK:
config_byte = CB_CFIG_LOOPBACK_NORMAL;
break;
case MAC_LOOPBACK:
config_byte = CB_CFIG_LOOPBACK_INTERNAL;
break;
case PHY_LOOPBACK:
config_byte = CB_CFIG_LOOPBACK_EXTERNAL;
break;
default:
printk(KERN_NOTICE "e100: e100_config_loopback_mode: "
"Invalid argument 'mode': %d\n", mode);
goto exit;
}
if ((bdp->config[10] & CB_CFIG_LOOPBACK_MODE) != config_byte) {
bdp->config[10] &= (~CB_CFIG_LOOPBACK_MODE);
bdp->config[10] |= config_byte;
E100_CONFIG(bdp, 10);
bc_changed = true;
}
exit:
spin_unlock_bh(&(bdp->config_lock));
return bc_changed;
}
unsigned char
e100_config_tcb_ext_enable(struct e100_private *bdp, unsigned char enable)
{
unsigned char bc_changed = false;
spin_lock_bh(&(bdp->config_lock));
if (enable) {
if (bdp->config[6] & CB_CFIG_EXT_TCB_DIS) {
bdp->config[6] &= (~CB_CFIG_EXT_TCB_DIS);
E100_CONFIG(bdp, 6);
bc_changed = true;
}
} else {
if (!(bdp->config[6] & CB_CFIG_EXT_TCB_DIS)) {
bdp->config[6] |= CB_CFIG_EXT_TCB_DIS;
E100_CONFIG(bdp, 6);
bc_changed = true;
}
}
spin_unlock_bh(&(bdp->config_lock));
return bc_changed;
}
unsigned char
e100_config_dynamic_tbd(struct e100_private *bdp, unsigned char enable)
{
unsigned char bc_changed = false;
spin_lock_bh(&(bdp->config_lock));
if (enable) {
if (!(bdp->config[7] & CB_CFIG_DYNTBD_EN)) {
bdp->config[7] |= CB_CFIG_DYNTBD_EN;
E100_CONFIG(bdp, 7);
bc_changed = true;
}
} else {
if (bdp->config[7] & CB_CFIG_DYNTBD_EN) {
bdp->config[7] &= (~CB_CFIG_DYNTBD_EN);
E100_CONFIG(bdp, 7);
bc_changed = true;
}
}
spin_unlock_bh(&(bdp->config_lock));
return bc_changed;
}
drivers/net/e100/e100_config.h deleted 100644 → 0
View file @ 02a38ad0
/*******************************************************************************
Copyright(c) 1999 - 2003 Intel Corporation. All rights reserved.
This program is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the Free
Software Foundation; either version 2 of the License, or (at your option)
any later version.
This program is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
this program; if not, write to the Free Software Foundation, Inc., 59
Temple Place - Suite 330, Boston, MA 02111-1307, USA.
The full GNU General Public License is included in this distribution in the
file called LICENSE.
Contact Information:
Linux NICS <linux.nics@intel.com>
Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
*******************************************************************************/
#ifndef _E100_CONFIG_INC_
#define _E100_CONFIG_INC_
#include "e100.h"
#define E100_CONFIG(bdp, X) ((bdp)->config[0] = max_t(u8, (bdp)->config[0], (X)+1))
#define CB_CFIG_MIN_PARAMS 8
/* byte 0 bit definitions*/
#define CB_CFIG_BYTE_COUNT_MASK BIT_0_5 /* Byte count occupies bit 5-0 */
/* byte 1 bit definitions*/
#define CB_CFIG_RXFIFO_LIMIT_MASK BIT_0_4 /* RxFifo limit mask */
#define CB_CFIG_TXFIFO_LIMIT_MASK BIT_4_7 /* TxFifo limit mask */
/* byte 2 bit definitions -- ADAPTIVE_IFS*/
/* word 3 bit definitions -- RESERVED*/
/* Changed for 82558 enhancements */
/* byte 3 bit definitions */
#define CB_CFIG_MWI_EN BIT_0 /* Enable MWI on PCI bus */
#define CB_CFIG_TYPE_EN BIT_1 /* Type Enable */
#define CB_CFIG_READAL_EN BIT_2 /* Enable Read Align */
#define CB_CFIG_TERMCL_EN BIT_3 /* Cache line write */
/* byte 4 bit definitions*/
#define CB_CFIG_RX_MIN_DMA_MASK BIT_0_6 /* Rx minimum DMA count mask */
/* byte 5 bit definitions*/
#define CB_CFIG_TX_MIN_DMA_MASK BIT_0_6 /* Tx minimum DMA count mask */
#define CB_CFIG_DMBC_EN BIT_7 /* Enable Tx/Rx min. DMA counts */
/* Changed for 82558 enhancements */
/* byte 6 bit definitions*/
#define CB_CFIG_LATE_SCB BIT_0 /* Update SCB After New Tx Start */
#define CB_CFIG_DIRECT_DMA_DIS BIT_1 /* Direct DMA mode */
#define CB_CFIG_TNO_INT BIT_2 /* Tx Not OK Interrupt */
#define CB_CFIG_TCO_STAT BIT_2 /* TCO statistics in 559 and above */
#define CB_CFIG_CI_INT BIT_3 /* Command Complete Interrupt */
#define CB_CFIG_EXT_TCB_DIS BIT_4 /* Extended TCB */
#define CB_CFIG_EXT_STAT_DIS BIT_5 /* Extended Stats */
#define CB_CFIG_SAVE_BAD_FRAMES BIT_7 /* Save Bad Frames Enabled */
/* byte 7 bit definitions*/
#define CB_CFIG_DISC_SHORT_FRAMES BIT_0 /* Discard Short Frames */
#define CB_CFIG_DYNTBD_EN BIT_7 /* Enable dynamic TBD */
/* Enable extended RFD's on D102 */
#define CB_CFIG_EXTENDED_RFD BIT_5
/* byte 8 bit definitions*/
#define CB_CFIG_503_MII BIT_0 /* 503 vs. MII mode */
/* byte 9 bit definitions -- pre-defined all zeros*/
#define CB_LINK_STATUS_WOL BIT_5
/* byte 10 bit definitions*/
#define CB_CFIG_NO_SRCADR BIT_3 /* No Source Address Insertion */
#define CB_CFIG_PREAMBLE_LEN BIT_4_5 /* Preamble Length */
#define CB_CFIG_LOOPBACK_MODE BIT_6_7 /* Loopback Mode */
#define CB_CFIG_LOOPBACK_NORMAL 0
#define CB_CFIG_LOOPBACK_INTERNAL BIT_6
#define CB_CFIG_LOOPBACK_EXTERNAL BIT_6_7
/* byte 11 bit definitions*/
#define CB_CFIG_LINEAR_PRIORITY BIT_0_2 /* Linear Priority */
/* byte 12 bit definitions*/
#define CB_CFIG_LINEAR_PRI_MODE BIT_0 /* Linear Priority mode */
#define CB_CFIG_IFS_MASK BIT_4_7 /* Interframe Spacing mask */
/* byte 13 bit definitions -- pre-defined all zeros*/
/* byte 14 bit definitions -- pre-defined 0xf2*/
/* byte 15 bit definitions*/
#define CB_CFIG_PROMISCUOUS BIT_0 /* Promiscuous Mode Enable */
#define CB_CFIG_BROADCAST_DIS BIT_1 /* Broadcast Mode Disable */
#define CB_CFIG_CRS_OR_CDT BIT_7 /* CRS Or CDT */
/* byte 16 bit definitions -- pre-defined all zeros*/
#define DFLT_FC_DELAY_LSB 0x1f /* Delay for outgoing Pause frames */
#define DFLT_NO_FC_DELAY_LSB 0x00 /* no flow control default value */
/* byte 17 bit definitions -- pre-defined 0x40*/
#define DFLT_FC_DELAY_MSB 0x01 /* Delay for outgoing Pause frames */
#define DFLT_NO_FC_DELAY_MSB 0x40 /* no flow control default value */
/* byte 18 bit definitions*/
#define CB_CFIG_STRIPPING BIT_0 /* Padding Disabled */
#define CB_CFIG_PADDING BIT_1 /* Padding Disabled */
#define CB_CFIG_CRC_IN_MEM BIT_2 /* Transfer CRC To Memory */
/* byte 19 bit definitions*/
#define CB_CFIG_TX_ADDR_WAKE BIT_0 /* Address Wakeup */
#define CB_DISABLE_MAGPAK_WAKE BIT_1 /* Magic Packet Wakeup disable */
/* Changed TX_FC_EN to TX_FC_DIS because 0 enables, 1 disables. Jul 8, 1999 */
#define CB_CFIG_TX_FC_DIS BIT_2 /* Tx Flow Control Disable */
#define CB_CFIG_FC_RESTOP BIT_3 /* Rx Flow Control Restop */
#define CB_CFIG_FC_RESTART BIT_4 /* Rx Flow Control Restart */
#define CB_CFIG_FC_REJECT BIT_5 /* Rx Flow Control Restart */
#define CB_CFIG_FC_OPTS (CB_CFIG_FC_RESTOP | CB_CFIG_FC_RESTART | CB_CFIG_FC_REJECT)
/* end 82558/9 specifics */
#define CB_CFIG_FORCE_FDX BIT_6 /* Force Full Duplex */
#define CB_CFIG_FDX_ENABLE BIT_7 /* Full Duplex Enabled */
/* byte 20 bit definitions*/
#define CB_CFIG_MULTI_IA BIT_6 /* Multiple IA Addr */
/* byte 21 bit definitions*/
#define CB_CFIG_MULTICAST_ALL BIT_3 /* Multicast All */
/* byte 22 bit defines */
#define CB_CFIG_RECEIVE_GAMLA_MODE BIT_0 /* D102 receive mode */
#define CB_CFIG_VLAN_DROP_ENABLE BIT_1 /* vlan stripping */
#define CB_CFIG_LONG_RX_OK BIT_3
#define NO_LOOPBACK 0
#define MAC_LOOPBACK 0x01
#define PHY_LOOPBACK 0x02
/* function prototypes */
extern void e100_config_init(struct e100_private *bdp);
extern void e100_config_init_82557(struct e100_private *bdp);
extern unsigned char e100_force_config(struct e100_private *bdp);
extern unsigned char e100_config(struct e100_private *bdp);
extern void e100_config_fc(struct e100_private *bdp);
extern void e100_config_promisc(struct e100_private *bdp, unsigned char enable);
extern void e100_config_brdcast_dsbl(struct e100_private *bdp);
extern void e100_config_mulcast_enbl(struct e100_private *bdp,
unsigned char enable);
extern void e100_config_ifs(struct e100_private *bdp);
extern void e100_config_force_dplx(struct e100_private *bdp);
extern u8 e100_config_loopback_mode(struct e100_private *bdp, u8 mode);
extern u8 e100_config_dynamic_tbd(struct e100_private *bdp, u8 enable);
extern u8 e100_config_tcb_ext_enable(struct e100_private *bdp, u8 enable);
extern void e100_config_vlan_drop(struct e100_private *bdp, unsigned char enable);
#endif /* _E100_CONFIG_INC_ */
drivers/net/e100/e100_eeprom.c deleted 100644 → 0
View file @ 02a38ad0
/*******************************************************************************
Copyright(c) 1999 - 2003 Intel Corporation. All rights reserved.
This program is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the Free
Software Foundation; either version 2 of the License, or (at your option)
any later version.
This program is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
this program; if not, write to the Free Software Foundation, Inc., 59
Temple Place - Suite 330, Boston, MA 02111-1307, USA.
The full GNU General Public License is included in this distribution in the
file called LICENSE.
Contact Information:
Linux NICS <linux.nics@intel.com>
Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
*******************************************************************************/
/**********************************************************************
* *
* INTEL CORPORATION *
* *
* This software is supplied under the terms of the license included *
* above. All use of this driver must be in accordance with the terms *
* of that license. *
* *
* Module Name: e100_eeprom.c *
* *
* Abstract: This module contains routines to read and write to a *
* serial EEPROM *
* *
* Environment: This file is intended to be specific to the Linux *
* operating system. *
* *
**********************************************************************/
#include "e100.h"
#define CSR_EEPROM_CONTROL_FIELD(bdp) ((bdp)->scb->scb_eprm_cntrl)
#define CSR_GENERAL_CONTROL2_FIELD(bdp) \
((bdp)->scb->scb_ext.d102_scb.scb_gen_ctrl2)
#define EEPROM_STALL_TIME 4
#define EEPROM_CHECKSUM ((u16) 0xBABA)
#define EEPROM_MAX_WORD_SIZE 256
void e100_eeprom_cleanup(struct e100_private *adapter);
u16 e100_eeprom_calculate_chksum(struct e100_private *adapter);
static void e100_eeprom_write_word(struct e100_private *adapter, u16 reg,
u16 data);
void e100_eeprom_write_block(struct e100_private *adapter, u16 start, u16 *data,
u16 size);
u16 e100_eeprom_size(struct e100_private *adapter);
u16 e100_eeprom_read(struct e100_private *adapter, u16 reg);
static void shift_out_bits(struct e100_private *adapter, u16 data, u16 count);
static u16 shift_in_bits(struct e100_private *adapter);
static void raise_clock(struct e100_private *adapter, u16 *x);
static void lower_clock(struct e100_private *adapter, u16 *x);
static u16 eeprom_wait_cmd_done(struct e100_private *adapter);
static void eeprom_stand_by(struct e100_private *adapter);
//----------------------------------------------------------------------------------------
// Procedure: eeprom_set_semaphore
//
// Description: This function set (write 1) Gamla EEPROM semaphore bit (bit 23 word 0x1C in the CSR).
//
// Arguments:
// Adapter - Adapter context
//
// Returns: true if success
// else return false
//
//----------------------------------------------------------------------------------------
inline u8
eeprom_set_semaphore(struct e100_private *adapter)
{
u16 data = 0;
unsigned long expiration_time = jiffies + HZ / 100 + 1;
do {
// Get current value of General Control 2
data = readb(&CSR_GENERAL_CONTROL2_FIELD(adapter));
// Set bit 23 word 0x1C in the CSR.
data |= SCB_GCR2_EEPROM_ACCESS_SEMAPHORE;
writeb(data, &CSR_GENERAL_CONTROL2_FIELD(adapter));
// Check to see if this bit set or not.
data = readb(&CSR_GENERAL_CONTROL2_FIELD(adapter));
if (data & SCB_GCR2_EEPROM_ACCESS_SEMAPHORE) {
return true;
}
if (time_before(jiffies, expiration_time))
yield();
else
return false;
} while (true);
}
//----------------------------------------------------------------------------------------
// Procedure: eeprom_reset_semaphore
//
// Description: This function reset (write 0) Gamla EEPROM semaphore bit
// (bit 23 word 0x1C in the CSR).
//
// Arguments: struct e100_private * adapter - Adapter context
//----------------------------------------------------------------------------------------
inline void
eeprom_reset_semaphore(struct e100_private *adapter)
{
u16 data = 0;
data = readb(&CSR_GENERAL_CONTROL2_FIELD(adapter));
data &= ~(SCB_GCR2_EEPROM_ACCESS_SEMAPHORE);
writeb(data, &CSR_GENERAL_CONTROL2_FIELD(adapter));
}
//----------------------------------------------------------------------------------------
// Procedure: e100_eeprom_size
//
// Description: This routine determines the size of the EEPROM. This value should be
// checked for validity - ie. is it too big or too small. The size returned
// is then passed to the read/write functions.
//
// Returns:
// Size of the eeprom, or zero if an error occurred
//----------------------------------------------------------------------------------------
u16
e100_eeprom_size(struct e100_private *adapter)
{
u16 x, size = 1; // must be one to accumulate a product
// if we've already stored this data, read from memory
if (adapter->eeprom_size) {
return adapter->eeprom_size;
}
// otherwise, read from the eeprom
// Set EEPROM semaphore.
if (adapter->rev_id >= D102_REV_ID) {
if (!eeprom_set_semaphore(adapter))
return 0;
}
// enable the eeprom by setting EECS.
x = readw(&CSR_EEPROM_CONTROL_FIELD(adapter));
x &= ~(EEDI | EEDO | EESK);
x |= EECS;
writew(x, &CSR_EEPROM_CONTROL_FIELD(adapter));
// write the read opcode
shift_out_bits(adapter, EEPROM_READ_OPCODE, 3);
// experiment to discover the size of the eeprom. request register zero
// and wait for the eeprom to tell us it has accepted the entire address.
x = readw(&CSR_EEPROM_CONTROL_FIELD(adapter));
do {
size *= 2; // each bit of address doubles eeprom size
x |= EEDO; // set bit to detect "dummy zero"
x &= ~EEDI; // address consists of all zeros
writew(x, &CSR_EEPROM_CONTROL_FIELD(adapter));
readw(&(adapter->scb->scb_status));
udelay(EEPROM_STALL_TIME);
raise_clock(adapter, &x);
lower_clock(adapter, &x);
// check for "dummy zero"
x = readw(&CSR_EEPROM_CONTROL_FIELD(adapter));
if (size > EEPROM_MAX_WORD_SIZE) {
size = 0;
break;
}
} while (x & EEDO);
// read in the value requested
(void) shift_in_bits(adapter);
e100_eeprom_cleanup(adapter);
// Clear EEPROM Semaphore.
if (adapter->rev_id >= D102_REV_ID) {
eeprom_reset_semaphore(adapter);
}
return size;
}
//----------------------------------------------------------------------------------------
// Procedure: eeprom_address_size
//
// Description: determines the number of bits in an address for the eeprom acceptable
// values are 64, 128, and 256
// Arguments: size of the eeprom
// Returns: bits in an address for that size eeprom
//----------------------------------------------------------------------------------------
static inline int
eeprom_address_size(u16 size)
{
int isize = size;
return (ffs(isize) - 1);
}
//----------------------------------------------------------------------------------------
// Procedure: e100_eeprom_read
//
// Description: This routine serially reads one word out of the EEPROM.
//
// Arguments:
// adapter - our adapter context
// reg - EEPROM word to read.
//
// Returns:
// Contents of EEPROM word (reg).
//----------------------------------------------------------------------------------------
u16
e100_eeprom_read(struct e100_private *adapter, u16 reg)
{
u16 x, data, bits;
// Set EEPROM semaphore.
if (adapter->rev_id >= D102_REV_ID) {
if (!eeprom_set_semaphore(adapter))
return 0;
}
// eeprom size is initialized to zero
if (!adapter->eeprom_size)
adapter->eeprom_size = e100_eeprom_size(adapter);
bits = eeprom_address_size(adapter->eeprom_size);
// select EEPROM, reset bits, set EECS
x = readw(&CSR_EEPROM_CONTROL_FIELD(adapter));
x &= ~(EEDI | EEDO | EESK);
x |= EECS;
writew(x, &CSR_EEPROM_CONTROL_FIELD(adapter));
// write the read opcode and register number in that order
// The opcode is 3bits in length, reg is 'bits' bits long
shift_out_bits(adapter, EEPROM_READ_OPCODE, 3);
shift_out_bits(adapter, reg, bits);
// Now read the data (16 bits) in from the selected EEPROM word
data = shift_in_bits(adapter);
e100_eeprom_cleanup(adapter);
// Clear EEPROM Semaphore.
if (adapter->rev_id >= D102_REV_ID) {
eeprom_reset_semaphore(adapter);
}
return data;
}
//----------------------------------------------------------------------------------------
// Procedure: shift_out_bits
//
// Description: This routine shifts data bits out to the EEPROM.
//
// Arguments:
// data - data to send to the EEPROM.
// count - number of data bits to shift out.
//
// Returns: (none)
//----------------------------------------------------------------------------------------
static void
shift_out_bits(struct e100_private *adapter, u16 data, u16 count)
{
u16 x, mask;
mask = 1 << (count - 1);
x = readw(&CSR_EEPROM_CONTROL_FIELD(adapter));
x &= ~(EEDO | EEDI);
do {
x &= ~EEDI;
if (data & mask)
x |= EEDI;
writew(x, &CSR_EEPROM_CONTROL_FIELD(adapter));
readw(&(adapter->scb->scb_status)); /* flush command to card */
udelay(EEPROM_STALL_TIME);
raise_clock(adapter, &x);
lower_clock(adapter, &x);
mask = mask >> 1;
} while (mask);
x &= ~EEDI;
writew(x, &CSR_EEPROM_CONTROL_FIELD(adapter));
}
//----------------------------------------------------------------------------------------
// Procedure: raise_clock
//
// Description: This routine raises the EEPROM's clock input (EESK)
//
// Arguments:
// x - Ptr to the EEPROM control register's current value
//
// Returns: (none)
//----------------------------------------------------------------------------------------
void
raise_clock(struct e100_private *adapter, u16 *x)
{
*x = *x | EESK;
writew(*x, &CSR_EEPROM_CONTROL_FIELD(adapter));
readw(&(adapter->scb->scb_status)); /* flush command to card */
udelay(EEPROM_STALL_TIME);
}
//----------------------------------------------------------------------------------------
// Procedure: lower_clock
//
// Description: This routine lower's the EEPROM's clock input (EESK)
//
// Arguments:
// x - Ptr to the EEPROM control register's current value
//
// Returns: (none)
//----------------------------------------------------------------------------------------
void
lower_clock(struct e100_private *adapter, u16 *x)
{
*x = *x & ~EESK;
writew(*x, &CSR_EEPROM_CONTROL_FIELD(adapter));
readw(&(adapter->scb->scb_status)); /* flush command to card */
udelay(EEPROM_STALL_TIME);
}
//----------------------------------------------------------------------------------------
// Procedure: shift_in_bits
//
// Description: This routine shifts data bits in from the EEPROM.
//
// Arguments:
//
// Returns:
// The contents of that particular EEPROM word
//----------------------------------------------------------------------------------------
static u16
shift_in_bits(struct e100_private *adapter)
{
u16 x, d, i;
x = readw(&CSR_EEPROM_CONTROL_FIELD(adapter));
x &= ~(EEDO | EEDI);
d = 0;
for (i = 0; i < 16; i++) {
d <<= 1;
raise_clock(adapter, &x);
x = readw(&CSR_EEPROM_CONTROL_FIELD(adapter));
x &= ~EEDI;
if (x & EEDO)
d |= 1;
lower_clock(adapter, &x);
}
return d;
}
//----------------------------------------------------------------------------------------
// Procedure: e100_eeprom_cleanup
//
// Description: This routine returns the EEPROM to an idle state
//----------------------------------------------------------------------------------------
void
e100_eeprom_cleanup(struct e100_private *adapter)
{
u16 x;
x = readw(&CSR_EEPROM_CONTROL_FIELD(adapter));
x &= ~(EECS | EEDI);
writew(x, &CSR_EEPROM_CONTROL_FIELD(adapter));
raise_clock(adapter, &x);
lower_clock(adapter, &x);
}
//**********************************************************************************
// Procedure: e100_eeprom_update_chksum
//
// Description: Calculates the checksum and writes it to the EEProm.
// It calculates the checksum accroding to the formula:
// Checksum = 0xBABA - (sum of first 63 words).
//
//-----------------------------------------------------------------------------------
u16
e100_eeprom_calculate_chksum(struct e100_private *adapter)
{
u16 idx, xsum_index, checksum = 0;
// eeprom size is initialized to zero
if (!adapter->eeprom_size)
adapter->eeprom_size = e100_eeprom_size(adapter);
xsum_index = adapter->eeprom_size - 1;
for (idx = 0; idx < xsum_index; idx++)
checksum += e100_eeprom_read(adapter, idx);
checksum = EEPROM_CHECKSUM - checksum;
return checksum;
}
//----------------------------------------------------------------------------------------
// Procedure: e100_eeprom_write_word
//
// Description: This routine writes a word to a specific EEPROM location without.
// taking EEPROM semaphore and updating checksum.
// Use e100_eeprom_write_block for the EEPROM update
// Arguments: reg - The EEPROM word that we are going to write to.
// data - The data (word) that we are going to write to the EEPROM.
//----------------------------------------------------------------------------------------
static void
e100_eeprom_write_word(struct e100_private *adapter, u16 reg, u16 data)
{
u16 x;
u16 bits;
bits = eeprom_address_size(adapter->eeprom_size);
/* select EEPROM, mask off ASIC and reset bits, set EECS */
x = readw(&CSR_EEPROM_CONTROL_FIELD(adapter));
x &= ~(EEDI | EEDO | EESK);
writew(x, &CSR_EEPROM_CONTROL_FIELD(adapter));
readw(&(adapter->scb->scb_status)); /* flush command to card */
udelay(EEPROM_STALL_TIME);
x |= EECS;
writew(x, &CSR_EEPROM_CONTROL_FIELD(adapter));
shift_out_bits(adapter, EEPROM_EWEN_OPCODE, 5);
shift_out_bits(adapter, reg, (u16) (bits - 2));
if (!eeprom_wait_cmd_done(adapter))
return;
/* write the new word to the EEPROM & send the write opcode the EEPORM */
shift_out_bits(adapter, EEPROM_WRITE_OPCODE, 3);
/* select which word in the EEPROM that we are writing to */
shift_out_bits(adapter, reg, bits);
/* write the data to the selected EEPROM word */
shift_out_bits(adapter, data, 16);
if (!eeprom_wait_cmd_done(adapter))
return;
shift_out_bits(adapter, EEPROM_EWDS_OPCODE, 5);
shift_out_bits(adapter, reg, (u16) (bits - 2));
if (!eeprom_wait_cmd_done(adapter))
return;
e100_eeprom_cleanup(adapter);
}
//----------------------------------------------------------------------------------------
// Procedure: e100_eeprom_write_block
//
// Description: This routine writes a block of words starting from specified EEPROM
// location and updates checksum
// Arguments: reg - The EEPROM word that we are going to write to.
// data - The data (word) that we are going to write to the EEPROM.
//----------------------------------------------------------------------------------------
void
e100_eeprom_write_block(struct e100_private *adapter, u16 start, u16 *data,
u16 size)
{
u16 checksum;
u16 i;
if (!adapter->eeprom_size)
adapter->eeprom_size = e100_eeprom_size(adapter);
// Set EEPROM semaphore.
if (adapter->rev_id >= D102_REV_ID) {
if (!eeprom_set_semaphore(adapter))
return;
}
for (i = 0; i < size; i++) {
e100_eeprom_write_word(adapter, start + i, data[i]);
}
//Update checksum
checksum = e100_eeprom_calculate_chksum(adapter);
e100_eeprom_write_word(adapter, (adapter->eeprom_size - 1), checksum);
// Clear EEPROM Semaphore.
if (adapter->rev_id >= D102_REV_ID) {
eeprom_reset_semaphore(adapter);
}
}
//----------------------------------------------------------------------------------------
// Procedure: eeprom_wait_cmd_done
//
// Description: This routine waits for the the EEPROM to finish its command.
// Specifically, it waits for EEDO (data out) to go high.
// Returns: true - If the command finished
// false - If the command never finished (EEDO stayed low)
//----------------------------------------------------------------------------------------
static u16
eeprom_wait_cmd_done(struct e100_private *adapter)
{
u16 x;
unsigned long expiration_time = jiffies + HZ / 100 + 1;
eeprom_stand_by(adapter);
do {
rmb();
x = readw(&CSR_EEPROM_CONTROL_FIELD(adapter));
if (x & EEDO)
return true;
if (time_before(jiffies, expiration_time))
yield();
else
return false;
} while (true);
}
//----------------------------------------------------------------------------------------
// Procedure: eeprom_stand_by
//
// Description: This routine lowers the EEPROM chip select (EECS) for a few microseconds.
//----------------------------------------------------------------------------------------
static void
eeprom_stand_by(struct e100_private *adapter)
{
u16 x;
x = readw(&CSR_EEPROM_CONTROL_FIELD(adapter));
x &= ~(EECS | EESK);
writew(x, &CSR_EEPROM_CONTROL_FIELD(adapter));
readw(&(adapter->scb->scb_status)); /* flush command to card */
udelay(EEPROM_STALL_TIME);
x |= EECS;
writew(x, &CSR_EEPROM_CONTROL_FIELD(adapter));
readw(&(adapter->scb->scb_status)); /* flush command to card */
udelay(EEPROM_STALL_TIME);
}
drivers/net/e100/e100_main.c deleted 100644 → 0
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drivers/net/e100/e100_phy.c deleted 100644 → 0
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/*******************************************************************************
Copyright(c) 1999 - 2003 Intel Corporation. All rights reserved.
This program is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the Free
Software Foundation; either version 2 of the License, or (at your option)
any later version.
This program is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
this program; if not, write to the Free Software Foundation, Inc., 59
Temple Place - Suite 330, Boston, MA 02111-1307, USA.
The full GNU General Public License is included in this distribution in the
file called LICENSE.
Contact Information:
Linux NICS <linux.nics@intel.com>
Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
*******************************************************************************/
#include "e100_phy.h"
void e100_handle_zlock(struct e100_private *bdp);
/*
* Procedure: e100_mdi_write
*
* Description: This routine will write a value to the specified MII register
* of an external MDI compliant device (e.g. PHY 100). The
* command will execute in polled mode.
*
* Arguments:
* bdp - Ptr to this card's e100_bdconfig structure
* reg_addr - The MII register that we are writing to
* phy_addr - The MDI address of the Phy component.
* data - The value that we are writing to the MII register.
*
* Returns:
* NOTHING
*/
int
e100_mdi_write(struct e100_private *bdp, u32 reg_addr, u32 phy_addr, u16 data)
{
int e100_retry;
u32 temp_val;
unsigned int mdi_cntrl;
spin_lock_bh(&bdp->mdi_access_lock);
temp_val = (((u32) data) | (reg_addr << 16) |
(phy_addr << 21) | (MDI_WRITE << 26));
writel(temp_val, &bdp->scb->scb_mdi_cntrl);
readw(&bdp->scb->scb_status);
/* wait 20usec before checking status */
udelay(20);
/* poll for the mdi write to complete */
e100_retry = E100_CMD_WAIT;
while ((!((mdi_cntrl = readl(&bdp->scb->scb_mdi_cntrl)) & MDI_PHY_READY)) && (e100_retry)) {
udelay(20);
e100_retry--;
}
spin_unlock_bh(&bdp->mdi_access_lock);
if (mdi_cntrl & MDI_PHY_READY)
return 0;
else {
printk(KERN_ERR "e100: MDI write timeout\n");
return 1;
}
}
/*
* Procedure: e100_mdi_read
*
* Description: This routine will read a value from the specified MII register
* of an external MDI compliant device (e.g. PHY 100), and return
* it to the calling routine. The command will execute in polled
* mode.
*
* Arguments:
* bdp - Ptr to this card's e100_bdconfig structure
* reg_addr - The MII register that we are reading from
* phy_addr - The MDI address of the Phy component.
*
* Results:
* data - The value that we read from the MII register.
*
* Returns:
* NOTHING
*/
int
e100_mdi_read(struct e100_private *bdp, u32 reg_addr, u32 phy_addr, u16 *data)
{
int e100_retry;
u32 temp_val;
unsigned int mdi_cntrl;
spin_lock_bh(&bdp->mdi_access_lock);
/* Issue the read command to the MDI control register. */
temp_val = ((reg_addr << 16) | (phy_addr << 21) | (MDI_READ << 26));
writel(temp_val, &bdp->scb->scb_mdi_cntrl);
readw(&bdp->scb->scb_status);
/* wait 20usec before checking status */
udelay(20);
/* poll for the mdi read to complete */
e100_retry = E100_CMD_WAIT;
while ((!((mdi_cntrl = readl(&bdp->scb->scb_mdi_cntrl)) & MDI_PHY_READY)) && (e100_retry)) {
udelay(20);
e100_retry--;
}
spin_unlock_bh(&bdp->mdi_access_lock);
if (mdi_cntrl & MDI_PHY_READY) {
/* return the lower word */
*data = (u16) mdi_cntrl;
return 0;
}
else {
printk(KERN_ERR "e100: MDI read timeout\n");
return 1;
}
}
static unsigned char
e100_phy_valid(struct e100_private *bdp, unsigned int phy_address)
{
u16 ctrl_reg, stat_reg;
/* Read the MDI control register */
e100_mdi_read(bdp, MII_BMCR, phy_address, &ctrl_reg);
/* Read the status register twice, bacause of sticky bits */
e100_mdi_read(bdp, MII_BMSR, phy_address, &stat_reg);
e100_mdi_read(bdp, MII_BMSR, phy_address, &stat_reg);
if ((ctrl_reg == 0xffff) || ((stat_reg == 0) && (ctrl_reg == 0)))
return false;
return true;
}
static void
e100_phy_address_detect(struct e100_private *bdp)
{
unsigned int addr;
unsigned char valid_phy_found = false;
if (IS_NC3133(bdp)) {
bdp->phy_addr = 0;
return;
}
if (e100_phy_valid(bdp, PHY_DEFAULT_ADDRESS)) {
bdp->phy_addr = PHY_DEFAULT_ADDRESS;
valid_phy_found = true;
} else {
for (addr = MIN_PHY_ADDR; addr <= MAX_PHY_ADDR; addr++) {
if (e100_phy_valid(bdp, addr)) {
bdp->phy_addr = addr;
valid_phy_found = true;
break;
}
}
}
if (!valid_phy_found) {
bdp->phy_addr = PHY_ADDRESS_503;
}
}
static void
e100_phy_id_detect(struct e100_private *bdp)
{
u16 low_id_reg, high_id_reg;
if (bdp->phy_addr == PHY_ADDRESS_503) {
bdp->PhyId = PHY_503;
return;
}
if (!(bdp->flags & IS_ICH)) {
if (bdp->rev_id >= D102_REV_ID) {
bdp->PhyId = PHY_82562ET;
return;
}
}
/* Read phy id from the MII register */
e100_mdi_read(bdp, MII_PHYSID1, bdp->phy_addr, &low_id_reg);
e100_mdi_read(bdp, MII_PHYSID2, bdp->phy_addr, &high_id_reg);
bdp->PhyId = ((unsigned int) low_id_reg |
((unsigned int) high_id_reg << 16));
}
static void
e100_phy_isolate(struct e100_private *bdp)
{
unsigned int phy_address;
u16 ctrl_reg;
/* Go over all phy addresses. Deisolate the selected one, and isolate
* all the rest */
for (phy_address = 0; phy_address <= MAX_PHY_ADDR; phy_address++) {
if (phy_address != bdp->phy_addr) {
e100_mdi_write(bdp, MII_BMCR, phy_address,
BMCR_ISOLATE);
} else {
e100_mdi_read(bdp, MII_BMCR, bdp->phy_addr, &ctrl_reg);
ctrl_reg &= ~BMCR_ISOLATE;
e100_mdi_write(bdp, MII_BMCR, bdp->phy_addr, ctrl_reg);
}
udelay(100);
}
}
static unsigned char
e100_phy_specific_setup(struct e100_private *bdp)
{
u16 misc_reg;
if (bdp->phy_addr == PHY_ADDRESS_503) {
switch (bdp->params.e100_speed_duplex) {
case E100_AUTONEG:
/* The adapter can't autoneg. so set to 10/HALF */
printk(KERN_INFO
"e100: 503 serial component detected which "
"cannot autonegotiate\n");
printk(KERN_INFO
"e100: speed/duplex forced to "
"10Mbps / Half duplex\n");
bdp->params.e100_speed_duplex = E100_SPEED_10_HALF;
break;
case E100_SPEED_100_HALF:
case E100_SPEED_100_FULL:
printk(KERN_ERR
"e100: 503 serial component detected "
"which does not support 100Mbps\n");
printk(KERN_ERR
"e100: Change the forced speed/duplex "
"to a supported setting\n");
return false;
}
return true;
}
if (IS_NC3133(bdp)) {
u16 int_reg;
/* enable 100BASE fiber interface */
e100_mdi_write(bdp, MDI_NC3133_CONFIG_REG, bdp->phy_addr,
MDI_NC3133_100FX_ENABLE);
if ((bdp->params.e100_speed_duplex != E100_AUTONEG) &&
(bdp->params.e100_speed_duplex != E100_SPEED_100_FULL)) {
/* just inform user about 100 full */
printk(KERN_ERR "e100: NC3133 NIC can only run "
"at 100Mbps full duplex\n");
}
bdp->params.e100_speed_duplex = E100_SPEED_100_FULL;
/* enable interrupts */
e100_mdi_read(bdp, MDI_NC3133_INT_ENABLE_REG,
bdp->phy_addr, &int_reg);
int_reg |= MDI_NC3133_INT_ENABLE;
e100_mdi_write(bdp, MDI_NC3133_INT_ENABLE_REG,
bdp->phy_addr, int_reg);
}
/* Handle the National TX */
if ((bdp->PhyId & PHY_MODEL_REV_ID_MASK) == PHY_NSC_TX) {
e100_mdi_read(bdp, NSC_CONG_CONTROL_REG,
bdp->phy_addr, &misc_reg);
misc_reg |= NSC_TX_CONG_TXREADY;
/* disable the congestion control bit in the National Phy */
misc_reg &= ~NSC_TX_CONG_ENABLE;
e100_mdi_write(bdp, NSC_CONG_CONTROL_REG,
bdp->phy_addr, misc_reg);
}
return true;
}
/*
* Procedure: e100_phy_fix_squelch
*
* Description:
* Help find link on certain rare scenarios.
* NOTE: This routine must be called once per watchdog,
* and *after* setting the current link state.
*
* Arguments:
* bdp - Ptr to this card's e100_bdconfig structure
*
* Returns:
* NOTHING
*/
static void
e100_phy_fix_squelch(struct e100_private *bdp)
{
if ((bdp->PhyId != PHY_82555_TX) || (bdp->flags & DF_SPEED_FORCED))
return;
if (netif_carrier_ok(bdp->device)) {
switch (bdp->PhyState) {
case 0:
break;
case 1:
e100_mdi_write(bdp, PHY_82555_SPECIAL_CONTROL,
bdp->phy_addr, 0x0000);
break;
case 2:
e100_mdi_write(bdp, PHY_82555_MDI_EQUALIZER_CSR,
bdp->phy_addr, 0x3000);
break;
}
bdp->PhyState = 0;
bdp->PhyDelay = 0;
} else if (!bdp->PhyDelay--) {
switch (bdp->PhyState) {
case 0:
e100_mdi_write(bdp, PHY_82555_SPECIAL_CONTROL,
bdp->phy_addr, EXTENDED_SQUELCH_BIT);
bdp->PhyState = 1;
break;
case 1:
e100_mdi_write(bdp, PHY_82555_SPECIAL_CONTROL,
bdp->phy_addr, 0x0000);
e100_mdi_write(bdp, PHY_82555_MDI_EQUALIZER_CSR,
bdp->phy_addr, 0x2010);
bdp->PhyState = 2;
break;
case 2:
e100_mdi_write(bdp, PHY_82555_MDI_EQUALIZER_CSR,
bdp->phy_addr, 0x3000);
bdp->PhyState = 0;
break;
}
e100_mdi_write(bdp, MII_BMCR, bdp->phy_addr,
BMCR_ANENABLE | BMCR_ANRESTART);
bdp->PhyDelay = 3;
}
}
/*
* Procedure: e100_fix_polarity
*
* Description:
* Fix for 82555 auto-polarity toggle problem. With a short cable
* connecting an 82555 with an 840A link partner, if the medium is noisy,
* the 82555 sometime thinks that the polarity might be wrong and so
* toggles polarity. This happens repeatedly and results in a high bit
* error rate.
* NOTE: This happens only at 10 Mbps
*
* Arguments:
* bdp - Ptr to this card's e100_bdconfig structure
*
* Returns:
* NOTHING
*/
static void
e100_fix_polarity(struct e100_private *bdp)
{
u16 status;
u16 errors;
u16 misc_reg;
int speed;
if ((bdp->PhyId != PHY_82555_TX) && (bdp->PhyId != PHY_82562ET) &&
(bdp->PhyId != PHY_82562EM))
return;
/* If the user wants auto-polarity disabled, do only that and nothing *
* else. * e100_autopolarity == 0 means disable --- we do just the
* disabling * e100_autopolarity == 1 means enable --- we do nothing at
* all * e100_autopolarity >= 2 means we do the workaround code. */
/* Change for 82558 enhancement */
switch (E100_AUTOPOLARITY) {
case 0:
e100_mdi_read(bdp, PHY_82555_SPECIAL_CONTROL,
bdp->phy_addr, &misc_reg);
e100_mdi_write(bdp, PHY_82555_SPECIAL_CONTROL, bdp->phy_addr,
(u16) (misc_reg | DISABLE_AUTO_POLARITY));
break;
case 1:
e100_mdi_read(bdp, PHY_82555_SPECIAL_CONTROL,
bdp->phy_addr, &misc_reg);
e100_mdi_write(bdp, PHY_82555_SPECIAL_CONTROL, bdp->phy_addr,
(u16) (misc_reg & ~DISABLE_AUTO_POLARITY));
break;
case 2:
/* we do this only if link is up */
if (!netif_carrier_ok(bdp->device)) {
break;
}
e100_mdi_read(bdp, PHY_82555_CSR, bdp->phy_addr, &status);
speed = (status & PHY_82555_SPEED_BIT) ? 100 : 10;
/* we need to do this only if speed is 10 */
if (speed != 10) {
break;
}
/* see if we have any end of frame errors */
e100_mdi_read(bdp, PHY_82555_EOF_COUNTER,
bdp->phy_addr, &errors);
/* if non-zero, wait for 100 ms before reading again */
if (errors) {
udelay(200);
e100_mdi_read(bdp, PHY_82555_EOF_COUNTER,
bdp->phy_addr, &errors);
/* if non-zero again, we disable polarity */
if (errors) {
e100_mdi_read(bdp, PHY_82555_SPECIAL_CONTROL,
bdp->phy_addr, &misc_reg);
e100_mdi_write(bdp, PHY_82555_SPECIAL_CONTROL,
bdp->phy_addr,
(u16) (misc_reg |
DISABLE_AUTO_POLARITY));
}
}
if (!errors) {
/* it is safe to read the polarity now */
e100_mdi_read(bdp, PHY_82555_CSR,
bdp->phy_addr, &status);
/* if polarity is normal, disable polarity */
if (!(status & PHY_82555_POLARITY_BIT)) {
e100_mdi_read(bdp, PHY_82555_SPECIAL_CONTROL,
bdp->phy_addr, &misc_reg);
e100_mdi_write(bdp, PHY_82555_SPECIAL_CONTROL,
bdp->phy_addr,
(u16) (misc_reg |
DISABLE_AUTO_POLARITY));
}
}
break;
default:
break;
}
}
/*
* Procedure: e100_find_speed_duplex
*
* Description: This routine will figure out what line speed and duplex mode
* the PHY is currently using.
*
* Arguments:
* bdp - Ptr to this card's e100_bdconfig structure
*
* Returns:
* NOTHING
*/
static void
e100_find_speed_duplex(struct e100_private *bdp)
{
unsigned int PhyId;
u16 stat_reg, misc_reg;
u16 ad_reg, lp_ad_reg;
PhyId = bdp->PhyId & PHY_MODEL_REV_ID_MASK;
/* First we should check to see if we have link */
/* If we don't have a link no reason to print a speed and duplex */
if (!e100_update_link_state(bdp)) {
bdp->cur_line_speed = 0;
bdp->cur_dplx_mode = 0;
return;
}
/* On the 82559 and later controllers, speed/duplex is part of the *
* SCB. So, we save an mdi_read and get these from the SCB. * */
if (bdp->rev_id >= D101MA_REV_ID) {
/* Read speed */
if (readb(&bdp->scb->scb_ext.d101m_scb.scb_gen_stat) & BIT_1)
bdp->cur_line_speed = 100;
else
bdp->cur_line_speed = 10;
/* Read duplex */
if (readb(&bdp->scb->scb_ext.d101m_scb.scb_gen_stat) & BIT_2)
bdp->cur_dplx_mode = FULL_DUPLEX;
else
bdp->cur_dplx_mode = HALF_DUPLEX;
return;
}
/* If this is a Phy 100, then read bits 1 and 0 of extended register 0,
* to get the current speed and duplex settings. */
if ((PhyId == PHY_100_A) || (PhyId == PHY_100_C) ||
(PhyId == PHY_82555_TX)) {
/* Read Phy 100 extended register 0 */
e100_mdi_read(bdp, EXTENDED_REG_0, bdp->phy_addr, &misc_reg);
/* Get current speed setting */
if (misc_reg & PHY_100_ER0_SPEED_INDIC)
bdp->cur_line_speed = 100;
else
bdp->cur_line_speed = 10;
/* Get current duplex setting -- FDX enabled if bit is set */
if (misc_reg & PHY_100_ER0_FDX_INDIC)
bdp->cur_dplx_mode = FULL_DUPLEX;
else
bdp->cur_dplx_mode = HALF_DUPLEX;
return;
}
/* See if link partner is capable of Auto-Negotiation (bit 0, reg 6) */
e100_mdi_read(bdp, MII_EXPANSION, bdp->phy_addr, &misc_reg);
/* See if Auto-Negotiation was complete (bit 5, reg 1) */
e100_mdi_read(bdp, MII_BMSR, bdp->phy_addr, &stat_reg);
/* If a True NWAY connection was made, then we can detect speed/dplx
* by ANDing our adapter's advertised abilities with our link partner's
* advertised ablilities, and then assuming that the highest common
* denominator was chosed by NWAY. */
if ((misc_reg & EXPANSION_NWAY) && (stat_reg & BMSR_ANEGCOMPLETE)) {
/* Read our advertisement register */
e100_mdi_read(bdp, MII_ADVERTISE, bdp->phy_addr, &ad_reg);
/* Read our link partner's advertisement register */
e100_mdi_read(bdp, MII_LPA, bdp->phy_addr, &lp_ad_reg);
/* AND the two advertisement registers together, and get rid
* of any extraneous bits. */
ad_reg &= (lp_ad_reg & NWAY_LP_ABILITY);
/* Get speed setting */
if (ad_reg &
(ADVERTISE_100HALF | ADVERTISE_100FULL |
ADVERTISE_100BASE4))
bdp->cur_line_speed = 100;
else
bdp->cur_line_speed = 10;
/* Get duplex setting -- use priority resolution algorithm */
if (ad_reg & ADVERTISE_100BASE4) {
bdp->cur_dplx_mode = HALF_DUPLEX;
} else if (ad_reg & ADVERTISE_100FULL) {
bdp->cur_dplx_mode = FULL_DUPLEX;
} else if (ad_reg & ADVERTISE_100HALF) {
bdp->cur_dplx_mode = HALF_DUPLEX;
} else if (ad_reg & ADVERTISE_10FULL) {
bdp->cur_dplx_mode = FULL_DUPLEX;
} else {
bdp->cur_dplx_mode = HALF_DUPLEX;
}
return;
}
/* If we are connected to a dumb (non-NWAY) repeater or hub, and the
* line speed was determined automatically by parallel detection, then
* we have no way of knowing exactly what speed the PHY is set to
* unless that PHY has a propietary register which indicates speed in
* this situation. The NSC TX PHY does have such a register. Also,
* since NWAY didn't establish the connection, the duplex setting
* should HALF duplex. */
bdp->cur_dplx_mode = HALF_DUPLEX;
if (PhyId == PHY_NSC_TX) {
/* Read register 25 to get the SPEED_10 bit */
e100_mdi_read(bdp, NSC_SPEED_IND_REG, bdp->phy_addr, &misc_reg);
/* If bit 6 was set then we're at 10Mbps */
if (misc_reg & NSC_TX_SPD_INDC_SPEED)
bdp->cur_line_speed = 10;
else
bdp->cur_line_speed = 100;
} else {
/* If we don't know the line speed, default to 10Mbps */
bdp->cur_line_speed = 10;
}
}
/*
* Procedure: e100_force_speed_duplex
*
* Description: This routine forces line speed and duplex mode of the
* adapter based on the values the user has set in e100.c.
*
* Arguments: bdp - Pointer to the e100_private structure for the board
*
* Returns: void
*
*/
void
e100_force_speed_duplex(struct e100_private *bdp)
{
u16 control;
unsigned long expires;
bdp->flags |= DF_SPEED_FORCED;
e100_mdi_read(bdp, MII_BMCR, bdp->phy_addr, &control);
control &= ~BMCR_ANENABLE;
control &= ~BMCR_LOOPBACK;
switch (bdp->params.e100_speed_duplex) {
case E100_SPEED_10_HALF:
control &= ~BMCR_SPEED100;
control &= ~BMCR_FULLDPLX;
bdp->cur_line_speed = 10;
bdp->cur_dplx_mode = HALF_DUPLEX;
break;
case E100_SPEED_10_FULL:
control &= ~BMCR_SPEED100;
control |= BMCR_FULLDPLX;
bdp->cur_line_speed = 10;
bdp->cur_dplx_mode = FULL_DUPLEX;
break;
case E100_SPEED_100_HALF:
control |= BMCR_SPEED100;
control &= ~BMCR_FULLDPLX;
bdp->cur_line_speed = 100;
bdp->cur_dplx_mode = HALF_DUPLEX;
break;
case E100_SPEED_100_FULL:
control |= BMCR_SPEED100;
control |= BMCR_FULLDPLX;
bdp->cur_line_speed = 100;
bdp->cur_dplx_mode = FULL_DUPLEX;
break;
}
e100_mdi_write(bdp, MII_BMCR, bdp->phy_addr, control);
/* loop must run at least once */
expires = jiffies + 2 * HZ;
do {
if (e100_update_link_state(bdp) ||
time_after(jiffies, expires)) {
break;
} else {
yield();
}
} while (true);
}
void
e100_force_speed_duplex_to_phy(struct e100_private *bdp)
{
u16 control;
e100_mdi_read(bdp, MII_BMCR, bdp->phy_addr, &control);
control &= ~BMCR_ANENABLE;
control &= ~BMCR_LOOPBACK;
switch (bdp->params.e100_speed_duplex) {
case E100_SPEED_10_HALF:
control &= ~BMCR_SPEED100;
control &= ~BMCR_FULLDPLX;
break;
case E100_SPEED_10_FULL:
control &= ~BMCR_SPEED100;
control |= BMCR_FULLDPLX;
break;
case E100_SPEED_100_HALF:
control |= BMCR_SPEED100;
control &= ~BMCR_FULLDPLX;
break;
case E100_SPEED_100_FULL:
control |= BMCR_SPEED100;
control |= BMCR_FULLDPLX;
break;
}
/* Send speed/duplex command to PHY layer. */
e100_mdi_write(bdp, MII_BMCR, bdp->phy_addr, control);
}
/*
* Procedure: e100_set_fc
*
* Description: Checks the link's capability for flow control.
*
* Arguments: bdp - Pointer to the e100_private structure for the board
*
* Returns: void
*
*/
static void
e100_set_fc(struct e100_private *bdp)
{
u16 ad_reg;
u16 lp_ad_reg;
u16 exp_reg;
/* no flow control for 82557, forced links or half duplex */
if (!netif_carrier_ok(bdp->device) || (bdp->flags & DF_SPEED_FORCED) ||
(bdp->cur_dplx_mode == HALF_DUPLEX) ||
!(bdp->flags & IS_BACHELOR)) {
bdp->flags &= ~DF_LINK_FC_CAP;
return;
}
/* See if link partner is capable of Auto-Negotiation (bit 0, reg 6) */
e100_mdi_read(bdp, MII_EXPANSION, bdp->phy_addr, &exp_reg);
if (exp_reg & EXPANSION_NWAY) {
/* Read our advertisement register */
e100_mdi_read(bdp, MII_ADVERTISE, bdp->phy_addr, &ad_reg);
/* Read our link partner's advertisement register */
e100_mdi_read(bdp, MII_LPA, bdp->phy_addr, &lp_ad_reg);
ad_reg &= lp_ad_reg; /* AND the 2 ad registers */
if (ad_reg & NWAY_AD_FC_SUPPORTED)
bdp->flags |= DF_LINK_FC_CAP;
else
/* If link partner is capable of autoneg, but */
/* not capable of flow control, Received PAUSE */
/* frames are still honored, i.e., */
/* transmitted frames would be paused */
/* by incoming PAUSE frames */
bdp->flags |= DF_LINK_FC_TX_ONLY;
} else {
bdp->flags &= ~DF_LINK_FC_CAP;
}
}
/*
* Procedure: e100_phy_check
*
* Arguments: bdp - Pointer to the e100_private structure for the board
*
* Returns: true if link state was changed
* false otherwise
*
*/
unsigned char
e100_phy_check(struct e100_private *bdp)
{
unsigned char old_link;
unsigned char changed = false;
old_link = netif_carrier_ok(bdp->device) ? 1 : 0;
e100_find_speed_duplex(bdp);
if (!old_link && netif_carrier_ok(bdp->device)) {
e100_set_fc(bdp);
changed = true;
}
if (old_link && !netif_carrier_ok(bdp->device)) {
/* reset the zero lock state */
bdp->zlock_state = ZLOCK_INITIAL;
// set auto lock for phy auto-negotiation on link up
if ((bdp->PhyId & PHY_MODEL_REV_ID_MASK) == PHY_82555_TX)
e100_mdi_write(bdp, PHY_82555_MDI_EQUALIZER_CSR,
bdp->phy_addr, 0);
changed = true;
}
e100_phy_fix_squelch(bdp);
e100_handle_zlock(bdp);
return changed;
}
/*
* Procedure: e100_auto_neg
*
* Description: This routine will start autonegotiation and wait
* for it to complete
*
* Arguments:
* bdp - pointer to this card's e100_bdconfig structure
* force_restart - defines if autoneg should be restarted even if it
* has been completed before
* Returns:
* NOTHING
*/
static void
e100_auto_neg(struct e100_private *bdp, unsigned char force_restart)
{
u16 stat_reg;
unsigned long expires;
bdp->flags &= ~DF_SPEED_FORCED;
e100_mdi_read(bdp, MII_BMSR, bdp->phy_addr, &stat_reg);
e100_mdi_read(bdp, MII_BMSR, bdp->phy_addr, &stat_reg);
/* if we are capable of performing autoneg then we restart if needed */
if ((stat_reg != 0xFFFF) && (stat_reg & BMSR_ANEGCAPABLE)) {
if ((!force_restart) &&
(stat_reg & BMSR_ANEGCOMPLETE)) {
goto exit;
}
e100_mdi_write(bdp, MII_BMCR, bdp->phy_addr,
BMCR_ANENABLE | BMCR_ANRESTART);
/* wait for autoneg to complete (up to 3 seconds) */
expires = jiffies + HZ * 3;
do {
/* now re-read the value. Sticky so read twice */
e100_mdi_read(bdp, MII_BMSR, bdp->phy_addr, &stat_reg);
e100_mdi_read(bdp, MII_BMSR, bdp->phy_addr, &stat_reg);
if ((stat_reg & BMSR_ANEGCOMPLETE) ||
time_after(jiffies, expires) ) {
goto exit;
} else {
yield();
}
} while (true);
}
exit:
e100_find_speed_duplex(bdp);
}
void
e100_phy_set_speed_duplex(struct e100_private *bdp, unsigned char force_restart)
{
if (bdp->params.e100_speed_duplex == E100_AUTONEG) {
if (bdp->rev_id >= D102_REV_ID)
/* Enable MDI/MDI-X auto switching */
e100_mdi_write(bdp, MII_NCONFIG, bdp->phy_addr,
MDI_MDIX_AUTO_SWITCH_ENABLE);
e100_auto_neg(bdp, force_restart);
} else {
if (bdp->rev_id >= D102_REV_ID)
/* Disable MDI/MDI-X auto switching */
e100_mdi_write(bdp, MII_NCONFIG, bdp->phy_addr,
MDI_MDIX_RESET_ALL_MASK);
e100_force_speed_duplex(bdp);
}
e100_set_fc(bdp);
}
void
e100_phy_autoneg(struct e100_private *bdp)
{
u16 ctrl_reg;
ctrl_reg = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET;
e100_mdi_write(bdp, MII_BMCR, bdp->phy_addr, ctrl_reg);
udelay(100);
}
void
e100_phy_set_loopback(struct e100_private *bdp)
{
u16 ctrl_reg;
ctrl_reg = BMCR_LOOPBACK;
e100_mdi_write(bdp, MII_BMCR, bdp->phy_addr, ctrl_reg);
udelay(100);
}
void
e100_phy_reset(struct e100_private *bdp)
{
u16 ctrl_reg;
ctrl_reg = BMCR_RESET;
e100_mdi_write(bdp, MII_BMCR, bdp->phy_addr, ctrl_reg);
/* ieee 802.3 : The reset process shall be completed */
/* within 0.5 seconds from the settting of PHY reset bit. */
set_current_state(TASK_UNINTERRUPTIBLE);
schedule_timeout(HZ / 2);
}
unsigned char
e100_phy_init(struct e100_private *bdp)
{
e100_phy_reset(bdp);
e100_phy_address_detect(bdp);
e100_phy_isolate(bdp);
e100_phy_id_detect(bdp);
if (!e100_phy_specific_setup(bdp))
return false;
bdp->PhyState = 0;
bdp->PhyDelay = 0;
bdp->zlock_state = ZLOCK_INITIAL;
e100_phy_set_speed_duplex(bdp, false);
e100_fix_polarity(bdp);
return true;
}
/*
* Procedure: e100_get_link_state
*
* Description: This routine checks the link status of the adapter
*
* Arguments: bdp - Pointer to the e100_private structure for the board
*
*
* Returns: true - If a link is found
* false - If there is no link
*
*/
unsigned char
e100_get_link_state(struct e100_private *bdp)
{
unsigned char link = false;
u16 status;
/* Check link status */
/* If the controller is a 82559 or later one, link status is available
* from the CSR. This avoids the mdi_read. */
if (bdp->rev_id >= D101MA_REV_ID) {
if (readb(&bdp->scb->scb_ext.d101m_scb.scb_gen_stat) & BIT_0) {
link = true;
} else {
link = false;
}
} else {
/* Read the status register twice because of sticky bits */
e100_mdi_read(bdp, MII_BMSR, bdp->phy_addr, &status);
e100_mdi_read(bdp, MII_BMSR, bdp->phy_addr, &status);
if (status & BMSR_LSTATUS) {
link = true;
} else {
link = false;
}
}
return link;
}
/*
* Procedure: e100_update_link_state
*
* Description: This routine updates the link status of the adapter,
* also considering netif_running
*
* Arguments: bdp - Pointer to the e100_private structure for the board
*
*
* Returns: true - If a link is found
* false - If there is no link
*
*/
unsigned char
e100_update_link_state(struct e100_private *bdp)
{
unsigned char link;
/* Logical AND PHY link & netif_running */
link = e100_get_link_state(bdp) && netif_running(bdp->device);
if (link) {
if (!netif_carrier_ok(bdp->device))
netif_carrier_on(bdp->device);
} else {
if (netif_carrier_ok(bdp->device))
netif_carrier_off(bdp->device);
}
return link;
}
/**************************************************************************\
**
** PROC NAME: e100_handle_zlock
** This function manages a state machine that controls
** the driver's zero locking algorithm.
** This function is called by e100_watchdog() every ~2 second.
** States:
** The current link handling state is stored in
** bdp->zlock_state, and is one of:
** ZLOCK_INITIAL, ZLOCK_READING, ZLOCK_SLEEPING
** Detailed description of the states and the transitions
** between states is found below.
** Note that any time the link is down / there is a reset
** state will be changed outside this function to ZLOCK_INITIAL
** Algorithm:
** 1. If link is up & 100 Mbps continue else stay in #1:
** 2. Set 'auto lock'
** 3. Read & Store 100 times 'Zero' locked in 1 sec interval
** 4. If max zero read >= 0xB continue else goto 1
** 5. Set most popular 'Zero' read in #3
** 6. Sleep 5 minutes
** 7. Read number of errors, if it is > 300 goto 2 else goto 6
** Data Structures (in DRIVER_DATA):
** zlock_state - current state of the algorithm
** zlock_read_cnt - counts number of reads (up to 100)
** zlock_read_data[i] - counts number of times 'Zero' read was i, 0 <= i <= 15
** zlock_sleep_cnt - keeps track of "sleep" time (up to 300 secs = 5 minutes)
**
** Parameters: DRIVER_DATA *bdp
**
** bdp - Pointer to HSM's adapter data space
**
** Return Value: NONE
**
** See Also: e100_watchdog()
**
\**************************************************************************/
void
e100_handle_zlock(struct e100_private *bdp)
{
u16 pos;
u16 eq_reg;
u16 err_cnt;
u8 mpz; /* Most Popular Zero */
switch (bdp->zlock_state) {
case ZLOCK_INITIAL:
if (((u8) bdp->rev_id <= D102_REV_ID) ||
!(bdp->cur_line_speed == 100) ||
!netif_carrier_ok(bdp->device)) {
break;
}
/* initialize hw and sw and start reading */
e100_mdi_write(bdp, PHY_82555_MDI_EQUALIZER_CSR,
bdp->phy_addr, 0);
/* reset read counters: */
bdp->zlock_read_cnt = 0;
for (pos = 0; pos < 16; pos++)
bdp->zlock_read_data[pos] = 0;
/* start reading in the next call back: */
bdp->zlock_state = ZLOCK_READING;
/* FALL THROUGH !! */
case ZLOCK_READING:
/* state: reading (100 times) zero locked in 1 sec interval
* prev states: ZLOCK_INITIAL
* next states: ZLOCK_INITIAL, ZLOCK_SLEEPING */
e100_mdi_read(bdp, PHY_82555_MDI_EQUALIZER_CSR,
bdp->phy_addr, &eq_reg);
pos = (eq_reg & ZLOCK_ZERO_MASK) >> 4;
bdp->zlock_read_data[pos]++;
bdp->zlock_read_cnt++;
if (bdp->zlock_read_cnt == ZLOCK_MAX_READS) {
/* check if we read a 'Zero' value of 0xB or greater */
if ((bdp->zlock_read_data[0xB]) ||
(bdp->zlock_read_data[0xC]) ||
(bdp->zlock_read_data[0xD]) ||
(bdp->zlock_read_data[0xE]) ||
(bdp->zlock_read_data[0xF])) {
/* we've read 'Zero' value of 0xB or greater,
* find most popular 'Zero' value and lock it */
mpz = 0;
/* this loop finds the most popular 'Zero': */
for (pos = 1; pos < 16; pos++) {
if (bdp->zlock_read_data[pos] >
bdp->zlock_read_data[mpz])
mpz = pos;
}
/* now lock the most popular 'Zero': */
eq_reg = (ZLOCK_SET_ZERO | mpz);
e100_mdi_write(bdp,
PHY_82555_MDI_EQUALIZER_CSR,
bdp->phy_addr, eq_reg);
/* sleep for 5 minutes: */
bdp->zlock_sleep_cnt = jiffies;
bdp->zlock_state = ZLOCK_SLEEPING;
/* we will be reading the # of errors after 5
* minutes, so we need to reset the error
* counters - these registers are self clearing
* on read, so read them */
e100_mdi_read(bdp, PHY_82555_SYMBOL_ERR,
bdp->phy_addr, &err_cnt);
} else {
/* we did not read a 'Zero' value of 0xB or
* above. go back to the start */
bdp->zlock_state = ZLOCK_INITIAL;
}
}
break;
case ZLOCK_SLEEPING:
/* state: sleeping for 5 minutes
* prev states: ZLOCK_READING
* next states: ZLOCK_READING, ZLOCK_SLEEPING */
/* if 5 minutes have passed: */
if ((jiffies - bdp->zlock_sleep_cnt) >= ZLOCK_MAX_SLEEP) {
/* read and sum up the number of errors: */
e100_mdi_read(bdp, PHY_82555_SYMBOL_ERR,
bdp->phy_addr, &err_cnt);
/* if we've more than 300 errors (this number was
* calculated according to the spec max allowed errors
* (80 errors per 1 million frames) for 5 minutes in
* 100 Mbps (or the user specified max BER number) */
if (err_cnt > bdp->params.ber) {
/* start again in the next callback: */
bdp->zlock_state = ZLOCK_INITIAL;
} else {
/* we don't have more errors than allowed,
* sleep for 5 minutes */
bdp->zlock_sleep_cnt = jiffies;
}
}
break;
default:
break;
}
}
drivers/net/e100/e100_phy.h deleted 100644 → 0
View file @ 02a38ad0
/*******************************************************************************
Copyright(c) 1999 - 2003 Intel Corporation. All rights reserved.
This program is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the Free
Software Foundation; either version 2 of the License, or (at your option)
any later version.
This program is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
this program; if not, write to the Free Software Foundation, Inc., 59
Temple Place - Suite 330, Boston, MA 02111-1307, USA.
The full GNU General Public License is included in this distribution in the
file called LICENSE.
Contact Information:
Linux NICS <linux.nics@intel.com>
Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
*******************************************************************************/
#ifndef _E100_PHY_INC_
#define _E100_PHY_INC_
#include "e100.h"
/*
* Auto-polarity enable/disable
* e100_autopolarity = 0 => disable auto-polarity
* e100_autopolarity = 1 => enable auto-polarity
* e100_autopolarity = 2 => let software determine
*/
#define E100_AUTOPOLARITY 2
#define IS_NC3133(bdp) (((bdp)->pdev->subsystem_vendor == 0x0E11) && \
((bdp)->pdev->subsystem_device == 0xB0E1))
#define PHY_503 0
#define PHY_100_A 0x000003E0
#define PHY_100_C 0x035002A8
#define PHY_NSC_TX 0x5c002000
#define PHY_82562ET 0x033002A8
#define PHY_82562EM 0x032002A8
#define PHY_82562EH 0x017002A8
#define PHY_82555_TX 0x015002a8 /* added this for 82555 */
#define PHY_OTHER 0xFFFF
#define MAX_PHY_ADDR 31
#define MIN_PHY_ADDR 0
#define PHY_MODEL_REV_ID_MASK 0xFFF0FFFF
#define PHY_DEFAULT_ADDRESS 1
#define PHY_ADDRESS_503 32
/* MDI Control register bit definitions */
#define MDI_PHY_READY BIT_28 /* PHY is ready for next MDI cycle */
#define MDI_NC3133_CONFIG_REG 0x19
#define MDI_NC3133_100FX_ENABLE BIT_2
#define MDI_NC3133_INT_ENABLE_REG 0x17
#define MDI_NC3133_INT_ENABLE BIT_1
/* MDI Control register opcode definitions */
#define MDI_WRITE 1 /* Phy Write */
#define MDI_READ 2 /* Phy read */
/* MDI register set*/
#define AUTO_NEG_NEXT_PAGE_REG 0x07 /* Auto-negotiation next page xmit */
#define EXTENDED_REG_0 0x10 /* Extended reg 0 (Phy 100 modes) */
#define EXTENDED_REG_1 0x14 /* Extended reg 1 (Phy 100 error indications) */
#define NSC_CONG_CONTROL_REG 0x17 /* National (TX) congestion control */
#define NSC_SPEED_IND_REG 0x19 /* National (TX) speed indication */
#define HWI_CONTROL_REG 0x1D /* HWI Control register */
/* MDI/MDI-X Control Register bit definitions */
#define MDI_MDIX_RES_TIMER BIT_0_3 /* minimum slot time for resolution timer */
#define MDI_MDIX_CONFIG_IS_OK BIT_4 /* 1 = resolution algorithm completes OK */
#define MDI_MDIX_STATUS BIT_5 /* 1 = MDIX (croos over), 0 = MDI (straight through) */
#define MDI_MDIX_SWITCH BIT_6 /* 1 = Forces to MDIX, 0 = Forces to MDI */
#define MDI_MDIX_AUTO_SWITCH_ENABLE BIT_7 /* 1 = MDI/MDI-X feature enabled */
#define MDI_MDIX_CONCT_CONFIG BIT_8 /* Sets the MDI/MDI-X connectivity configuration (test prupose only) */
#define MDI_MDIX_CONCT_TEST_ENABLE BIT_9 /* 1 = Enables connectivity testing */
#define MDI_MDIX_RESET_ALL_MASK 0x0000
/* HWI Control Register bit definitions */
#define HWI_TEST_DISTANCE BIT_0_8 /* distance to cable problem */
#define HWI_TEST_HIGHZ_PROBLEM BIT_9 /* 1 = Open Circuit */
#define HWI_TEST_LOWZ_PROBLEM BIT_10 /* 1 = Short Circuit */
#define HWI_TEST_RESERVED (BIT_11 | BIT_12) /* reserved */
#define HWI_TEST_EXECUTE BIT_13 /* 1 = Execute the HWI test on the PHY */
#define HWI_TEST_ABILITY BIT_14 /* 1 = test passed */
#define HWI_TEST_ENABLE BIT_15 /* 1 = Enables the HWI feature */
#define HWI_RESET_ALL_MASK 0x0000
/* ############Start of 82555 specific defines################## */
/* Intel 82555 specific registers */
#define PHY_82555_CSR 0x10 /* 82555 CSR */
#define PHY_82555_SPECIAL_CONTROL 0x11 /* 82555 special control register */
#define PHY_82555_RCV_ERR 0x15 /* 82555 100BaseTx Receive Error
* Frame Counter */
#define PHY_82555_SYMBOL_ERR 0x16 /* 82555 RCV Symbol Error Counter */
#define PHY_82555_PREM_EOF_ERR 0x17 /* 82555 100BaseTx RCV Premature End
* of Frame Error Counter */
#define PHY_82555_EOF_COUNTER 0x18 /* 82555 end of frame error counter */
#define PHY_82555_MDI_EQUALIZER_CSR 0x1a /* 82555 specific equalizer reg. */
/* 82555 CSR bits */
#define PHY_82555_SPEED_BIT BIT_1
#define PHY_82555_POLARITY_BIT BIT_8
/* 82555 equalizer reg. opcodes */
#define ENABLE_ZERO_FORCING 0x2010 /* write to ASD conf. reg. 0 */
#define DISABLE_ZERO_FORCING 0x2000 /* write to ASD conf. reg. 0 */
/* 82555 special control reg. opcodes */
#define DISABLE_AUTO_POLARITY 0x0010
#define EXTENDED_SQUELCH_BIT BIT_2
/* ############End of 82555 specific defines##################### */
/* Auto-Negotiation advertisement register bit definitions*/
#define NWAY_AD_FC_SUPPORTED 0x0400 /* Flow Control supported */
/* Auto-Negotiation link partner ability register bit definitions*/
#define NWAY_LP_ABILITY 0x07e0 /* technologies supported */
/* PHY 100 Extended Register 0 bit definitions*/
#define PHY_100_ER0_FDX_INDIC BIT_0 /* 1 = FDX, 0 = half duplex */
#define PHY_100_ER0_SPEED_INDIC BIT_1 /* 1 = 100Mbps, 0= 10Mbps */
/* National Semiconductor TX phy congestion control register bit definitions*/
#define NSC_TX_CONG_TXREADY BIT_10 /* Makes TxReady an input */
#define NSC_TX_CONG_ENABLE BIT_8 /* Enables congestion control */
/* National Semiconductor TX phy speed indication register bit definitions*/
#define NSC_TX_SPD_INDC_SPEED BIT_6 /* 0 = 100Mbps, 1=10Mbps */
/************* function prototypes ************/
extern unsigned char e100_phy_init(struct e100_private *bdp);
extern unsigned char e100_update_link_state(struct e100_private *bdp);
extern unsigned char e100_phy_check(struct e100_private *bdp);
extern void e100_phy_set_speed_duplex(struct e100_private *bdp,
unsigned char force_restart);
extern void e100_phy_autoneg(struct e100_private *bdp);
extern void e100_phy_reset(struct e100_private *bdp);
extern void e100_phy_set_loopback(struct e100_private *bdp);
extern int e100_mdi_write(struct e100_private *, u32, u32, u16);
extern int e100_mdi_read(struct e100_private *, u32, u32, u16 *);
#endif
drivers/net/e100/e100_test.c deleted 100644 → 0
View file @ 02a38ad0
/*******************************************************************************
Copyright(c) 1999 - 2003 Intel Corporation. All rights reserved.
This program is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the Free
Software Foundation; either version 2 of the License, or (at your option)
any later version.
This program is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
this program; if not, write to the Free Software Foundation, Inc., 59
Temple Place - Suite 330, Boston, MA 02111-1307, USA.
The full GNU General Public License is included in this distribution in the
file called LICENSE.
Contact Information:
Linux NICS <linux.nics@intel.com>
Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
*******************************************************************************/
#include "e100_phy.h"
#include "e100_config.h"
extern u16 e100_eeprom_read(struct e100_private *, u16);
extern int e100_wait_exec_cmplx(struct e100_private *, u32,u8, u8);
extern void e100_phy_reset(struct e100_private *bdp);
extern void e100_phy_autoneg(struct e100_private *bdp);
extern void e100_phy_set_loopback(struct e100_private *bdp);
extern void e100_force_speed_duplex(struct e100_private *bdp);
static u8 e100_diag_selftest(struct net_device *);
static u8 e100_diag_eeprom(struct net_device *);
static u8 e100_diag_loopback(struct net_device *);
static u8 e100_diag_one_loopback (struct net_device *, u8);
static u8 e100_diag_rcv_loopback_pkt(struct e100_private *);
static void e100_diag_config_loopback(struct e100_private *, u8, u8, u8 *,u8 *);
static u8 e100_diag_loopback_alloc(struct e100_private *);
static void e100_diag_loopback_cu_ru_exec(struct e100_private *);
static u8 e100_diag_check_pkt(u8 *);
static void e100_diag_loopback_free(struct e100_private *);
static int e100_cable_diag(struct e100_private *bdp);
#define LB_PACKET_SIZE 1500
/**
* e100_run_diag - main test execution handler - checks mask of requests and calls the diag routines
* @dev: atapter's net device data struct
* @test_info: array with test request mask also used to store test results
*
* RETURNS: updated flags field of struct ethtool_test
*/
u32
e100_run_diag(struct net_device *dev, u64 *test_info, u32 flags)
{
struct e100_private* bdp = dev->priv;
u8 test_result = 0;
if (!e100_get_link_state(bdp)) {
test_result = ETH_TEST_FL_FAILED;
test_info[test_link] = true;
}
if (!e100_diag_eeprom(dev)) {
test_result = ETH_TEST_FL_FAILED;
test_info[test_eeprom] = true;
}
if (flags & ETH_TEST_FL_OFFLINE) {
u8 fail_mask;
if (netif_running(dev)) {
spin_lock_bh(&dev->xmit_lock);
e100_close(dev);
spin_unlock_bh(&dev->xmit_lock);
}
if (e100_diag_selftest(dev)) {
test_result = ETH_TEST_FL_FAILED;
test_info[test_self_test] = true;
}
fail_mask = e100_diag_loopback(dev);
if (fail_mask) {
test_result = ETH_TEST_FL_FAILED;
if (fail_mask & PHY_LOOPBACK)
test_info[test_loopback_phy] = true;
if (fail_mask & MAC_LOOPBACK)
test_info[test_loopback_mac] = true;
}
test_info[cable_diag] = e100_cable_diag(bdp);
/* Need hw init regardless of netif_running */
e100_hw_init(bdp);
if (netif_running(dev)) {
e100_open(dev);
}
}
else {
test_info[test_self_test] = false;
test_info[test_loopback_phy] = false;
test_info[test_loopback_mac] = false;
test_info[cable_diag] = false;
}
return flags | test_result;
}
/**
* e100_diag_selftest - run hardware selftest
* @dev: atapter's net device data struct
*/
static u8
e100_diag_selftest(struct net_device *dev)
{
struct e100_private *bdp = dev->priv;
u32 st_timeout, st_result;
u8 retval = 0;
if (!e100_selftest(bdp, &st_timeout, &st_result)) {
if (!st_timeout) {
if (st_result & CB_SELFTEST_REGISTER_BIT)
retval |= REGISTER_TEST_FAIL;
if (st_result & CB_SELFTEST_DIAG_BIT)
retval |= SELF_TEST_FAIL;
if (st_result & CB_SELFTEST_ROM_BIT)
retval |= ROM_TEST_FAIL;
} else {
retval = TEST_TIMEOUT;
}
}
return retval;
}
/**
* e100_diag_eeprom - validate eeprom checksum correctness
* @dev: atapter's net device data struct
*
*/
static u8
e100_diag_eeprom (struct net_device *dev)
{
struct e100_private *bdp = dev->priv;
u16 i, eeprom_sum, eeprom_actual_csm;
for (i = 0, eeprom_sum = 0; i < (bdp->eeprom_size - 1); i++) {
eeprom_sum += e100_eeprom_read(bdp, i);
}
eeprom_actual_csm = e100_eeprom_read(bdp, bdp->eeprom_size - 1);
if (eeprom_actual_csm == (u16)(EEPROM_SUM - eeprom_sum)) {
return true;
}
return false;
}
/**
* e100_diag_loopback - performs loopback test
* @dev: atapter's net device data struct
*/
static u8
e100_diag_loopback (struct net_device *dev)
{
u8 rc = 0;
printk(KERN_DEBUG "%s: PHY loopback test starts\n", dev->name);
e100_hw_init(dev->priv);
if (!e100_diag_one_loopback(dev, PHY_LOOPBACK)) {
rc |= PHY_LOOPBACK;
}
printk(KERN_DEBUG "%s: PHY loopback test ends\n", dev->name);
printk(KERN_DEBUG "%s: MAC loopback test starts\n", dev->name);
e100_hw_init(dev->priv);
if (!e100_diag_one_loopback(dev, MAC_LOOPBACK)) {
rc |= MAC_LOOPBACK;
}
printk(KERN_DEBUG "%s: MAC loopback test ends\n", dev->name);
return rc;
}
/**
* e100_diag_loopback - performs loopback test
* @dev: atapter's net device data struct
* @mode: lopback test type
*/
static u8
e100_diag_one_loopback (struct net_device *dev, u8 mode)
{
struct e100_private *bdp = dev->priv;
u8 res = false;
u8 saved_dynamic_tbd = false;
u8 saved_extended_tcb = false;
if (!e100_diag_loopback_alloc(bdp))
return false;
/* change the config block to standard tcb and the correct loopback */
e100_diag_config_loopback(bdp, true, mode,
&saved_extended_tcb, &saved_dynamic_tbd);
e100_diag_loopback_cu_ru_exec(bdp);
if (e100_diag_rcv_loopback_pkt(bdp)) {
res = true;
}
e100_diag_loopback_free(bdp);
/* change the config block to previous tcb mode and the no loopback */
e100_diag_config_loopback(bdp, false, mode,
&saved_extended_tcb, &saved_dynamic_tbd);
return res;
}
/**
* e100_diag_config_loopback - setup/clear loopback before/after lpbk test
* @bdp: atapter's private data struct
* @set_loopback: true if the function is called to set lb
* @loopback_mode: the loopback mode(MAC or PHY)
* @tcb_extended: true if need to set extended tcb mode after clean loopback
* @dynamic_tbd: true if needed to set dynamic tbd mode after clean loopback
*
*/
void
e100_diag_config_loopback(struct e100_private* bdp,
u8 set_loopback,
u8 loopback_mode,
u8* tcb_extended,
u8* dynamic_tbd)
{
/* if set_loopback == true - we want to clear tcb_extended/dynamic_tbd.
* the previous values are saved in the params tcb_extended/dynamic_tbd
* if set_loopback == false - we want to restore previous value.
*/
if (set_loopback || (*tcb_extended))
*tcb_extended = e100_config_tcb_ext_enable(bdp,*tcb_extended);
if (set_loopback || (*dynamic_tbd))
*dynamic_tbd = e100_config_dynamic_tbd(bdp,*dynamic_tbd);
if (set_loopback) {
/* ICH PHY loopback is broken */
if (bdp->flags & IS_ICH && loopback_mode == PHY_LOOPBACK)
loopback_mode = MAC_LOOPBACK;
/* Configure loopback on MAC */
e100_config_loopback_mode(bdp,loopback_mode);
} else {
e100_config_loopback_mode(bdp,NO_LOOPBACK);
}
e100_config(bdp);
if (loopback_mode == PHY_LOOPBACK) {
if (set_loopback)
/* Set PHY loopback mode */
e100_phy_set_loopback(bdp);
else
/* Reset PHY loopback mode */
e100_phy_reset(bdp);
/* Wait for PHY state change */
set_current_state(TASK_UNINTERRUPTIBLE);
schedule_timeout(HZ);
} else { /* For MAC loopback wait 500 msec to take effect */
set_current_state(TASK_UNINTERRUPTIBLE);
schedule_timeout(HZ / 2);
}
}
/**
* e100_diag_loopback_alloc - alloc & initate tcb and rfd for the loopback
* @bdp: atapter's private data struct
*
*/
static u8
e100_diag_loopback_alloc(struct e100_private *bdp)
{
dma_addr_t dma_handle;
tcb_t *tcb;
rfd_t *rfd;
tbd_t *tbd;
/* tcb, tbd and transmit buffer are allocated */
tcb = pci_alloc_consistent(bdp->pdev,
(sizeof (tcb_t) + sizeof (tbd_t) +
LB_PACKET_SIZE),
&dma_handle);
if (tcb == NULL)
return false;
memset(tcb, 0x00, sizeof (tcb_t) + sizeof (tbd_t) + LB_PACKET_SIZE);
tcb->tcb_phys = dma_handle;
tcb->tcb_hdr.cb_status = 0;
tcb->tcb_hdr.cb_cmd =
cpu_to_le16(CB_EL_BIT | CB_TRANSMIT | CB_TX_SF_BIT);
/* Next command is null */
tcb->tcb_hdr.cb_lnk_ptr = cpu_to_le32(0xffffffff);
tcb->tcb_cnt = 0;
tcb->tcb_thrshld = bdp->tx_thld;
tcb->tcb_tbd_num = 1;
/* Set up tcb tbd pointer */
tcb->tcb_tbd_ptr = cpu_to_le32(tcb->tcb_phys + sizeof (tcb_t));
tbd = (tbd_t *) ((u8 *) tcb + sizeof (tcb_t));
/* Set up tbd transmit buffer */
tbd->tbd_buf_addr =
cpu_to_le32(le32_to_cpu(tcb->tcb_tbd_ptr) + sizeof (tbd_t));
tbd->tbd_buf_cnt = __constant_cpu_to_le16(1024);
/* The value of first 512 bytes is FF */
memset((void *) ((u8 *) tbd + sizeof (tbd_t)), 0xFF, 512);
/* The value of second 512 bytes is BA */
memset((void *) ((u8 *) tbd + sizeof (tbd_t) + 512), 0xBA, 512);
wmb();
rfd = pci_alloc_consistent(bdp->pdev, sizeof (rfd_t), &dma_handle);
if (rfd == NULL) {
pci_free_consistent(bdp->pdev,
sizeof (tcb_t) + sizeof (tbd_t) +
LB_PACKET_SIZE, tcb, tcb->tcb_phys);
return false;
}
memset(rfd, 0x00, sizeof (rfd_t));
/* init all fields in rfd */
rfd->rfd_header.cb_cmd = cpu_to_le16(RFD_EL_BIT);
rfd->rfd_sz = cpu_to_le16(ETH_FRAME_LEN + CHKSUM_SIZE);
/* dma_handle is physical address of rfd */
bdp->loopback.dma_handle = dma_handle;
bdp->loopback.tcb = tcb;
bdp->loopback.rfd = rfd;
wmb();
return true;
}
/**
* e100_diag_loopback_cu_ru_exec - activates cu and ru to send & receive the pkt
* @bdp: atapter's private data struct
*
*/
static void
e100_diag_loopback_cu_ru_exec(struct e100_private *bdp)
{
/*load CU & RU base */
if(!e100_wait_exec_cmplx(bdp, bdp->loopback.dma_handle, SCB_RUC_START, 0))
printk(KERN_ERR "e100: SCB_RUC_START failed!\n");
bdp->next_cu_cmd = START_WAIT;
e100_start_cu(bdp, bdp->loopback.tcb);
bdp->last_tcb = NULL;
rmb();
}
/**
* e100_diag_check_pkt - checks if a given packet is a loopback packet
* @bdp: atapter's private data struct
*
* Returns true if OK false otherwise.
*/
static u8
e100_diag_check_pkt(u8 *datap)
{
int i;
for (i = 0; i<512; i++) {
if( !((*datap)==0xFF && (*(datap + 512) == 0xBA)) ) {
printk (KERN_ERR "e100: check loopback packet failed at: %x\n", i);
return false;
}
}
printk (KERN_DEBUG "e100: Check received loopback packet OK\n");
return true;
}
/**
* e100_diag_rcv_loopback_pkt - waits for receive and checks lpbk packet
* @bdp: atapter's private data struct
*
* Returns true if OK false otherwise.
*/
static u8
e100_diag_rcv_loopback_pkt(struct e100_private* bdp)
{
rfd_t *rfdp;
u16 rfd_status;
unsigned long expires = jiffies + HZ * 2;
rfdp =bdp->loopback.rfd;
rfd_status = le16_to_cpu(rfdp->rfd_header.cb_status);
while (!(rfd_status & RFD_STATUS_COMPLETE)) {
if (time_before(jiffies, expires)) {
yield();
rmb();
rfd_status = le16_to_cpu(rfdp->rfd_header.cb_status);
} else {
break;
}
}
if (rfd_status & RFD_STATUS_COMPLETE) {
printk(KERN_DEBUG "e100: Loopback packet received\n");
return e100_diag_check_pkt(((u8 *)rfdp+bdp->rfd_size));
}
else {
printk(KERN_ERR "e100: Loopback packet not received\n");
return false;
}
}
/**
* e100_diag_loopback_free - free data allocated for loopback pkt send/receive
* @bdp: atapter's private data struct
*
*/
static void
e100_diag_loopback_free (struct e100_private *bdp)
{
pci_free_consistent(bdp->pdev,
sizeof(tcb_t) + sizeof(tbd_t) + LB_PACKET_SIZE,
bdp->loopback.tcb, bdp->loopback.tcb->tcb_phys);
pci_free_consistent(bdp->pdev, sizeof(rfd_t), bdp->loopback.rfd,
bdp->loopback.dma_handle);
}
static int
e100_cable_diag(struct e100_private *bdp)
{
int saved_open_circut = 0xffff;
int saved_short_circut = 0xffff;
int saved_distance = 0xffff;
int saved_same = 0;
int cable_status = E100_CABLE_UNKNOWN;
int i;
/* If we have link, */
if (e100_get_link_state(bdp))
return E100_CABLE_OK;
if (bdp->rev_id < D102_REV_ID)
return E100_CABLE_UNKNOWN;
/* Disable MDI/MDI-X auto switching */
e100_mdi_write(bdp, MII_NCONFIG, bdp->phy_addr,
MDI_MDIX_RESET_ALL_MASK);
/* Set to 100 Full as required by cable test */
e100_mdi_write(bdp, MII_BMCR, bdp->phy_addr,
BMCR_SPEED100 | BMCR_FULLDPLX);
/* Test up to 100 times */
for (i = 0; i < 100; i++) {
u16 ctrl_reg;
int distance, open_circut, short_circut, near_end;
/* Enable and execute cable test */
e100_mdi_write(bdp, HWI_CONTROL_REG, bdp->phy_addr,
(HWI_TEST_ENABLE | HWI_TEST_EXECUTE));
/* Wait for cable test finished */
set_current_state(TASK_UNINTERRUPTIBLE);
schedule_timeout(HZ/100 + 1);
/* Read results */
e100_mdi_read(bdp, HWI_CONTROL_REG, bdp->phy_addr, &ctrl_reg);
distance = ctrl_reg & HWI_TEST_DISTANCE;
open_circut = ctrl_reg & HWI_TEST_HIGHZ_PROBLEM;
short_circut = ctrl_reg & HWI_TEST_LOWZ_PROBLEM;
if ((distance == saved_distance) &&
(open_circut == saved_open_circut) &&
(short_circut == saved_short_circut))
saved_same++;
else {
saved_same = 0;
saved_distance = distance;
saved_open_circut = open_circut;
saved_short_circut = short_circut;
}
/* If results are the same 3 times */
if (saved_same == 3) {
near_end = ((distance * HWI_REGISTER_GRANULARITY) <
HWI_NEAR_END_BOUNDARY);
if (open_circut)
cable_status = (near_end) ?
E100_CABLE_OPEN_NEAR : E100_CABLE_OPEN_FAR;
if (short_circut)
cable_status = (near_end) ?
E100_CABLE_SHORT_NEAR : E100_CABLE_SHORT_FAR;
break;
}
}
/* Reset cable test */
e100_mdi_write(bdp, HWI_CONTROL_REG, bdp->phy_addr, HWI_RESET_ALL_MASK);
return cable_status;
}
drivers/net/e100/e100_ucode.h deleted 100644 → 0
View file @ 02a38ad0
/*******************************************************************************
Copyright(c) 1999 - 2003 Intel Corporation. All rights reserved.
This program is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the Free
Software Foundation; either version 2 of the License, or (at your option)
any later version.
This program is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
this program; if not, write to the Free Software Foundation, Inc., 59
Temple Place - Suite 330, Boston, MA 02111-1307, USA.
The full GNU General Public License is included in this distribution in the
file called LICENSE.
Contact Information:
Linux NICS <linux.nics@intel.com>
Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
*******************************************************************************/
#ifndef _E100_UCODE_H_
#define _E100_UCODE_H_
/*
e100_ucode.h
This file contains the loadable micro code arrays to implement receive
bundling on the D101 A-step, D101 B-step, D101M (B-step only), D101S,
D102 B-step, D102 B-step with TCO work around and D102 C-step.
Each controller has its own specific micro code array. The array for one
controller is totally incompatible with any other controller, and if used
will most likely cause the controller to lock up and stop responding to
the driver. Each micro code array has its own parameter offsets (described
below), and they each have their own version number.
*/
/*************************************************************************
* CPUSaver parameters
*
* All CPUSaver parameters are 16-bit literals that are part of a
* "move immediate value" instruction. By changing the value of
* the literal in the instruction before the code is loaded, the
* driver can change algorithm.
*
* CPUSAVER_DWORD - This is the location of the instruction that loads
* the dead-man timer with its inital value. By writing a 16-bit
* value to the low word of this instruction, the driver can change
* the timer value. The current default is either x600 or x800;
* experiments show that the value probably should stay within the
* range of x200 - x1000.
*
* CPUSAVER_BUNDLE_MAX_DWORD - This is the location of the instruction
* that sets the maximum number of frames that will be bundled. In
* some situations, such as the TCP windowing algorithm, it may be
* better to limit the growth of the bundle size than let it go as
* high as it can, because that could cause too much added latency.
* The default is six, because this is the number of packets in the
* default TCP window size. A value of 1 would make CPUSaver indicate
* an interrupt for every frame received. If you do not want to put
* a limit on the bundle size, set this value to xFFFF.
*
* CPUSAVER_MIN_SIZE_DWORD - This is the location of the instruction
* that contains a bit-mask describing the minimum size frame that
* will be bundled. The default masks the lower 7 bits, which means
* that any frame less than 128 bytes in length will not be bundled,
* but will instead immediately generate an interrupt. This does
* not affect the current bundle in any way. Any frame that is 128
* bytes or large will be bundled normally. This feature is meant
* to provide immediate indication of ACK frames in a TCP environment.
* Customers were seeing poor performance when a machine with CPUSaver
* enabled was sending but not receiving. The delay introduced when
* the ACKs were received was enough to reduce total throughput, because
* the sender would sit idle until the ACK was finally seen.
*
* The current default is 0xFF80, which masks out the lower 7 bits.
* This means that any frame which is x7F (127) bytes or smaller
* will cause an immediate interrupt. Because this value must be a
* bit mask, there are only a few valid values that can be used. To
* turn this feature off, the driver can write the value xFFFF to the
* lower word of this instruction (in the same way that the other
* parameters are used). Likewise, a value of 0xF800 (2047) would
* cause an interrupt to be generated for every frame, because all
* standard Ethernet frames are <= 2047 bytes in length.
*************************************************************************/
#ifndef UCODE_MAX_DWORDS
#define UCODE_MAX_DWORDS 134
#endif
/********************************************************/
/* CPUSaver micro code for the D101A */
/********************************************************/
/* Version 2.0 */
/* This value is the same for both A and B step of 558. */
#define D101_CPUSAVER_TIMER_DWORD 72
#define D101_CPUSAVER_BUNDLE_DWORD UCODE_MAX_DWORDS
#define D101_CPUSAVER_MIN_SIZE_DWORD UCODE_MAX_DWORDS
#define D101_A_RCVBUNDLE_UCODE \
{\
0x03B301BB, 0x0046FFFF, 0xFFFFFFFF, 0x051DFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
0x000C0001, 0x00101212, 0x000C0008, 0x003801BC, \
0x00000000, 0x00124818, 0x000C1000, 0x00220809, \
0x00010200, 0x00124818, 0x000CFFFC, 0x003803B5, \
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x0010009C, 0x0024B81D, 0x00130836, 0x000C0001, \
0x0026081C, 0x0020C81B, 0x00130824, 0x00222819, \
0x00101213, 0x00041000, 0x003A03B3, 0x00010200, \
0x00101B13, 0x00238081, 0x00213049, 0x0038003B, \
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x0010009C, 0x0024B83E, 0x00130826, 0x000C0001, \
0x0026083B, 0x00010200, 0x00134824, 0x000C0001, \
0x00101213, 0x00041000, 0x0038051E, 0x00101313, \
0x00010400, 0x00380521, 0x00050600, 0x00100824, \
0x00101310, 0x00041000, 0x00080600, 0x00101B10, \
0x0038051E, 0x00000000, 0x00000000, 0x00000000 \
}
/********************************************************/
/* CPUSaver micro code for the D101B */
/********************************************************/
/* Version 2.0 */
#define D101_B0_RCVBUNDLE_UCODE \
{\
0x03B401BC, 0x0047FFFF, 0xFFFFFFFF, 0x051EFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \
0x000C0001, 0x00101B92, 0x000C0008, 0x003801BD, \
0x00000000, 0x00124818, 0x000C1000, 0x00220809, \
0x00010200, 0x00124818, 0x000CFFFC, 0x003803B6, \
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x0010009C, 0x0024B81D, 0x0013082F, 0x000C0001, \
0x0026081C, 0x0020C81B, 0x00130837, 0x00222819, \
0x00101B93, 0x00041000, 0x003A03B4, 0x00010200, \
0x00101793, 0x00238082, 0x0021304A, 0x0038003C, \
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x0010009C, 0x0024B83E, 0x00130826, 0x000C0001, \
0x0026083B, 0x00010200, 0x00134837, 0x000C0001, \
0x00101B93, 0x00041000, 0x0038051F, 0x00101313, \
0x00010400, 0x00380522, 0x00050600, 0x00100837, \
0x00101310, 0x00041000, 0x00080600, 0x00101790, \
0x0038051F, 0x00000000, 0x00000000, 0x00000000 \
}
/********************************************************/
/* CPUSaver micro code for the D101M (B-step only) */
/********************************************************/
/* Version 2.10.1 */
/* Parameter values for the D101M B-step */
#define D101M_CPUSAVER_TIMER_DWORD 78
#define D101M_CPUSAVER_BUNDLE_DWORD 65
#define D101M_CPUSAVER_MIN_SIZE_DWORD 126
#define D101M_B_RCVBUNDLE_UCODE \
{\
0x00550215, 0xFFFF0437, 0xFFFFFFFF, 0x06A70789, 0xFFFFFFFF, 0x0558FFFF, \
0x000C0001, 0x00101312, 0x000C0008, 0x00380216, \
0x0010009C, 0x00204056, 0x002380CC, 0x00380056, \
0x0010009C, 0x00244C0B, 0x00000800, 0x00124818, \
0x00380438, 0x00000000, 0x00140000, 0x00380555, \
0x00308000, 0x00100662, 0x00100561, 0x000E0408, \
0x00134861, 0x000C0002, 0x00103093, 0x00308000, \
0x00100624, 0x00100561, 0x000E0408, 0x00100861, \
0x000C007E, 0x00222C21, 0x000C0002, 0x00103093, \
0x00380C7A, 0x00080000, 0x00103090, 0x00380C7A, \
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x0010009C, 0x00244C2D, 0x00010004, 0x00041000, \
0x003A0437, 0x00044010, 0x0038078A, 0x00000000, \
0x00100099, 0x00206C7A, 0x0010009C, 0x00244C48, \
0x00130824, 0x000C0001, 0x00101213, 0x00260C75, \
0x00041000, 0x00010004, 0x00130826, 0x000C0006, \
0x002206A8, 0x0013C926, 0x00101313, 0x003806A8, \
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x00080600, 0x00101B10, 0x00050004, 0x00100826, \
0x00101210, 0x00380C34, 0x00000000, 0x00000000, \
0x0021155B, 0x00100099, 0x00206559, 0x0010009C, \
0x00244559, 0x00130836, 0x000C0000, 0x00220C62, \
0x000C0001, 0x00101B13, 0x00229C0E, 0x00210C0E, \
0x00226C0E, 0x00216C0E, 0x0022FC0E, 0x00215C0E, \
0x00214C0E, 0x00380555, 0x00010004, 0x00041000, \
0x00278C67, 0x00040800, 0x00018100, 0x003A0437, \
0x00130826, 0x000C0001, 0x00220559, 0x00101313, \
0x00380559, 0x00000000, 0x00000000, 0x00000000, \
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x00000000, 0x00130831, 0x0010090B, 0x00124813, \
0x000CFF80, 0x002606AB, 0x00041000, 0x00010004, \
0x003806A8, 0x00000000, 0x00000000, 0x00000000, \
}
/********************************************************/
/* CPUSaver micro code for the D101S */
/********************************************************/
/* Version 1.20.1 */
/* Parameter values for the D101S */
#define D101S_CPUSAVER_TIMER_DWORD 78
#define D101S_CPUSAVER_BUNDLE_DWORD 67
#define D101S_CPUSAVER_MIN_SIZE_DWORD 128
#define D101S_RCVBUNDLE_UCODE \
{\
0x00550242, 0xFFFF047E, 0xFFFFFFFF, 0x06FF0818, 0xFFFFFFFF, 0x05A6FFFF, \
0x000C0001, 0x00101312, 0x000C0008, 0x00380243, \
0x0010009C, 0x00204056, 0x002380D0, 0x00380056, \
0x0010009C, 0x00244F8B, 0x00000800, 0x00124818, \
0x0038047F, 0x00000000, 0x00140000, 0x003805A3, \
0x00308000, 0x00100610, 0x00100561, 0x000E0408, \
0x00134861, 0x000C0002, 0x00103093, 0x00308000, \
0x00100624, 0x00100561, 0x000E0408, 0x00100861, \
0x000C007E, 0x00222FA1, 0x000C0002, 0x00103093, \
0x00380F90, 0x00080000, 0x00103090, 0x00380F90, \
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x0010009C, 0x00244FAD, 0x00010004, 0x00041000, \
0x003A047E, 0x00044010, 0x00380819, 0x00000000, \
0x00100099, 0x00206FFD, 0x0010009A, 0x0020AFFD, \
0x0010009C, 0x00244FC8, 0x00130824, 0x000C0001, \
0x00101213, 0x00260FF7, 0x00041000, 0x00010004, \
0x00130826, 0x000C0006, 0x00220700, 0x0013C926, \
0x00101313, 0x00380700, 0x00000000, 0x00000000, \
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x00080600, 0x00101B10, 0x00050004, 0x00100826, \
0x00101210, 0x00380FB6, 0x00000000, 0x00000000, \
0x002115A9, 0x00100099, 0x002065A7, 0x0010009A, \
0x0020A5A7, 0x0010009C, 0x002445A7, 0x00130836, \
0x000C0000, 0x00220FE4, 0x000C0001, 0x00101B13, \
0x00229F8E, 0x00210F8E, 0x00226F8E, 0x00216F8E, \
0x0022FF8E, 0x00215F8E, 0x00214F8E, 0x003805A3, \
0x00010004, 0x00041000, 0x00278FE9, 0x00040800, \
0x00018100, 0x003A047E, 0x00130826, 0x000C0001, \
0x002205A7, 0x00101313, 0x003805A7, 0x00000000, \
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x00000000, 0x00000000, 0x00000000, 0x00130831, \
0x0010090B, 0x00124813, 0x000CFF80, 0x00260703, \
0x00041000, 0x00010004, 0x00380700 \
}
/********************************************************/
/* CPUSaver micro code for the D102 B-step */
/********************************************************/
/* Version 2.0 */
/* Parameter values for the D102 B-step */
#define D102_B_CPUSAVER_TIMER_DWORD 82
#define D102_B_CPUSAVER_BUNDLE_DWORD 106
#define D102_B_CPUSAVER_MIN_SIZE_DWORD 70
#define D102_B_RCVBUNDLE_UCODE \
{\
0x006F0276, 0x0EF71FFF, 0x0ED30F86, 0x0D250ED9, 0x1FFF1FFF, 0x1FFF04D2, \
0x00300001, 0x0140D871, 0x00300008, 0x00E00277, \
0x01406C57, 0x00816073, 0x008700FA, 0x00E00070, \
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x01406CBA, 0x00807F9A, 0x00901F9A, 0x0024FFFF, \
0x014B6F6F, 0x0030FFFE, 0x01407172, 0x01496FBA, \
0x014B6F72, 0x00308000, 0x01406C52, 0x00912EFC, \
0x00E00EF8, 0x00000000, 0x00000000, 0x00000000, \
0x00906F8C, 0x00900F8C, 0x00E00F87, 0x00000000, \
0x00906ED8, 0x01406C55, 0x00E00ED4, 0x00000000, \
0x01406C51, 0x0080DFC2, 0x01406C52, 0x00815FC2, \
0x01406C57, 0x00917FCC, 0x00E01FDD, 0x00000000, \
0x00822D30, 0x01406C51, 0x0080CD26, 0x01406C52, \
0x00814D26, 0x01406C57, 0x00916D26, 0x014C6FD7, \
0x00300000, 0x00841FD2, 0x00300001, 0x0140D772, \
0x00E012B3, 0x014C6F91, 0x0150710B, 0x01496F72, \
0x0030FF80, 0x00940EDD, 0x00102000, 0x00038400, \
0x00E00EDA, 0x00000000, 0x00000000, 0x00000000, \
0x01406C57, 0x00917FE9, 0x00001000, 0x00E01FE9, \
0x00200600, 0x0140D76F, 0x00138400, 0x01406FD8, \
0x0140D96F, 0x00E01FDD, 0x00038400, 0x00102000, \
0x00971FD7, 0x00101000, 0x00050200, 0x00E804D2, \
0x014C6FD8, 0x00300001, 0x00840D26, 0x0140D872, \
0x00E00D26, 0x014C6FD9, 0x00300001, 0x0140D972, \
0x00941FBD, 0x00102000, 0x00038400, 0x014C6FD8, \
0x00300006, 0x00840EDA, 0x014F71D8, 0x0140D872, \
0x00E00EDA, 0x01496F50, 0x00E004D3, 0x00000000, \
}
/********************************************************/
/* Micro code for the D102 C-step */
/********************************************************/
/* Parameter values for the D102 C-step */
#define D102_C_CPUSAVER_TIMER_DWORD 46
#define D102_C_CPUSAVER_BUNDLE_DWORD 74
#define D102_C_CPUSAVER_MIN_SIZE_DWORD 54
#define D102_C_RCVBUNDLE_UCODE \
{ \
0x00700279, 0x0E6604E2, 0x02BF0CAE, 0x1508150C, 0x15190E5B, 0x0E840F13, \
0x00E014D8, 0x00000000, 0x00000000, 0x00000000, \
0x00E014DC, 0x00000000, 0x00000000, 0x00000000, \
0x00E014F4, 0x00000000, 0x00000000, 0x00000000, \
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x00E014E0, 0x00000000, 0x00000000, 0x00000000, \
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x00E014E7, 0x00000000, 0x00000000, 0x00000000, \
0x00141000, 0x015D6F0D, 0x00E002C0, 0x00000000, \
0x00200600, 0x00E0150D, 0x00000000, 0x00000000, \
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x0030FF80, 0x00940E6A, 0x00038200, 0x00102000, \
0x00E00E67, 0x00000000, 0x00000000, 0x00000000, \
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x00906E65, 0x00800E60, 0x00E00E5D, 0x00000000, \
0x00300006, 0x00E0151A, 0x00000000, 0x00000000, \
0x00906F19, 0x00900F19, 0x00E00F14, 0x00000000, \
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x01406CBA, 0x00807FDA, 0x00901FDA, 0x0024FFFF, \
0x014B6F6F, 0x0030FFFE, 0x01407172, 0x01496FBA, \
0x014B6F72, 0x00308000, 0x01406C52, 0x00912E89, \
0x00E00E85, 0x00000000, 0x00000000, 0x00000000 \
}
/********************************************************/
/* Micro code for the D102 E-step */
/********************************************************/
/* Parameter values for the D102 E-step */
#define D102_E_CPUSAVER_TIMER_DWORD 42
#define D102_E_CPUSAVER_BUNDLE_DWORD 54
#define D102_E_CPUSAVER_MIN_SIZE_DWORD 46
#define D102_E_RCVBUNDLE_UCODE \
{\
0x007D028F, 0x0E4204F9, 0x14ED0C85, 0x14FA14E9, 0x1FFF1FFF, 0x1FFF1FFF, \
0x00E014B9, 0x00000000, 0x00000000, 0x00000000, \
0x00E014BD, 0x00000000, 0x00000000, 0x00000000, \
0x00E014D5, 0x00000000, 0x00000000, 0x00000000, \
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x00E014C1, 0x00000000, 0x00000000, 0x00000000, \
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x00000000, 0x00000000, 0x00000000, 0x00000000, \
0x00E014C8, 0x00000000, 0x00000000, 0x00000000, \
0x00200600, 0x00E014EE, 0x00000000, 0x00000000, \
0x0030FF80, 0x00940E46, 0x00038200, 0x00102000, \
0x00E00E43, 0x00000000, 0x00000000, 0x00000000, \
0x00300006, 0x00E014FB, 0x00000000, 0x00000000 \
}
#endif /* _E100_UCODE_H_ */
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