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Commit cb44ec31 authored by Scott Feldman's avatar Scott Feldman Committed by Jeff Garzik
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[netdrvr] e100 version 3 (complete rewrite)

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drivers/net/Kconfig
View file @ cb44ec31
......@@ -1341,8 +1341,9 @@ config EEPRO100_PIO
say N.
config E100
tristate "EtherExpressPro/100 support (e100, Alternate Intel driver)"
tristate "Intel(R) PRO/100+ support"
depends on NET_PCI && PCI
select MII
---help---
This driver supports Intel(R) PRO/100 family of adapters, which
includes:
......@@ -1415,6 +1416,10 @@ config E100
<file:Documentation/networking/net-modules.txt>. The module
will be called e100.
config E100_NAPI
bool "Use Rx Polling (NAPI)"
depends on E100
config LNE390
tristate "Mylex EISA LNE390A/B support (EXPERIMENTAL)"
depends on NET_PCI && EISA && EXPERIMENTAL
......
drivers/net/Makefile
View file @ cb44ec31
......@@ -8,7 +8,6 @@ ifeq ($(CONFIG_ISDN_PPP),y)
obj-$(CONFIG_ISDN) += slhc.o
endif
obj-$(CONFIG_E100) += e100/
obj-$(CONFIG_E1000) += e1000/
obj-$(CONFIG_IXGB) += ixgb/
obj-$(CONFIG_BONDING) += bonding/
......@@ -39,6 +38,7 @@ obj-$(CONFIG_TYPHOON) += typhoon.o
obj-$(CONFIG_NE2K_PCI) += ne2k-pci.o 8390.o
obj-$(CONFIG_PCNET32) += pcnet32.o
obj-$(CONFIG_EEPRO100) += eepro100.o
obj-$(CONFIG_E100) += e100.o
obj-$(CONFIG_TLAN) += tlan.o
obj-$(CONFIG_EPIC100) += epic100.o
obj-$(CONFIG_SIS190) += sis190.o
......
drivers/net/e100.c 0 → 100644
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drivers/net/e100/LICENSE deleted 100644 → 0
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drivers/net/e100/Makefile deleted 100644 → 0
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#
# Makefile for the Intel's E100 ethernet driver
#
obj-$(CONFIG_E100) += e100.o
e100-objs := e100_main.o e100_config.o e100_phy.o \
e100_eeprom.o e100_test.o
drivers/net/e100/e100.h deleted 100644 → 0
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drivers/net/e100/e100_config.c deleted 100644 → 0
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drivers/net/e100/e100_config.h deleted 100644 → 0
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/*******************************************************************************
Copyright(c) 1999 - 2003 Intel Corporation. All rights reserved.
This program is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the Free
Software Foundation; either version 2 of the License, or (at your option)
any later version.
This program is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
this program; if not, write to the Free Software Foundation, Inc., 59
Temple Place - Suite 330, Boston, MA 02111-1307, USA.
The full GNU General Public License is included in this distribution in the
file called LICENSE.
Contact Information:
Linux NICS <linux.nics@intel.com>
Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
*******************************************************************************/
#ifndef _E100_CONFIG_INC_
#define _E100_CONFIG_INC_
#include "e100.h"
#define E100_CONFIG(bdp, X) ((bdp)->config[0] = max_t(u8, (bdp)->config[0], (X)+1))
#define CB_CFIG_MIN_PARAMS 8
/* byte 0 bit definitions*/
#define CB_CFIG_BYTE_COUNT_MASK BIT_0_5 /* Byte count occupies bit 5-0 */
/* byte 1 bit definitions*/
#define CB_CFIG_RXFIFO_LIMIT_MASK BIT_0_4 /* RxFifo limit mask */
#define CB_CFIG_TXFIFO_LIMIT_MASK BIT_4_7 /* TxFifo limit mask */
/* byte 2 bit definitions -- ADAPTIVE_IFS*/
/* word 3 bit definitions -- RESERVED*/
/* Changed for 82558 enhancements */
/* byte 3 bit definitions */
#define CB_CFIG_MWI_EN BIT_0 /* Enable MWI on PCI bus */
#define CB_CFIG_TYPE_EN BIT_1 /* Type Enable */
#define CB_CFIG_READAL_EN BIT_2 /* Enable Read Align */
#define CB_CFIG_TERMCL_EN BIT_3 /* Cache line write */
/* byte 4 bit definitions*/
#define CB_CFIG_RX_MIN_DMA_MASK BIT_0_6 /* Rx minimum DMA count mask */
/* byte 5 bit definitions*/
#define CB_CFIG_TX_MIN_DMA_MASK BIT_0_6 /* Tx minimum DMA count mask */
#define CB_CFIG_DMBC_EN BIT_7 /* Enable Tx/Rx min. DMA counts */
/* Changed for 82558 enhancements */
/* byte 6 bit definitions*/
#define CB_CFIG_LATE_SCB BIT_0 /* Update SCB After New Tx Start */
#define CB_CFIG_DIRECT_DMA_DIS BIT_1 /* Direct DMA mode */
#define CB_CFIG_TNO_INT BIT_2 /* Tx Not OK Interrupt */
#define CB_CFIG_TCO_STAT BIT_2 /* TCO statistics in 559 and above */
#define CB_CFIG_CI_INT BIT_3 /* Command Complete Interrupt */
#define CB_CFIG_EXT_TCB_DIS BIT_4 /* Extended TCB */
#define CB_CFIG_EXT_STAT_DIS BIT_5 /* Extended Stats */
#define CB_CFIG_SAVE_BAD_FRAMES BIT_7 /* Save Bad Frames Enabled */
/* byte 7 bit definitions*/
#define CB_CFIG_DISC_SHORT_FRAMES BIT_0 /* Discard Short Frames */
#define CB_CFIG_DYNTBD_EN BIT_7 /* Enable dynamic TBD */
/* Enable extended RFD's on D102 */
#define CB_CFIG_EXTENDED_RFD BIT_5
/* byte 8 bit definitions*/
#define CB_CFIG_503_MII BIT_0 /* 503 vs. MII mode */
/* byte 9 bit definitions -- pre-defined all zeros*/
#define CB_LINK_STATUS_WOL BIT_5
/* byte 10 bit definitions*/
#define CB_CFIG_NO_SRCADR BIT_3 /* No Source Address Insertion */
#define CB_CFIG_PREAMBLE_LEN BIT_4_5 /* Preamble Length */
#define CB_CFIG_LOOPBACK_MODE BIT_6_7 /* Loopback Mode */
#define CB_CFIG_LOOPBACK_NORMAL 0
#define CB_CFIG_LOOPBACK_INTERNAL BIT_6
#define CB_CFIG_LOOPBACK_EXTERNAL BIT_6_7
/* byte 11 bit definitions*/
#define CB_CFIG_LINEAR_PRIORITY BIT_0_2 /* Linear Priority */
/* byte 12 bit definitions*/
#define CB_CFIG_LINEAR_PRI_MODE BIT_0 /* Linear Priority mode */
#define CB_CFIG_IFS_MASK BIT_4_7 /* Interframe Spacing mask */
/* byte 13 bit definitions -- pre-defined all zeros*/
/* byte 14 bit definitions -- pre-defined 0xf2*/
/* byte 15 bit definitions*/
#define CB_CFIG_PROMISCUOUS BIT_0 /* Promiscuous Mode Enable */
#define CB_CFIG_BROADCAST_DIS BIT_1 /* Broadcast Mode Disable */
#define CB_CFIG_CRS_OR_CDT BIT_7 /* CRS Or CDT */
/* byte 16 bit definitions -- pre-defined all zeros*/
#define DFLT_FC_DELAY_LSB 0x1f /* Delay for outgoing Pause frames */
#define DFLT_NO_FC_DELAY_LSB 0x00 /* no flow control default value */
/* byte 17 bit definitions -- pre-defined 0x40*/
#define DFLT_FC_DELAY_MSB 0x01 /* Delay for outgoing Pause frames */
#define DFLT_NO_FC_DELAY_MSB 0x40 /* no flow control default value */
/* byte 18 bit definitions*/
#define CB_CFIG_STRIPPING BIT_0 /* Padding Disabled */
#define CB_CFIG_PADDING BIT_1 /* Padding Disabled */
#define CB_CFIG_CRC_IN_MEM BIT_2 /* Transfer CRC To Memory */
/* byte 19 bit definitions*/
#define CB_CFIG_TX_ADDR_WAKE BIT_0 /* Address Wakeup */
#define CB_DISABLE_MAGPAK_WAKE BIT_1 /* Magic Packet Wakeup disable */
/* Changed TX_FC_EN to TX_FC_DIS because 0 enables, 1 disables. Jul 8, 1999 */
#define CB_CFIG_TX_FC_DIS BIT_2 /* Tx Flow Control Disable */
#define CB_CFIG_FC_RESTOP BIT_3 /* Rx Flow Control Restop */
#define CB_CFIG_FC_RESTART BIT_4 /* Rx Flow Control Restart */
#define CB_CFIG_FC_REJECT BIT_5 /* Rx Flow Control Restart */
#define CB_CFIG_FC_OPTS (CB_CFIG_FC_RESTOP | CB_CFIG_FC_RESTART | CB_CFIG_FC_REJECT)
/* end 82558/9 specifics */
#define CB_CFIG_FORCE_FDX BIT_6 /* Force Full Duplex */
#define CB_CFIG_FDX_ENABLE BIT_7 /* Full Duplex Enabled */
/* byte 20 bit definitions*/
#define CB_CFIG_MULTI_IA BIT_6 /* Multiple IA Addr */
/* byte 21 bit definitions*/
#define CB_CFIG_MULTICAST_ALL BIT_3 /* Multicast All */
/* byte 22 bit defines */
#define CB_CFIG_RECEIVE_GAMLA_MODE BIT_0 /* D102 receive mode */
#define CB_CFIG_VLAN_DROP_ENABLE BIT_1 /* vlan stripping */
#define CB_CFIG_LONG_RX_OK BIT_3
#define NO_LOOPBACK 0
#define MAC_LOOPBACK 0x01
#define PHY_LOOPBACK 0x02
/* function prototypes */
extern void e100_config_init(struct e100_private *bdp);
extern void e100_config_init_82557(struct e100_private *bdp);
extern unsigned char e100_force_config(struct e100_private *bdp);
extern unsigned char e100_config(struct e100_private *bdp);
extern void e100_config_fc(struct e100_private *bdp);
extern void e100_config_promisc(struct e100_private *bdp, unsigned char enable);
extern void e100_config_brdcast_dsbl(struct e100_private *bdp);
extern void e100_config_mulcast_enbl(struct e100_private *bdp,
unsigned char enable);
extern void e100_config_ifs(struct e100_private *bdp);
extern void e100_config_force_dplx(struct e100_private *bdp);
extern u8 e100_config_loopback_mode(struct e100_private *bdp, u8 mode);
extern u8 e100_config_dynamic_tbd(struct e100_private *bdp, u8 enable);
extern u8 e100_config_tcb_ext_enable(struct e100_private *bdp, u8 enable);
extern void e100_config_vlan_drop(struct e100_private *bdp, unsigned char enable);
#endif /* _E100_CONFIG_INC_ */
drivers/net/e100/e100_eeprom.c deleted 100644 → 0
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drivers/net/e100/e100_main.c deleted 100644 → 0
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drivers/net/e100/e100_phy.c deleted 100644 → 0
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drivers/net/e100/e100_phy.h deleted 100644 → 0
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/*******************************************************************************
Copyright(c) 1999 - 2003 Intel Corporation. All rights reserved.
This program is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the Free
Software Foundation; either version 2 of the License, or (at your option)
any later version.
This program is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
this program; if not, write to the Free Software Foundation, Inc., 59
Temple Place - Suite 330, Boston, MA 02111-1307, USA.
The full GNU General Public License is included in this distribution in the
file called LICENSE.
Contact Information:
Linux NICS <linux.nics@intel.com>
Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
*******************************************************************************/
#ifndef _E100_PHY_INC_
#define _E100_PHY_INC_
#include "e100.h"
/*
* Auto-polarity enable/disable
* e100_autopolarity = 0 => disable auto-polarity
* e100_autopolarity = 1 => enable auto-polarity
* e100_autopolarity = 2 => let software determine
*/
#define E100_AUTOPOLARITY 2
#define IS_NC3133(bdp) (((bdp)->pdev->subsystem_vendor == 0x0E11) && \
((bdp)->pdev->subsystem_device == 0xB0E1))
#define PHY_503 0
#define PHY_100_A 0x000003E0
#define PHY_100_C 0x035002A8
#define PHY_NSC_TX 0x5c002000
#define PHY_82562ET 0x033002A8
#define PHY_82562EM 0x032002A8
#define PHY_82562EH 0x017002A8
#define PHY_82555_TX 0x015002a8 /* added this for 82555 */
#define PHY_OTHER 0xFFFF
#define MAX_PHY_ADDR 31
#define MIN_PHY_ADDR 0
#define PHY_MODEL_REV_ID_MASK 0xFFF0FFFF
#define PHY_DEFAULT_ADDRESS 1
#define PHY_ADDRESS_503 32
/* MDI Control register bit definitions */
#define MDI_PHY_READY BIT_28 /* PHY is ready for next MDI cycle */
#define MDI_NC3133_CONFIG_REG 0x19
#define MDI_NC3133_100FX_ENABLE BIT_2
#define MDI_NC3133_INT_ENABLE_REG 0x17
#define MDI_NC3133_INT_ENABLE BIT_1
/* MDI Control register opcode definitions */
#define MDI_WRITE 1 /* Phy Write */
#define MDI_READ 2 /* Phy read */
/* MDI register set*/
#define AUTO_NEG_NEXT_PAGE_REG 0x07 /* Auto-negotiation next page xmit */
#define EXTENDED_REG_0 0x10 /* Extended reg 0 (Phy 100 modes) */
#define EXTENDED_REG_1 0x14 /* Extended reg 1 (Phy 100 error indications) */
#define NSC_CONG_CONTROL_REG 0x17 /* National (TX) congestion control */
#define NSC_SPEED_IND_REG 0x19 /* National (TX) speed indication */
#define HWI_CONTROL_REG 0x1D /* HWI Control register */
/* MDI/MDI-X Control Register bit definitions */
#define MDI_MDIX_RES_TIMER BIT_0_3 /* minimum slot time for resolution timer */
#define MDI_MDIX_CONFIG_IS_OK BIT_4 /* 1 = resolution algorithm completes OK */
#define MDI_MDIX_STATUS BIT_5 /* 1 = MDIX (croos over), 0 = MDI (straight through) */
#define MDI_MDIX_SWITCH BIT_6 /* 1 = Forces to MDIX, 0 = Forces to MDI */
#define MDI_MDIX_AUTO_SWITCH_ENABLE BIT_7 /* 1 = MDI/MDI-X feature enabled */
#define MDI_MDIX_CONCT_CONFIG BIT_8 /* Sets the MDI/MDI-X connectivity configuration (test prupose only) */
#define MDI_MDIX_CONCT_TEST_ENABLE BIT_9 /* 1 = Enables connectivity testing */
#define MDI_MDIX_RESET_ALL_MASK 0x0000
/* HWI Control Register bit definitions */
#define HWI_TEST_DISTANCE BIT_0_8 /* distance to cable problem */
#define HWI_TEST_HIGHZ_PROBLEM BIT_9 /* 1 = Open Circuit */
#define HWI_TEST_LOWZ_PROBLEM BIT_10 /* 1 = Short Circuit */
#define HWI_TEST_RESERVED (BIT_11 | BIT_12) /* reserved */
#define HWI_TEST_EXECUTE BIT_13 /* 1 = Execute the HWI test on the PHY */
#define HWI_TEST_ABILITY BIT_14 /* 1 = test passed */
#define HWI_TEST_ENABLE BIT_15 /* 1 = Enables the HWI feature */
#define HWI_RESET_ALL_MASK 0x0000
/* ############Start of 82555 specific defines################## */
/* Intel 82555 specific registers */
#define PHY_82555_CSR 0x10 /* 82555 CSR */
#define PHY_82555_SPECIAL_CONTROL 0x11 /* 82555 special control register */
#define PHY_82555_RCV_ERR 0x15 /* 82555 100BaseTx Receive Error
* Frame Counter */
#define PHY_82555_SYMBOL_ERR 0x16 /* 82555 RCV Symbol Error Counter */
#define PHY_82555_PREM_EOF_ERR 0x17 /* 82555 100BaseTx RCV Premature End
* of Frame Error Counter */
#define PHY_82555_EOF_COUNTER 0x18 /* 82555 end of frame error counter */
#define PHY_82555_MDI_EQUALIZER_CSR 0x1a /* 82555 specific equalizer reg. */
/* 82555 CSR bits */
#define PHY_82555_SPEED_BIT BIT_1
#define PHY_82555_POLARITY_BIT BIT_8
/* 82555 equalizer reg. opcodes */
#define ENABLE_ZERO_FORCING 0x2010 /* write to ASD conf. reg. 0 */
#define DISABLE_ZERO_FORCING 0x2000 /* write to ASD conf. reg. 0 */
/* 82555 special control reg. opcodes */
#define DISABLE_AUTO_POLARITY 0x0010
#define EXTENDED_SQUELCH_BIT BIT_2
/* ############End of 82555 specific defines##################### */
/* Auto-Negotiation advertisement register bit definitions*/
#define NWAY_AD_FC_SUPPORTED 0x0400 /* Flow Control supported */
/* Auto-Negotiation link partner ability register bit definitions*/
#define NWAY_LP_ABILITY 0x07e0 /* technologies supported */
/* PHY 100 Extended Register 0 bit definitions*/
#define PHY_100_ER0_FDX_INDIC BIT_0 /* 1 = FDX, 0 = half duplex */
#define PHY_100_ER0_SPEED_INDIC BIT_1 /* 1 = 100Mbps, 0= 10Mbps */
/* National Semiconductor TX phy congestion control register bit definitions*/
#define NSC_TX_CONG_TXREADY BIT_10 /* Makes TxReady an input */
#define NSC_TX_CONG_ENABLE BIT_8 /* Enables congestion control */
/* National Semiconductor TX phy speed indication register bit definitions*/
#define NSC_TX_SPD_INDC_SPEED BIT_6 /* 0 = 100Mbps, 1=10Mbps */
/************* function prototypes ************/
extern unsigned char e100_phy_init(struct e100_private *bdp);
extern unsigned char e100_update_link_state(struct e100_private *bdp);
extern unsigned char e100_phy_check(struct e100_private *bdp);
extern void e100_phy_set_speed_duplex(struct e100_private *bdp,
unsigned char force_restart);
extern void e100_phy_autoneg(struct e100_private *bdp);
extern void e100_phy_reset(struct e100_private *bdp);
extern void e100_phy_set_loopback(struct e100_private *bdp);
extern int e100_mdi_write(struct e100_private *, u32, u32, u16);
extern int e100_mdi_read(struct e100_private *, u32, u32, u16 *);
#endif
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