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Commit cdb54c44 authored by Paul Walmsley's avatar Paul Walmsley
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OMAP4: PRCM: rename _MOD macros to _INST 

Back in the OMAP2/3 PRCM interface days, the macros that referred to
the offsets of individual PRM/CM instances from the top of the PRM/CM
hardware modules were incorrectly suffixed with "_MOD".  (They should
have been suffixed with something like "_INST" or "_INSTANCE".)  These
days, now that we have better contact with the OMAP hardware people,
we know that this naming is wrong.  And in fact in OMAP4, there are
actual hardware module offsets inside the instances, so the incorrect
naming gets confusing very quickly for anyone who knows the hardware.

Fix this naming for OMAP4, before things get too far along, by
changing "_MOD" to "_INST" on the end of these macros.  So, for
example, OMAP4430_CM2_INSTR_MOD becomes OMAP4430_CM2_INSTR_INST.

This unfortunately creates quite a large diff, but it is a
straightforward rename.  This patch should not result in any
functional changes.

The autogeneration scripts have been updated accordingly.
Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
Cc: Benoît Cousson <b-cousson@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Reviewed-by: default avatarKevin Hilman <khilman@deeprootsystems.com>
Tested-by: default avatarKevin Hilman <khilman@deeprootsystems.com>
Tested-by: default avatarSantosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: default avatarRajendra Nayak <rnayak@ti.com>
parent 0f318fd5
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Showing with 718 additions and 730 deletions
arch/arm/mach-omap2/cm1_44xx.h
View file @ cdb54c44
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arch/arm/mach-omap2/cm2_44xx.h
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arch/arm/mach-omap2/powerdomains44xx_data.c
View file @ cdb54c44
......@@ -34,7 +34,7 @@
/* core_44xx_pwrdm: CORE power domain */
static struct powerdomain core_44xx_pwrdm = {
.name = "core_pwrdm",
.prcm_offs = OMAP4430_PRM_CORE_MOD,
.prcm_offs = OMAP4430_PRM_CORE_INST,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
.pwrsts = PWRSTS_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
......@@ -59,7 +59,7 @@ static struct powerdomain core_44xx_pwrdm = {
/* gfx_44xx_pwrdm: 3D accelerator power domain */
static struct powerdomain gfx_44xx_pwrdm = {
.name = "gfx_pwrdm",
.prcm_offs = OMAP4430_PRM_GFX_MOD,
.prcm_offs = OMAP4430_PRM_GFX_INST,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
.pwrsts = PWRSTS_OFF_ON,
.banks = 1,
......@@ -75,7 +75,7 @@ static struct powerdomain gfx_44xx_pwrdm = {
/* abe_44xx_pwrdm: Audio back end power domain */
static struct powerdomain abe_44xx_pwrdm = {
.name = "abe_pwrdm",
.prcm_offs = OMAP4430_PRM_ABE_MOD,
.prcm_offs = OMAP4430_PRM_ABE_INST,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRDM_POWER_OFF,
......@@ -94,7 +94,7 @@ static struct powerdomain abe_44xx_pwrdm = {
/* dss_44xx_pwrdm: Display subsystem power domain */
static struct powerdomain dss_44xx_pwrdm = {
.name = "dss_pwrdm",
.prcm_offs = OMAP4430_PRM_DSS_MOD,
.prcm_offs = OMAP4430_PRM_DSS_INST,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF,
......@@ -111,7 +111,7 @@ static struct powerdomain dss_44xx_pwrdm = {
/* tesla_44xx_pwrdm: Tesla processor power domain */
static struct powerdomain tesla_44xx_pwrdm = {
.name = "tesla_pwrdm",
.prcm_offs = OMAP4430_PRM_TESLA_MOD,
.prcm_offs = OMAP4430_PRM_TESLA_INST,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
......@@ -132,7 +132,7 @@ static struct powerdomain tesla_44xx_pwrdm = {
/* wkup_44xx_pwrdm: Wake-up power domain */
static struct powerdomain wkup_44xx_pwrdm = {
.name = "wkup_pwrdm",
.prcm_offs = OMAP4430_PRM_WKUP_MOD,
.prcm_offs = OMAP4430_PRM_WKUP_INST,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
.pwrsts = PWRSTS_ON,
.banks = 1,
......@@ -147,7 +147,7 @@ static struct powerdomain wkup_44xx_pwrdm = {
/* cpu0_44xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
static struct powerdomain cpu0_44xx_pwrdm = {
.name = "cpu0_pwrdm",
.prcm_offs = OMAP4430_PRCM_MPU_CPU0_MOD,
.prcm_offs = OMAP4430_PRCM_MPU_CPU0_INST,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
......@@ -163,7 +163,7 @@ static struct powerdomain cpu0_44xx_pwrdm = {
/* cpu1_44xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
static struct powerdomain cpu1_44xx_pwrdm = {
.name = "cpu1_pwrdm",
.prcm_offs = OMAP4430_PRCM_MPU_CPU1_MOD,
.prcm_offs = OMAP4430_PRCM_MPU_CPU1_INST,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
......@@ -179,7 +179,7 @@ static struct powerdomain cpu1_44xx_pwrdm = {
/* emu_44xx_pwrdm: Emulation power domain */
static struct powerdomain emu_44xx_pwrdm = {
.name = "emu_pwrdm",
.prcm_offs = OMAP4430_PRM_EMU_MOD,
.prcm_offs = OMAP4430_PRM_EMU_INST,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
.pwrsts = PWRSTS_OFF_ON,
.banks = 1,
......@@ -194,7 +194,7 @@ static struct powerdomain emu_44xx_pwrdm = {
/* mpu_44xx_pwrdm: Modena processor and the Neon coprocessor power domain */
static struct powerdomain mpu_44xx_pwrdm = {
.name = "mpu_pwrdm",
.prcm_offs = OMAP4430_PRM_MPU_MOD,
.prcm_offs = OMAP4430_PRM_MPU_INST,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
......@@ -214,7 +214,7 @@ static struct powerdomain mpu_44xx_pwrdm = {
/* ivahd_44xx_pwrdm: IVA-HD power domain */
static struct powerdomain ivahd_44xx_pwrdm = {
.name = "ivahd_pwrdm",
.prcm_offs = OMAP4430_PRM_IVAHD_MOD,
.prcm_offs = OMAP4430_PRM_IVAHD_INST,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRDM_POWER_OFF,
......@@ -237,7 +237,7 @@ static struct powerdomain ivahd_44xx_pwrdm = {
/* cam_44xx_pwrdm: Camera subsystem power domain */
static struct powerdomain cam_44xx_pwrdm = {
.name = "cam_pwrdm",
.prcm_offs = OMAP4430_PRM_CAM_MOD,
.prcm_offs = OMAP4430_PRM_CAM_INST,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
.pwrsts = PWRSTS_OFF_ON,
.banks = 1,
......@@ -253,7 +253,7 @@ static struct powerdomain cam_44xx_pwrdm = {
/* l3init_44xx_pwrdm: L3 initators pheripherals power domain */
static struct powerdomain l3init_44xx_pwrdm = {
.name = "l3init_pwrdm",
.prcm_offs = OMAP4430_PRM_L3INIT_MOD,
.prcm_offs = OMAP4430_PRM_L3INIT_INST,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
......@@ -270,7 +270,7 @@ static struct powerdomain l3init_44xx_pwrdm = {
/* l4per_44xx_pwrdm: Target peripherals power domain */
static struct powerdomain l4per_44xx_pwrdm = {
.name = "l4per_pwrdm",
.prcm_offs = OMAP4430_PRM_L4PER_MOD,
.prcm_offs = OMAP4430_PRM_L4PER_INST,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
.pwrsts = PWRSTS_OFF_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
......@@ -292,7 +292,7 @@ static struct powerdomain l4per_44xx_pwrdm = {
*/
static struct powerdomain always_on_core_44xx_pwrdm = {
.name = "always_on_core_pwrdm",
.prcm_offs = OMAP4430_PRM_ALWAYS_ON_MOD,
.prcm_offs = OMAP4430_PRM_ALWAYS_ON_INST,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
.pwrsts = PWRSTS_ON,
};
......@@ -300,7 +300,7 @@ static struct powerdomain always_on_core_44xx_pwrdm = {
/* cefuse_44xx_pwrdm: Customer efuse controller power domain */
static struct powerdomain cefuse_44xx_pwrdm = {
.name = "cefuse_pwrdm",
.prcm_offs = OMAP4430_PRM_CEFUSE_MOD,
.prcm_offs = OMAP4430_PRM_CEFUSE_INST,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
.pwrsts = PWRSTS_OFF_ON,
};
......
arch/arm/mach-omap2/prcm.c
View file @ cdb54c44
......@@ -146,7 +146,7 @@ void omap_prcm_arch_reset(char mode, const char *cmd)
prcm_offs = OMAP3430_GR_MOD;
omap3_ctrl_write_boot_mode((cmd ? (u8)*cmd : 0));
} else if (cpu_is_omap44xx())
prcm_offs = OMAP4430_PRM_DEVICE_MOD;
prcm_offs = OMAP4430_PRM_DEVICE_INST;
else
WARN_ON(1);
......
arch/arm/mach-omap2/prcm_mpu44xx.h
View file @ cdb54c44
......@@ -27,15 +27,15 @@
#define OMAP4430_PRCM_MPU_BASE 0x48243000
#define OMAP44XX_PRCM_MPU_REGADDR(module, reg) \
OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (module) + (reg))
#define OMAP44XX_PRCM_MPU_REGADDR(inst, reg) \
OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (inst) + (reg))
/* PRCM_MPU instances */
#define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_MOD 0x0000
#define OMAP4430_PRCM_MPU_DEVICE_PRM_MOD 0x0200
#define OMAP4430_PRCM_MPU_CPU0_MOD 0x0400
#define OMAP4430_PRCM_MPU_CPU1_MOD 0x0800
#define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST 0x0000
#define OMAP4430_PRCM_MPU_DEVICE_PRM_INST 0x0200
#define OMAP4430_PRCM_MPU_CPU0_INST 0x0400
#define OMAP4430_PRCM_MPU_CPU1_INST 0x0800
/*
* PRCM_MPU
......@@ -48,44 +48,44 @@
/* PRCM_MPU.OCP_SOCKET_PRCM register offsets */
#define OMAP4_REVISION_PRCM_OFFSET 0x0000
#define OMAP4430_REVISION_PRCM OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_MOD, 0x0000)
#define OMAP4430_REVISION_PRCM OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST, 0x0000)
/* PRCM_MPU.DEVICE_PRM register offsets */
#define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 0x0000
#define OMAP4430_PRCM_MPU_PRM_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_MOD, 0x0000)
#define OMAP4430_PRCM_MPU_PRM_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0000)
#define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 0x0004
#define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_MOD, 0x0004)
#define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0004)
/* PRCM_MPU.CPU0 register offsets */
#define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET 0x0000
#define OMAP4430_PM_CPU0_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0000)
#define OMAP4430_PM_CPU0_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0000)
#define OMAP4_PM_CPU0_PWRSTST_OFFSET 0x0004
#define OMAP4430_PM_CPU0_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0004)
#define OMAP4430_PM_CPU0_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0004)
#define OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0008
#define OMAP4430_RM_CPU0_CPU0_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0008)
#define OMAP4430_RM_CPU0_CPU0_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0008)
#define OMAP4_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x000c
#define OMAP4430_RM_CPU0_CPU0_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x000c)
#define OMAP4430_RM_CPU0_CPU0_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x000c)
#define OMAP4_RM_CPU0_CPU0_RSTST_OFFSET 0x0010
#define OMAP4430_RM_CPU0_CPU0_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0010)
#define OMAP4430_RM_CPU0_CPU0_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0010)
#define OMAP4_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0014
#define OMAP4430_CM_CPU0_CPU0_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0014)
#define OMAP4430_CM_CPU0_CPU0_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0014)
#define OMAP4_CM_CPU0_CLKSTCTRL_OFFSET 0x0018
#define OMAP4430_CM_CPU0_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_MOD, 0x0018)
#define OMAP4430_CM_CPU0_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0018)
/* PRCM_MPU.CPU1 register offsets */
#define OMAP4_PM_CPU1_PWRSTCTRL_OFFSET 0x0000
#define OMAP4430_PM_CPU1_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0000)
#define OMAP4430_PM_CPU1_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0000)
#define OMAP4_PM_CPU1_PWRSTST_OFFSET 0x0004
#define OMAP4430_PM_CPU1_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0004)
#define OMAP4430_PM_CPU1_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0004)
#define OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0008
#define OMAP4430_RM_CPU1_CPU1_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0008)
#define OMAP4430_RM_CPU1_CPU1_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0008)
#define OMAP4_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x000c
#define OMAP4430_RM_CPU1_CPU1_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x000c)
#define OMAP4430_RM_CPU1_CPU1_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x000c)
#define OMAP4_RM_CPU1_CPU1_RSTST_OFFSET 0x0010
#define OMAP4430_RM_CPU1_CPU1_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0010)
#define OMAP4430_RM_CPU1_CPU1_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0010)
#define OMAP4_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0014
#define OMAP4430_CM_CPU1_CPU1_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0014)
#define OMAP4430_CM_CPU1_CPU1_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0014)
#define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET 0x0018
#define OMAP4430_CM_CPU1_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_MOD, 0x0018)
#define OMAP4430_CM_CPU1_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0018)
#endif
arch/arm/mach-omap2/prm44xx.h
View file @ cdb54c44
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