Commit ce171780 authored by Zou Nan hai's avatar Zou Nan hai Committed by Eric Anholt

drm/i915: Enable RC6 on Ironlake.

RC6 allows the GPU to enter a lower power state when the GPU is idle.
Signed-off-by: default avatarZou Nan hai <nanhai.zou@intel.com>
[anholt: Fixed the !renderctx error path to actually not enable RC6.]
Signed-off-by: default avatarEric Anholt <eric@anholt.net>
parent 8545423a
...@@ -5753,7 +5753,8 @@ void intel_init_clock_gating(struct drm_device *dev) ...@@ -5753,7 +5753,8 @@ void intel_init_clock_gating(struct drm_device *dev)
ILK_DPFC_DIS2 | ILK_DPFC_DIS2 |
ILK_CLK_FBC); ILK_CLK_FBC);
} }
return; if (IS_GEN6(dev))
return;
} else if (IS_G4X(dev)) { } else if (IS_G4X(dev)) {
uint32_t dspclk_gate; uint32_t dspclk_gate;
I915_WRITE(RENCLK_GATE_D1, 0); I915_WRITE(RENCLK_GATE_D1, 0);
...@@ -5814,9 +5815,11 @@ void intel_init_clock_gating(struct drm_device *dev) ...@@ -5814,9 +5815,11 @@ void intel_init_clock_gating(struct drm_device *dev)
OUT_RING(MI_FLUSH); OUT_RING(MI_FLUSH);
ADVANCE_LP_RING(); ADVANCE_LP_RING();
} }
} else } else {
DRM_DEBUG_KMS("Failed to allocate render context." DRM_DEBUG_KMS("Failed to allocate render context."
"Disable RC6\n"); "Disable RC6\n");
return;
}
} }
if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) { if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
......
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