Commit d6e3af54 authored by Uma Shankar's avatar Uma Shankar Committed by Jani Nikula

drm/i915/bxt: Remove DSP CLK_GATE programming for BXT

DSP CLK_GATE registers are specific to BYT and CHT.
Avoid programming the same for BXT platform.

v2: Rebased on latest drm nightly branch.

v3: Fixed Jani's review comments
Signed-off-by: default avatarUma Shankar <uma.shankar@intel.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1455796166-13052-1-git-send-email-jani.nikula@intel.com
parent 4d800030
...@@ -634,7 +634,6 @@ static void intel_dsi_post_disable(struct intel_encoder *encoder) ...@@ -634,7 +634,6 @@ static void intel_dsi_post_disable(struct intel_encoder *encoder)
{ {
struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
u32 val;
DRM_DEBUG_KMS("\n"); DRM_DEBUG_KMS("\n");
...@@ -642,9 +641,13 @@ static void intel_dsi_post_disable(struct intel_encoder *encoder) ...@@ -642,9 +641,13 @@ static void intel_dsi_post_disable(struct intel_encoder *encoder)
intel_dsi_clear_device_ready(encoder); intel_dsi_clear_device_ready(encoder);
val = I915_READ(DSPCLK_GATE_D); if (!IS_BROXTON(dev_priv)) {
val &= ~DPOUNIT_CLOCK_GATE_DISABLE; u32 val;
I915_WRITE(DSPCLK_GATE_D, val);
val = I915_READ(DSPCLK_GATE_D);
val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
I915_WRITE(DSPCLK_GATE_D, val);
}
drm_panel_unprepare(intel_dsi->panel); drm_panel_unprepare(intel_dsi->panel);
......
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