Commit d99659a0 authored by Tao Zhou's avatar Tao Zhou Committed by Alex Deucher

drm/amdgpu: rename umc ras_init to err_cnt_init

this interface is related to specific version of umc, distinguish it
from ras_late_init
Signed-off-by: default avatarTao Zhou <tao.zhou1@amd.com>
Reviewed-by: default avatarGuchun Chen <guchun.chen@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 4930aabe
...@@ -63,8 +63,8 @@ int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, void *ras_ih_info) ...@@ -63,8 +63,8 @@ int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, void *ras_ih_info)
} }
/* ras init of specific umc version */ /* ras init of specific umc version */
if (adev->umc.funcs && adev->umc.funcs->ras_init) if (adev->umc.funcs && adev->umc.funcs->err_cnt_init)
adev->umc.funcs->ras_init(adev); adev->umc.funcs->err_cnt_init(adev);
return 0; return 0;
......
...@@ -54,7 +54,7 @@ ...@@ -54,7 +54,7 @@
adev->umc.funcs->disable_umc_index_mode(adev); adev->umc.funcs->disable_umc_index_mode(adev);
struct amdgpu_umc_funcs { struct amdgpu_umc_funcs {
void (*ras_init)(struct amdgpu_device *adev); void (*err_cnt_init)(struct amdgpu_device *adev);
int (*ras_late_init)(struct amdgpu_device *adev, void *ras_ih_info); int (*ras_late_init)(struct amdgpu_device *adev, void *ras_ih_info);
void (*query_ras_error_count)(struct amdgpu_device *adev, void (*query_ras_error_count)(struct amdgpu_device *adev,
void *ras_error_status); void *ras_error_status);
......
...@@ -234,7 +234,7 @@ static void umc_v6_1_query_ras_error_address(struct amdgpu_device *adev, ...@@ -234,7 +234,7 @@ static void umc_v6_1_query_ras_error_address(struct amdgpu_device *adev,
amdgpu_umc_for_each_channel(umc_v6_1_query_error_address); amdgpu_umc_for_each_channel(umc_v6_1_query_error_address);
} }
static void umc_v6_1_ras_init_per_channel(struct amdgpu_device *adev, static void umc_v6_1_err_cnt_init_per_channel(struct amdgpu_device *adev,
struct ras_err_data *err_data, struct ras_err_data *err_data,
uint32_t umc_reg_offset, uint32_t channel_index) uint32_t umc_reg_offset, uint32_t channel_index)
{ {
...@@ -264,15 +264,15 @@ static void umc_v6_1_ras_init_per_channel(struct amdgpu_device *adev, ...@@ -264,15 +264,15 @@ static void umc_v6_1_ras_init_per_channel(struct amdgpu_device *adev,
WREG32(ecc_err_cnt_addr + umc_reg_offset, UMC_V6_1_CE_CNT_INIT); WREG32(ecc_err_cnt_addr + umc_reg_offset, UMC_V6_1_CE_CNT_INIT);
} }
static void umc_v6_1_ras_init(struct amdgpu_device *adev) static void umc_v6_1_err_cnt_init(struct amdgpu_device *adev)
{ {
void *ras_error_status = NULL; void *ras_error_status = NULL;
amdgpu_umc_for_each_channel(umc_v6_1_ras_init_per_channel); amdgpu_umc_for_each_channel(umc_v6_1_err_cnt_init_per_channel);
} }
const struct amdgpu_umc_funcs umc_v6_1_funcs = { const struct amdgpu_umc_funcs umc_v6_1_funcs = {
.ras_init = umc_v6_1_ras_init, .err_cnt_init = umc_v6_1_err_cnt_init,
.ras_late_init = amdgpu_umc_ras_late_init, .ras_late_init = amdgpu_umc_ras_late_init,
.query_ras_error_count = umc_v6_1_query_ras_error_count, .query_ras_error_count = umc_v6_1_query_ras_error_count,
.query_ras_error_address = umc_v6_1_query_ras_error_address, .query_ras_error_address = umc_v6_1_query_ras_error_address,
......
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