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Commit da52faa5 authored by Linus Walleij's avatar Linus Walleij
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Merge branch 'pinmux/next/pin-no-gpio' of git://linuxtv.org/pinchartl/fbdev into devel 

Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parents f29bdca0 4f82e3ee
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Showing with 3275 additions and 3673 deletions
drivers/pinctrl/sh-pfc/core.c
View file @ da52faa5
......@@ -82,24 +82,20 @@ int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
unsigned int offset;
unsigned int i;
if (pfc->info->ranges == NULL)
return pin;
for (i = 0, offset = 0; i < pfc->info->nr_ranges; ++i) {
const struct pinmux_range *range = &pfc->info->ranges[i];
for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
const struct sh_pfc_pin_range *range = &pfc->ranges[i];
if (pin <= range->end)
return pin >= range->begin
? offset + pin - range->begin : -1;
return pin >= range->start
? offset + pin - range->start : -1;
offset += range->end - range->begin + 1;
offset += range->end - range->start + 1;
}
return -EINVAL;
}
static int sh_pfc_enum_in_range(pinmux_enum_t enum_id,
const struct pinmux_range *r)
static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
{
if (enum_id < r->begin)
return 0;
......@@ -194,7 +190,7 @@ static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
}
static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id,
static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
const struct pinmux_cfg_reg **crp, int *fieldp,
int *valuep)
{
......@@ -238,10 +234,10 @@ static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id,
return -EINVAL;
}
static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, pinmux_enum_t mark, int pos,
pinmux_enum_t *enum_idp)
static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
u16 *enum_idp)
{
const pinmux_enum_t *data = pfc->info->gpio_data;
const u16 *data = pfc->info->gpio_data;
int k;
if (pos) {
......@@ -264,7 +260,7 @@ static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, pinmux_enum_t mark, int pos,
int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
{
const struct pinmux_cfg_reg *cr = NULL;
pinmux_enum_t enum_id;
u16 enum_id;
const struct pinmux_range *range;
int in_range, pos, field, value;
int ret;
......@@ -283,14 +279,6 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
range = &pfc->info->input;
break;
case PINMUX_TYPE_INPUT_PULLUP:
range = &pfc->info->input_pu;
break;
case PINMUX_TYPE_INPUT_PULLDOWN:
range = &pfc->info->input_pd;
break;
default:
return -EINVAL;
}
......@@ -350,6 +338,67 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
return 0;
}
static int sh_pfc_init_ranges(struct sh_pfc *pfc)
{
struct sh_pfc_pin_range *range;
unsigned int nr_ranges;
unsigned int i;
if (pfc->info->pins[0].pin == (u16)-1) {
/* Pin number -1 denotes that the SoC doesn't report pin numbers
* in its pin arrays yet. Consider the pin numbers range as
* continuous and allocate a single range.
*/
pfc->nr_ranges = 1;
pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges),
GFP_KERNEL);
if (pfc->ranges == NULL)
return -ENOMEM;
pfc->ranges->start = 0;
pfc->ranges->end = pfc->info->nr_pins - 1;
pfc->nr_gpio_pins = pfc->info->nr_pins;
return 0;
}
/* Count, allocate and fill the ranges. The PFC SoC data pins array must
* be sorted by pin numbers, and pins without a GPIO port must come
* last.
*/
for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
nr_ranges++;
}
pfc->nr_ranges = nr_ranges;
pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges) * nr_ranges,
GFP_KERNEL);
if (pfc->ranges == NULL)
return -ENOMEM;
range = pfc->ranges;
range->start = pfc->info->pins[0].pin;
for (i = 1; i < pfc->info->nr_pins; ++i) {
if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
continue;
range->end = pfc->info->pins[i-1].pin;
if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
pfc->nr_gpio_pins = range->end + 1;
range++;
range->start = pfc->info->pins[i].pin;
}
range->end = pfc->info->pins[i-1].pin;
if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
pfc->nr_gpio_pins = range->end + 1;
return 0;
}
#ifdef CONFIG_OF
static const struct of_device_id sh_pfc_of_table[] = {
#ifdef CONFIG_PINCTRL_PFC_R8A73A4
......@@ -440,6 +489,10 @@ static int sh_pfc_probe(struct platform_device *pdev)
pinctrl_provide_dummies();
ret = sh_pfc_init_ranges(pfc);
if (ret < 0)
return ret;
/*
* Initialize pinctrl bindings first
*/
......
drivers/pinctrl/sh-pfc/core.h
View file @ da52faa5
......@@ -25,6 +25,11 @@ struct sh_pfc_window {
struct sh_pfc_chip;
struct sh_pfc_pinctrl;
struct sh_pfc_pin_range {
u16 start;
u16 end;
};
struct sh_pfc {
struct device *dev;
const struct sh_pfc_soc_info *info;
......@@ -34,7 +39,10 @@ struct sh_pfc {
unsigned int num_windows;
struct sh_pfc_window *window;
unsigned int nr_pins;
struct sh_pfc_pin_range *ranges;
unsigned int nr_ranges;
unsigned int nr_gpio_pins;
struct sh_pfc_chip *gpio;
struct sh_pfc_chip *func;
......
drivers/pinctrl/sh-pfc/gpio.c
View file @ da52faa5
......@@ -48,11 +48,11 @@ static struct sh_pfc *gpio_to_pfc(struct gpio_chip *gc)
return gpio_to_pfc_chip(gc)->pfc;
}
static void gpio_get_data_reg(struct sh_pfc_chip *chip, unsigned int gpio,
static void gpio_get_data_reg(struct sh_pfc_chip *chip, unsigned int offset,
struct sh_pfc_gpio_data_reg **reg,
unsigned int *bit)
{
int idx = sh_pfc_get_pin_index(chip->pfc, gpio);
int idx = sh_pfc_get_pin_index(chip->pfc, offset);
struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[idx];
*reg = &chip->regs[gpio_pin->dreg];
......@@ -76,11 +76,11 @@ static void gpio_write_data_reg(struct sh_pfc_chip *chip,
sh_pfc_write_raw_reg(mem, dreg->reg_width, value);
}
static void gpio_setup_data_reg(struct sh_pfc_chip *chip, unsigned gpio)
static void gpio_setup_data_reg(struct sh_pfc_chip *chip, unsigned idx)
{
struct sh_pfc *pfc = chip->pfc;
struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[gpio];
const struct sh_pfc_pin *pin = &pfc->info->pins[gpio];
struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[idx];
const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
const struct pinmux_data_reg *dreg;
unsigned int bit;
unsigned int i;
......@@ -224,8 +224,8 @@ static int gpio_pin_setup(struct sh_pfc_chip *chip)
struct gpio_chip *gc = &chip->gpio_chip;
int ret;
chip->pins = devm_kzalloc(pfc->dev, pfc->nr_pins * sizeof(*chip->pins),
GFP_KERNEL);
chip->pins = devm_kzalloc(pfc->dev, pfc->info->nr_pins *
sizeof(*chip->pins), GFP_KERNEL);
if (chip->pins == NULL)
return -ENOMEM;
......@@ -245,7 +245,7 @@ static int gpio_pin_setup(struct sh_pfc_chip *chip)
gc->dev = pfc->dev;
gc->owner = THIS_MODULE;
gc->base = 0;
gc->ngpio = pfc->nr_pins;
gc->ngpio = pfc->nr_gpio_pins;
return 0;
}
......@@ -293,7 +293,7 @@ static int gpio_function_setup(struct sh_pfc_chip *chip)
gc->label = pfc->info->name;
gc->owner = THIS_MODULE;
gc->base = pfc->nr_pins;
gc->base = pfc->nr_gpio_pins;
gc->ngpio = pfc->info->nr_func_gpios;
return 0;
......@@ -334,10 +334,7 @@ sh_pfc_add_gpiochip(struct sh_pfc *pfc, int(*setup)(struct sh_pfc_chip *),
int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
{
const struct pinmux_range *ranges;
struct pinmux_range def_range;
struct sh_pfc_chip *chip;
unsigned int nr_ranges;
unsigned int i;
int ret;
......@@ -367,24 +364,20 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
pfc->gpio = chip;
/* Register the GPIO to pin mappings. */
if (pfc->info->ranges == NULL) {
def_range.begin = 0;
def_range.end = pfc->info->nr_pins - 1;
ranges = &def_range;
nr_ranges = 1;
} else {
ranges = pfc->info->ranges;
nr_ranges = pfc->info->nr_ranges;
}
/* Register the GPIO to pin mappings. As pins with GPIO ports must come
* first in the ranges, skip the pins without GPIO ports by stopping at
* the first range that contains such a pin.
*/
for (i = 0; i < pfc->nr_ranges; ++i) {
const struct sh_pfc_pin_range *range = &pfc->ranges[i];
for (i = 0; i < nr_ranges; ++i) {
const struct pinmux_range *range = &ranges[i];
if (range->start >= pfc->nr_gpio_pins)
break;
ret = gpiochip_add_pin_range(&chip->gpio_chip,
dev_name(pfc->dev),
range->begin, range->begin,
range->end - range->begin + 1);
range->start, range->start,
range->end - range->start + 1);
if (ret < 0)
return ret;
}
......
drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
View file @ da52faa5
......@@ -28,78 +28,78 @@
#define CPU_ALL_PORT(fn, pfx, sfx) \
/* Port0 - Port30 */ \
PORT_10(fn, pfx, sfx), \
PORT_10(fn, pfx##1, sfx), \
PORT_10(fn, pfx##2, sfx), \
PORT_1(fn, pfx##30, sfx), \
PORT_10(0, fn, pfx, sfx), \
PORT_10(10, fn, pfx##1, sfx), \
PORT_10(20, fn, pfx##2, sfx), \
PORT_1(30, fn, pfx##30, sfx), \
/* Port32 - Port40 */ \
PORT_1(fn, pfx##32, sfx), PORT_1(fn, pfx##33, sfx), \
PORT_1(fn, pfx##34, sfx), PORT_1(fn, pfx##35, sfx), \
PORT_1(fn, pfx##36, sfx), PORT_1(fn, pfx##37, sfx), \
PORT_1(fn, pfx##38, sfx), PORT_1(fn, pfx##39, sfx), \
PORT_1(fn, pfx##40, sfx), \
PORT_1(32, fn, pfx##32, sfx), PORT_1(33, fn, pfx##33, sfx), \
PORT_1(34, fn, pfx##34, sfx), PORT_1(35, fn, pfx##35, sfx), \
PORT_1(36, fn, pfx##36, sfx), PORT_1(37, fn, pfx##37, sfx), \
PORT_1(38, fn, pfx##38, sfx), PORT_1(39, fn, pfx##39, sfx), \
PORT_1(40, fn, pfx##40, sfx), \
/* Port64 - Port85 */ \
PORT_1(fn, pfx##64, sfx), PORT_1(fn, pfx##65, sfx), \
PORT_1(fn, pfx##66, sfx), PORT_1(fn, pfx##67, sfx), \
PORT_1(fn, pfx##68, sfx), PORT_1(fn, pfx##69, sfx), \
PORT_10(fn, pfx##7, sfx), \
PORT_1(fn, pfx##80, sfx), PORT_1(fn, pfx##81, sfx), \
PORT_1(fn, pfx##82, sfx), PORT_1(fn, pfx##83, sfx), \
PORT_1(fn, pfx##84, sfx), PORT_1(fn, pfx##85, sfx), \
PORT_1(64, fn, pfx##64, sfx), PORT_1(65, fn, pfx##65, sfx), \
PORT_1(66, fn, pfx##66, sfx), PORT_1(67, fn, pfx##67, sfx), \
PORT_1(68, fn, pfx##68, sfx), PORT_1(69, fn, pfx##69, sfx), \
PORT_10(70, fn, pfx##7, sfx), \
PORT_1(80, fn, pfx##80, sfx), PORT_1(81, fn, pfx##81, sfx), \
PORT_1(82, fn, pfx##82, sfx), PORT_1(83, fn, pfx##83, sfx), \
PORT_1(84, fn, pfx##84, sfx), PORT_1(85, fn, pfx##85, sfx), \
/* Port96 - Port126 */ \
PORT_1(fn, pfx##96, sfx), PORT_1(fn, pfx##97, sfx), \
PORT_1(fn, pfx##98, sfx), PORT_1(fn, pfx##99, sfx), \
PORT_10(fn, pfx##10, sfx), \
PORT_10(fn, pfx##11, sfx), \
PORT_1(fn, pfx##120, sfx), PORT_1(fn, pfx##121, sfx), \
PORT_1(fn, pfx##122, sfx), PORT_1(fn, pfx##123, sfx), \
PORT_1(fn, pfx##124, sfx), PORT_1(fn, pfx##125, sfx), \
PORT_1(fn, pfx##126, sfx), \
PORT_1(96, fn, pfx##96, sfx), PORT_1(97, fn, pfx##97, sfx), \
PORT_1(98, fn, pfx##98, sfx), PORT_1(99, fn, pfx##99, sfx), \
PORT_10(100, fn, pfx##10, sfx), \
PORT_10(110, fn, pfx##11, sfx), \
PORT_1(120, fn, pfx##120, sfx), PORT_1(121, fn, pfx##121, sfx), \
PORT_1(122, fn, pfx##122, sfx), PORT_1(123, fn, pfx##123, sfx), \
PORT_1(124, fn, pfx##124, sfx), PORT_1(125, fn, pfx##125, sfx), \
PORT_1(126, fn, pfx##126, sfx), \
/* Port128 - Port134 */ \
PORT_1(fn, pfx##128, sfx), PORT_1(fn, pfx##129, sfx), \
PORT_1(fn, pfx##130, sfx), PORT_1(fn, pfx##131, sfx), \
PORT_1(fn, pfx##132, sfx), PORT_1(fn, pfx##133, sfx), \
PORT_1(fn, pfx##134, sfx), \
PORT_1(128, fn, pfx##128, sfx), PORT_1(129, fn, pfx##129, sfx), \
PORT_1(130, fn, pfx##130, sfx), PORT_1(131, fn, pfx##131, sfx), \
PORT_1(132, fn, pfx##132, sfx), PORT_1(133, fn, pfx##133, sfx), \
PORT_1(134, fn, pfx##134, sfx), \
/* Port160 - Port178 */ \
PORT_10(fn, pfx##16, sfx), \
PORT_1(fn, pfx##170, sfx), PORT_1(fn, pfx##171, sfx), \
PORT_1(fn, pfx##172, sfx), PORT_1(fn, pfx##173, sfx), \
PORT_1(fn, pfx##174, sfx), PORT_1(fn, pfx##175, sfx), \
PORT_1(fn, pfx##176, sfx), PORT_1(fn, pfx##177, sfx), \
PORT_1(fn, pfx##178, sfx), \
PORT_10(160, fn, pfx##16, sfx), \
PORT_1(170, fn, pfx##170, sfx), PORT_1(171, fn, pfx##171, sfx), \
PORT_1(172, fn, pfx##172, sfx), PORT_1(173, fn, pfx##173, sfx), \
PORT_1(174, fn, pfx##174, sfx), PORT_1(175, fn, pfx##175, sfx), \
PORT_1(176, fn, pfx##176, sfx), PORT_1(177, fn, pfx##177, sfx), \
PORT_1(178, fn, pfx##178, sfx), \
/* Port192 - Port222 */ \
PORT_1(fn, pfx##192, sfx), PORT_1(fn, pfx##193, sfx), \
PORT_1(fn, pfx##194, sfx), PORT_1(fn, pfx##195, sfx), \
PORT_1(fn, pfx##196, sfx), PORT_1(fn, pfx##197, sfx), \
PORT_1(fn, pfx##198, sfx), PORT_1(fn, pfx##199, sfx), \
PORT_10(fn, pfx##20, sfx), \
PORT_10(fn, pfx##21, sfx), \
PORT_1(fn, pfx##220, sfx), PORT_1(fn, pfx##221, sfx), \
PORT_1(fn, pfx##222, sfx), \
PORT_1(192, fn, pfx##192, sfx), PORT_1(193, fn, pfx##193, sfx), \
PORT_1(194, fn, pfx##194, sfx), PORT_1(195, fn, pfx##195, sfx), \
PORT_1(196, fn, pfx##196, sfx), PORT_1(197, fn, pfx##197, sfx), \
PORT_1(198, fn, pfx##198, sfx), PORT_1(199, fn, pfx##199, sfx), \
PORT_10(200, fn, pfx##20, sfx), \
PORT_10(210, fn, pfx##21, sfx), \
PORT_1(220, fn, pfx##220, sfx), PORT_1(221, fn, pfx##221, sfx), \
PORT_1(222, fn, pfx##222, sfx), \
/* Port224 - Port250 */ \
PORT_1(fn, pfx##224, sfx), PORT_1(fn, pfx##225, sfx), \
PORT_1(fn, pfx##226, sfx), PORT_1(fn, pfx##227, sfx), \
PORT_1(fn, pfx##228, sfx), PORT_1(fn, pfx##229, sfx), \
PORT_10(fn, pfx##23, sfx), \
PORT_10(fn, pfx##24, sfx), \
PORT_1(fn, pfx##250, sfx), \
PORT_1(224, fn, pfx##224, sfx), PORT_1(225, fn, pfx##225, sfx), \
PORT_1(226, fn, pfx##226, sfx), PORT_1(227, fn, pfx##227, sfx), \
PORT_1(228, fn, pfx##228, sfx), PORT_1(229, fn, pfx##229, sfx), \
PORT_10(230, fn, pfx##23, sfx), \
PORT_10(240, fn, pfx##24, sfx), \
PORT_1(250, fn, pfx##250, sfx), \
/* Port256 - Port283 */ \
PORT_1(fn, pfx##256, sfx), PORT_1(fn, pfx##257, sfx), \
PORT_1(fn, pfx##258, sfx), PORT_1(fn, pfx##259, sfx), \
PORT_10(fn, pfx##26, sfx), \
PORT_10(fn, pfx##27, sfx), \
PORT_1(fn, pfx##280, sfx), PORT_1(fn, pfx##281, sfx), \
PORT_1(fn, pfx##282, sfx), PORT_1(fn, pfx##283, sfx), \
PORT_1(256, fn, pfx##256, sfx), PORT_1(257, fn, pfx##257, sfx), \
PORT_1(258, fn, pfx##258, sfx), PORT_1(259, fn, pfx##259, sfx), \
PORT_10(260, fn, pfx##26, sfx), \
PORT_10(270, fn, pfx##27, sfx), \
PORT_1(280, fn, pfx##280, sfx), PORT_1(281, fn, pfx##281, sfx), \
PORT_1(282, fn, pfx##282, sfx), PORT_1(283, fn, pfx##283, sfx), \
/* Port288 - Port308 */ \
PORT_1(fn, pfx##288, sfx), PORT_1(fn, pfx##289, sfx), \
PORT_10(fn, pfx##29, sfx), \
PORT_1(fn, pfx##300, sfx), PORT_1(fn, pfx##301, sfx), \
PORT_1(fn, pfx##302, sfx), PORT_1(fn, pfx##303, sfx), \
PORT_1(fn, pfx##304, sfx), PORT_1(fn, pfx##305, sfx), \
PORT_1(fn, pfx##306, sfx), PORT_1(fn, pfx##307, sfx), \
PORT_1(fn, pfx##308, sfx), \
PORT_1(288, fn, pfx##288, sfx), PORT_1(289, fn, pfx##289, sfx), \
PORT_10(290, fn, pfx##29, sfx), \
PORT_1(300, fn, pfx##300, sfx), PORT_1(301, fn, pfx##301, sfx), \
PORT_1(302, fn, pfx##302, sfx), PORT_1(303, fn, pfx##303, sfx), \
PORT_1(304, fn, pfx##304, sfx), PORT_1(305, fn, pfx##305, sfx), \
PORT_1(306, fn, pfx##306, sfx), PORT_1(307, fn, pfx##307, sfx), \
PORT_1(308, fn, pfx##308, sfx), \
/* Port320 - Port329 */ \
PORT_10(fn, pfx##32, sfx)
PORT_10(320, fn, pfx##32, sfx)
enum {
......@@ -428,10 +428,7 @@ enum {
PINMUX_MARK_END,
};
#define _PORT_DATA(pfx, sfx) PORT_DATA_IO(pfx)
#define PINMUX_DATA_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
static const pinmux_enum_t pinmux_data[] = {
static const u16 pinmux_data[] = {
/* specify valid pin states for each pin in GPIO mode */
PINMUX_DATA_ALL(),
......@@ -1269,19 +1266,12 @@ static const pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(IRQ57_MARK, PORT329_FN0),
};
#define R8A73A4_PIN(pin, cfgs) \
{ \
.name = __stringify(PORT##pin), \
.enum_id = PORT##pin##_DATA, \
.configs = cfgs, \
}
#define __O (SH_PFC_PIN_CFG_OUTPUT)
#define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
#define R8A73A4_PIN_IO_PU_PD(pin) R8A73A4_PIN(pin, __IO | __PUD)
#define R8A73A4_PIN_O(pin) R8A73A4_PIN(pin, __O)
#define R8A73A4_PIN_IO_PU_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PUD)
#define R8A73A4_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O)
static struct sh_pfc_pin pinmux_pins[] = {
R8A73A4_PIN_IO_PU_PD(0), R8A73A4_PIN_IO_PU_PD(1),
......@@ -1408,20 +1398,6 @@ static struct sh_pfc_pin pinmux_pins[] = {
R8A73A4_PIN_IO_PU_PD(328), R8A73A4_PIN_IO_PU_PD(329),
};
static const struct pinmux_range pinmux_ranges[] = {
{.begin = 0, .end = 30,},
{.begin = 32, .end = 40,},
{.begin = 64, .end = 85,},
{.begin = 96, .end = 126,},
{.begin = 128, .end = 134,},
{.begin = 160, .end = 178,},
{.begin = 192, .end = 222,},
{.begin = 224, .end = 250,},
{.begin = 256, .end = 283,},
{.begin = 288, .end = 308,},
{.begin = 320, .end = 329,},
};
/* - IRQC ------------------------------------------------------------------- */
#define IRQC_PINS_MUX(pin, irq_mark) \
static const unsigned int irqc_irq##irq_mark##_pins[] = { \
......@@ -2766,9 +2742,6 @@ const struct sh_pfc_soc_info r8a73a4_pinmux_info = {
.pins = pinmux_pins,
.nr_pins = ARRAY_SIZE(pinmux_pins),
.ranges = pinmux_ranges,
.nr_ranges = ARRAY_SIZE(pinmux_ranges),
.groups = pinmux_groups,
.nr_groups = ARRAY_SIZE(pinmux_groups),
.functions = pinmux_functions,
......
drivers/pinctrl/sh-pfc/pfc-r8a7740.c
View file @ da52faa5
......@@ -29,17 +29,10 @@
#include "sh_pfc.h"
#define CPU_ALL_PORT(fn, pfx, sfx) \
PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \
PORT_10(fn, pfx##10, sfx), PORT_90(fn, pfx##1, sfx), \
PORT_10(fn, pfx##20, sfx), \
PORT_1(fn, pfx##210, sfx), PORT_1(fn, pfx##211, sfx)
#undef _GPIO_PORT
#define _GPIO_PORT(gpio, sfx) \
[gpio] = { \
.name = __stringify(PORT##gpio), \
.enum_id = PORT##gpio##_DATA, \
}
PORT_10(0, fn, pfx, sfx), PORT_90(0, fn, pfx, sfx), \
PORT_10(100, fn, pfx##10, sfx), PORT_90(100, fn, pfx##1, sfx), \
PORT_10(200, fn, pfx##20, sfx), \
PORT_1(210, fn, pfx##210, sfx), PORT_1(211, fn, pfx##211, sfx)
#define IRQC_PIN_MUX(irq, pin) \
static const unsigned int intc_irq##irq##_pins[] = { \
......@@ -590,11 +583,8 @@ enum {
PINMUX_MARK_END,
};
#define _PORT_DATA(pfx, sfx) PORT_DATA_IO(pfx)
#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
static const pinmux_enum_t pinmux_data[] = {
PINMUX_DATA_GP_ALL(),
static const u16 pinmux_data[] = {
PINMUX_DATA_ALL(),
/* Port0 */
PINMUX_DATA(DBGMDT2_MARK, PORT0_FN1),
......@@ -1537,13 +1527,6 @@ static const pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK, MSEL5CR_30_1, MSEL5CR_29_0),
};
#define R8A7740_PIN(pin, cfgs) \
{ \
.name = __stringify(PORT##pin), \
.enum_id = PORT##pin##_DATA, \
.configs = cfgs, \
}
#define __I (SH_PFC_PIN_CFG_INPUT)
#define __O (SH_PFC_PIN_CFG_OUTPUT)
#define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
......@@ -1551,15 +1534,15 @@ static const pinmux_enum_t pinmux_data[] = {
#define __PU (SH_PFC_PIN_CFG_PULL_UP)
#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
#define R8A7740_PIN_I_PD(pin) R8A7740_PIN(pin, __I | __PD)
#define R8A7740_PIN_I_PU(pin) R8A7740_PIN(pin, __I | __PU)
#define R8A7740_PIN_I_PU_PD(pin) R8A7740_PIN(pin, __I | __PUD)
#define R8A7740_PIN_IO(pin) R8A7740_PIN(pin, __IO)
#define R8A7740_PIN_IO_PD(pin) R8A7740_PIN(pin, __IO | __PD)
#define R8A7740_PIN_IO_PU(pin) R8A7740_PIN(pin, __IO | __PU)
#define R8A7740_PIN_IO_PU_PD(pin) R8A7740_PIN(pin, __IO | __PUD)
#define R8A7740_PIN_O(pin) R8A7740_PIN(pin, __O)
#define R8A7740_PIN_O_PU_PD(pin) R8A7740_PIN(pin, __O | __PUD)
#define R8A7740_PIN_I_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PD)
#define R8A7740_PIN_I_PU(pin) SH_PFC_PIN_CFG(pin, __I | __PU)
#define R8A7740_PIN_I_PU_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PUD)
#define R8A7740_PIN_IO(pin) SH_PFC_PIN_CFG(pin, __IO)
#define R8A7740_PIN_IO_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PD)
#define R8A7740_PIN_IO_PU(pin) SH_PFC_PIN_CFG(pin, __IO | __PU)
#define R8A7740_PIN_IO_PU_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PUD)
#define R8A7740_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O)
#define R8A7740_PIN_O_PU_PD(pin) SH_PFC_PIN_CFG(pin, __O | __PUD)
static struct sh_pfc_pin pinmux_pins[] = {
/* Table 56-1 (I/O and Pull U/D) */
......
drivers/pinctrl/sh-pfc/pfc-r8a7778.c
View file @ da52faa5
......@@ -23,26 +23,6 @@
#include <linux/kernel.h>
#include "sh_pfc.h"
#define PORT_GP_1(bank, pin, fn, sfx) fn(bank, pin, GP_##bank##_##pin, sfx)
#define PORT_GP_32(bank, fn, sfx) \
PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \
PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \
PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \
PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \
PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \
PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \
PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \
PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \
PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \
PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \
PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \
PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \
PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx), \
PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx), \
PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx), \
PORT_GP_1(bank, 30, fn, sfx), PORT_GP_1(bank, 31, fn, sfx)
#define PORT_GP_27(bank, fn, sfx) \
PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \
PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \
......@@ -66,26 +46,6 @@
PORT_GP_32(3, fn, sfx), \
PORT_GP_27(4, fn, sfx)
#define _GP_PORT_ALL(bank, pin, name, sfx) name##_##sfx
#define _GP_GPIO(bank, pin, _name, sfx) \
[RCAR_GP_PIN(bank, pin)] = { \
.name = __stringify(_name), \
.enum_id = _name##_DATA, \
}
#define _GP_DATA(bank, pin, name, sfx) \
PINMUX_DATA(name##_DATA, name##_FN)
#define GP_ALL(str) CPU_ALL_PORT(_GP_PORT_ALL, str)
#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused)
#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused)
#define PINMUX_IPSR_NOGP(ispr, fn) PINMUX_DATA(fn##_MARK, FN_##fn)
#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr)
#define PINMUX_IPSR_MSEL(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr, FN_##ms)
#define PINMUX_IPSR_NOGM(ispr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ms)
enum {
PINMUX_RESERVED = 0,
......@@ -579,7 +539,7 @@ enum {
PINMUX_MARK_END,
};
static const pinmux_enum_t pinmux_data[] = {
static const u16 pinmux_data[] = {
PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
PINMUX_DATA(PENC0_MARK, FN_PENC0),
......@@ -1294,16 +1254,21 @@ static const pinmux_enum_t pinmux_data[] = {
PINMUX_IPSR_MSEL(IP10_24_22, CAN_CLK_C, SEL_CANCLK_C),
};
static struct sh_pfc_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
};
/* Pin numbers for pins without a corresponding GPIO port number are computed
* from the row and column numbers with a 1000 offset to avoid collisions with
* GPIO port numbers.
*/
#define PIN_NUMBER(row, col) (1000+((row)-1)*25+(col)-1)
static struct sh_pfc_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
/* Pins not associated with a GPIO port */
SH_PFC_PIN_NAMED(3, 20, C20),
SH_PFC_PIN_NAMED(20, 1, T1),
SH_PFC_PIN_NAMED(25, 2, Y2),
};
/* - macro */
#define SH_PFC_PINS(name, args...) \
static const unsigned int name ##_pins[] = { args }
......
drivers/pinctrl/sh-pfc/pfc-r8a7779.c
View file @ da52faa5
......@@ -24,51 +24,13 @@
#include "sh_pfc.h"
#define PORT_GP_1(bank, pin, fn, sfx) fn(bank, pin, GP_##bank##_##pin, sfx)
#define PORT_GP_32(bank, fn, sfx) \
PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \
PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \
PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \
PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \
PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \
PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \
PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \
PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \
PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \
PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \
PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \
PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \
PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx), \
PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx), \
PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx), \
PORT_GP_1(bank, 30, fn, sfx), PORT_GP_1(bank, 31, fn, sfx)
#define PORT_GP_32_9(bank, fn, sfx) \
#define PORT_GP_9(bank, fn, sfx) \
PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \
PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \
PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \
PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \
PORT_GP_1(bank, 8, fn, sfx)
#define PORT_GP_32_REV(bank, fn, sfx) \
PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \
PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \
PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \
PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \
PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \
PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \
PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \
PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \
PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx), \
PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx), \
PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx), \
PORT_GP_1(bank, 9, fn, sfx), PORT_GP_1(bank, 8, fn, sfx), \
PORT_GP_1(bank, 7, fn, sfx), PORT_GP_1(bank, 6, fn, sfx), \
PORT_GP_1(bank, 5, fn, sfx), PORT_GP_1(bank, 4, fn, sfx), \
PORT_GP_1(bank, 3, fn, sfx), PORT_GP_1(bank, 2, fn, sfx), \
PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx)
#define CPU_ALL_PORT(fn, sfx) \
PORT_GP_32(0, fn, sfx), \
PORT_GP_32(1, fn, sfx), \
......@@ -76,26 +38,7 @@
PORT_GP_32(3, fn, sfx), \
PORT_GP_32(4, fn, sfx), \
PORT_GP_32(5, fn, sfx), \
PORT_GP_32_9(6, fn, sfx)
#define _GP_PORT_ALL(bank, pin, name, sfx) name##_##sfx
#define _GP_GPIO(bank, pin, _name, sfx) \
[RCAR_GP_PIN(bank, pin)] = { \
.name = __stringify(_name), \
.enum_id = _name##_DATA, \
}
#define _GP_DATA(bank, pin, name, sfx) \
PINMUX_DATA(name##_DATA, name##_FN)
#define GP_ALL(str) CPU_ALL_PORT(_GP_PORT_ALL, str)
#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused)
#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused)
#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
FN_##ipsr, FN_##fn)
PORT_GP_9(6, fn, sfx)
enum {
PINMUX_RESERVED = 0,
......@@ -664,7 +607,7 @@ enum {
PINMUX_MARK_END,
};
static const pinmux_enum_t pinmux_data[] = {
static const u16 pinmux_data[] = {
PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
PINMUX_DATA(AVS1_MARK, FN_AVS1),
......
drivers/pinctrl/sh-pfc/pfc-r8a7790.c
View file @ da52faa5
......@@ -27,44 +27,6 @@
#include "core.h"
#include "sh_pfc.h"
#define PORT_GP_1(bank, pin, fn, sfx) fn(bank, pin, GP_##bank##_##pin, sfx)
#define PORT_GP_32(bank, fn, sfx) \
PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \
PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \
PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \
PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \
PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \
PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \
PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \
PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \
PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \
PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \
PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \
PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \
PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx), \
PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx), \
PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx), \
PORT_GP_1(bank, 30, fn, sfx), PORT_GP_1(bank, 31, fn, sfx)
#define PORT_GP_32_REV(bank, fn, sfx) \
PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \
PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \
PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \
PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \
PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \
PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \
PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \
PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \
PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx), \
PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx), \
PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx), \
PORT_GP_1(bank, 9, fn, sfx), PORT_GP_1(bank, 8, fn, sfx), \
PORT_GP_1(bank, 7, fn, sfx), PORT_GP_1(bank, 6, fn, sfx), \
PORT_GP_1(bank, 5, fn, sfx), PORT_GP_1(bank, 4, fn, sfx), \
PORT_GP_1(bank, 3, fn, sfx), PORT_GP_1(bank, 2, fn, sfx), \
PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx)
#define CPU_ALL_PORT(fn, sfx) \
PORT_GP_32(0, fn, sfx), \
PORT_GP_32(1, fn, sfx), \
......@@ -73,25 +35,6 @@
PORT_GP_32(4, fn, sfx), \
PORT_GP_32(5, fn, sfx)
#define _GP_PORT_ALL(bank, pin, name, sfx) name##_##sfx
#define _GP_GPIO(bank, pin, _name, sfx) \
[(bank * 32) + pin] = { \
.name = __stringify(_name), \
.enum_id = _name##_DATA, \
}
#define _GP_DATA(bank, pin, name, sfx) \
PINMUX_DATA(name##_DATA, name##_FN)
#define GP_ALL(str) CPU_ALL_PORT(_GP_PORT_ALL, str)
#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused)
#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused)
#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
FN_##ipsr, FN_##fn)
enum {
PINMUX_RESERVED = 0,
......@@ -844,7 +787,7 @@ enum {
PINMUX_MARK_END,
};
static const pinmux_enum_t pinmux_data[] = {
static const u16 pinmux_data[] = {
PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
PINMUX_DATA(VI1_DATA7_VI1_B7_MARK, FN_VI1_DATA7_VI1_B7),
......
drivers/pinctrl/sh-pfc/pfc-sh7203.c
View file @ da52faa5
......@@ -272,8 +272,7 @@ enum {
PINMUX_MARK_END,
};
static const pinmux_enum_t pinmux_data[] = {
static const u16 pinmux_data[] = {
/* PA */
PINMUX_DATA(PA7_DATA, PA7_IN),
PINMUX_DATA(PA6_DATA, PA6_IN),
......@@ -704,117 +703,116 @@ static const pinmux_enum_t pinmux_data[] = {
};
static struct sh_pfc_pin pinmux_pins[] = {
/* PA */
PINMUX_GPIO(GPIO_PA7, PA7_DATA),
PINMUX_GPIO(GPIO_PA6, PA6_DATA),
PINMUX_GPIO(GPIO_PA5, PA5_DATA),
PINMUX_GPIO(GPIO_PA4, PA4_DATA),
PINMUX_GPIO(GPIO_PA3, PA3_DATA),
PINMUX_GPIO(GPIO_PA2, PA2_DATA),
PINMUX_GPIO(GPIO_PA1, PA1_DATA),
PINMUX_GPIO(GPIO_PA0, PA0_DATA),
PINMUX_GPIO(PA7),
PINMUX_GPIO(PA6),
PINMUX_GPIO(PA5),
PINMUX_GPIO(PA4),
PINMUX_GPIO(PA3),
PINMUX_GPIO(PA2),
PINMUX_GPIO(PA1),
PINMUX_GPIO(PA0),
/* PB */
PINMUX_GPIO(GPIO_PB12, PB12_DATA),
PINMUX_GPIO(GPIO_PB11, PB11_DATA),
PINMUX_GPIO(GPIO_PB10, PB10_DATA),
PINMUX_GPIO(GPIO_PB9, PB9_DATA),
PINMUX_GPIO(GPIO_PB8, PB8_DATA),
PINMUX_GPIO(GPIO_PB7, PB7_DATA),
PINMUX_GPIO(GPIO_PB6, PB6_DATA),
PINMUX_GPIO(GPIO_PB5, PB5_DATA),
PINMUX_GPIO(GPIO_PB4, PB4_DATA),
PINMUX_GPIO(GPIO_PB3, PB3_DATA),
PINMUX_GPIO(GPIO_PB2, PB2_DATA),
PINMUX_GPIO(GPIO_PB1, PB1_DATA),
PINMUX_GPIO(GPIO_PB0, PB0_DATA),
PINMUX_GPIO(PB12),
PINMUX_GPIO(PB11),
PINMUX_GPIO(PB10),
PINMUX_GPIO(PB9),
PINMUX_GPIO(PB8),
PINMUX_GPIO(PB7),
PINMUX_GPIO(PB6),
PINMUX_GPIO(PB5),
PINMUX_GPIO(PB4),
PINMUX_GPIO(PB3),
PINMUX_GPIO(PB2),
PINMUX_GPIO(PB1),
PINMUX_GPIO(PB0),
/* PC */
PINMUX_GPIO(GPIO_PC14, PC14_DATA),
PINMUX_GPIO(GPIO_PC13, PC13_DATA),
PINMUX_GPIO(GPIO_PC12, PC12_DATA),
PINMUX_GPIO(GPIO_PC11, PC11_DATA),
PINMUX_GPIO(GPIO_PC10, PC10_DATA),
PINMUX_GPIO(GPIO_PC9, PC9_DATA),
PINMUX_GPIO(GPIO_PC8, PC8_DATA),
PINMUX_GPIO(GPIO_PC7, PC7_DATA),
PINMUX_GPIO(GPIO_PC6, PC6_DATA),
PINMUX_GPIO(GPIO_PC5, PC5_DATA),
PINMUX_GPIO(GPIO_PC4, PC4_DATA),
PINMUX_GPIO(GPIO_PC3, PC3_DATA),
PINMUX_GPIO(GPIO_PC2, PC2_DATA),
PINMUX_GPIO(GPIO_PC1, PC1_DATA),
PINMUX_GPIO(GPIO_PC0, PC0_DATA),
PINMUX_GPIO(PC14),
PINMUX_GPIO(PC13),
PINMUX_GPIO(PC12),
PINMUX_GPIO(PC11),
PINMUX_GPIO(PC10),
PINMUX_GPIO(PC9),
PINMUX_GPIO(PC8),
PINMUX_GPIO(PC7),
PINMUX_GPIO(PC6),
PINMUX_GPIO(PC5),
PINMUX_GPIO(PC4),
PINMUX_GPIO(PC3),
PINMUX_GPIO(PC2),
PINMUX_GPIO(PC1),
PINMUX_GPIO(PC0),
/* PD */
PINMUX_GPIO(GPIO_PD15, PD15_DATA),
PINMUX_GPIO(GPIO_PD14, PD14_DATA),
PINMUX_GPIO(GPIO_PD13, PD13_DATA),
PINMUX_GPIO(GPIO_PD12, PD12_DATA),
PINMUX_GPIO(GPIO_PD11, PD11_DATA),
PINMUX_GPIO(GPIO_PD10, PD10_DATA),
PINMUX_GPIO(GPIO_PD9, PD9_DATA),
PINMUX_GPIO(GPIO_PD8, PD8_DATA),
PINMUX_GPIO(GPIO_PD7, PD7_DATA),
PINMUX_GPIO(GPIO_PD6, PD6_DATA),
PINMUX_GPIO(GPIO_PD5, PD5_DATA),
PINMUX_GPIO(GPIO_PD4, PD4_DATA),
PINMUX_GPIO(GPIO_PD3, PD3_DATA),
PINMUX_GPIO(GPIO_PD2, PD2_DATA),
PINMUX_GPIO(GPIO_PD1, PD1_DATA),
PINMUX_GPIO(GPIO_PD0, PD0_DATA),
PINMUX_GPIO(PD15),
PINMUX_GPIO(PD14),
PINMUX_GPIO(PD13),
PINMUX_GPIO(PD12),
PINMUX_GPIO(PD11),
PINMUX_GPIO(PD10),
PINMUX_GPIO(PD9),
PINMUX_GPIO(PD8),
PINMUX_GPIO(PD7),
PINMUX_GPIO(PD6),
PINMUX_GPIO(PD5),
PINMUX_GPIO(PD4),
PINMUX_GPIO(PD3),
PINMUX_GPIO(PD2),
PINMUX_GPIO(PD1),
PINMUX_GPIO(PD0),
/* PE */
PINMUX_GPIO(GPIO_PE15, PE15_DATA),
PINMUX_GPIO(GPIO_PE14, PE14_DATA),
PINMUX_GPIO(GPIO_PE13, PE13_DATA),
PINMUX_GPIO(GPIO_PE12, PE12_DATA),
PINMUX_GPIO(GPIO_PE11, PE11_DATA),
PINMUX_GPIO(GPIO_PE10, PE10_DATA),
PINMUX_GPIO(GPIO_PE9, PE9_DATA),
PINMUX_GPIO(GPIO_PE8, PE8_DATA),
PINMUX_GPIO(GPIO_PE7, PE7_DATA),
PINMUX_GPIO(GPIO_PE6, PE6_DATA),
PINMUX_GPIO(GPIO_PE5, PE5_DATA),
PINMUX_GPIO(GPIO_PE4, PE4_DATA),
PINMUX_GPIO(GPIO_PE3, PE3_DATA),
PINMUX_GPIO(GPIO_PE2, PE2_DATA),
PINMUX_GPIO(GPIO_PE1, PE1_DATA),
PINMUX_GPIO(GPIO_PE0, PE0_DATA),
PINMUX_GPIO(PE15),
PINMUX_GPIO(PE14),
PINMUX_GPIO(PE13),
PINMUX_GPIO(PE12),
PINMUX_GPIO(PE11),
PINMUX_GPIO(PE10),
PINMUX_GPIO(PE9),
PINMUX_GPIO(PE8),
PINMUX_GPIO(PE7),
PINMUX_GPIO(PE6),
PINMUX_GPIO(PE5),
PINMUX_GPIO(PE4),
PINMUX_GPIO(PE3),
PINMUX_GPIO(PE2),
PINMUX_GPIO(PE1),
PINMUX_GPIO(PE0),
/* PF */
PINMUX_GPIO(GPIO_PF30, PF30_DATA),
PINMUX_GPIO(GPIO_PF29, PF29_DATA),
PINMUX_GPIO(GPIO_PF28, PF28_DATA),
PINMUX_GPIO(GPIO_PF27, PF27_DATA),
PINMUX_GPIO(GPIO_PF26, PF26_DATA),
PINMUX_GPIO(GPIO_PF25, PF25_DATA),
PINMUX_GPIO(GPIO_PF24, PF24_DATA),
PINMUX_GPIO(GPIO_PF23, PF23_DATA),
PINMUX_GPIO(GPIO_PF22, PF22_DATA),
PINMUX_GPIO(GPIO_PF21, PF21_DATA),
PINMUX_GPIO(GPIO_PF20, PF20_DATA),
PINMUX_GPIO(GPIO_PF19, PF19_DATA),
PINMUX_GPIO(GPIO_PF18, PF18_DATA),
PINMUX_GPIO(GPIO_PF17, PF17_DATA),
PINMUX_GPIO(GPIO_PF16, PF16_DATA),
PINMUX_GPIO(GPIO_PF15, PF15_DATA),
PINMUX_GPIO(GPIO_PF14, PF14_DATA),
PINMUX_GPIO(GPIO_PF13, PF13_DATA),
PINMUX_GPIO(GPIO_PF12, PF12_DATA),
PINMUX_GPIO(GPIO_PF11, PF11_DATA),
PINMUX_GPIO(GPIO_PF10, PF10_DATA),
PINMUX_GPIO(GPIO_PF9, PF9_DATA),
PINMUX_GPIO(GPIO_PF8, PF8_DATA),
PINMUX_GPIO(GPIO_PF7, PF7_DATA),
PINMUX_GPIO(GPIO_PF6, PF6_DATA),
PINMUX_GPIO(GPIO_PF5, PF5_DATA),
PINMUX_GPIO(GPIO_PF4, PF4_DATA),
PINMUX_GPIO(GPIO_PF3, PF3_DATA),
PINMUX_GPIO(GPIO_PF2, PF2_DATA),
PINMUX_GPIO(GPIO_PF1, PF1_DATA),
PINMUX_GPIO(GPIO_PF0, PF0_DATA),
PINMUX_GPIO(PF30),
PINMUX_GPIO(PF29),
PINMUX_GPIO(PF28),
PINMUX_GPIO(PF27),
PINMUX_GPIO(PF26),
PINMUX_GPIO(PF25),
PINMUX_GPIO(PF24),
PINMUX_GPIO(PF23),
PINMUX_GPIO(PF22),
PINMUX_GPIO(PF21),
PINMUX_GPIO(PF20),
PINMUX_GPIO(PF19),
PINMUX_GPIO(PF18),
PINMUX_GPIO(PF17),
PINMUX_GPIO(PF16),
PINMUX_GPIO(PF15),
PINMUX_GPIO(PF14),
PINMUX_GPIO(PF13),
PINMUX_GPIO(PF12),
PINMUX_GPIO(PF11),
PINMUX_GPIO(PF10),
PINMUX_GPIO(PF9),
PINMUX_GPIO(PF8),
PINMUX_GPIO(PF7),
PINMUX_GPIO(PF6),
PINMUX_GPIO(PF5),
PINMUX_GPIO(PF4),
PINMUX_GPIO(PF3),
PINMUX_GPIO(PF2),
PINMUX_GPIO(PF1),
PINMUX_GPIO(PF0),
};
#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
......
drivers/pinctrl/sh-pfc/pfc-sh7264.c
View file @ da52faa5
......@@ -604,8 +604,7 @@ enum {
PINMUX_MARK_END,
};
static const pinmux_enum_t pinmux_data[] = {
static const u16 pinmux_data[] = {
/* Port A */
PINMUX_DATA(PA3_DATA, PA3_IN),
PINMUX_DATA(PA2_DATA, PA2_IN),
......@@ -1073,149 +1072,148 @@ static const pinmux_enum_t pinmux_data[] = {
};
static struct sh_pfc_pin pinmux_pins[] = {
/* Port A */
PINMUX_GPIO(GPIO_PA3, PA3_DATA),
PINMUX_GPIO(GPIO_PA2, PA2_DATA),
PINMUX_GPIO(GPIO_PA1, PA1_DATA),
PINMUX_GPIO(GPIO_PA0, PA0_DATA),
PINMUX_GPIO(PA3),
PINMUX_GPIO(PA2),
PINMUX_GPIO(PA1),
PINMUX_GPIO(PA0),
/* Port B */
PINMUX_GPIO(GPIO_PB22, PB22_DATA),
PINMUX_GPIO(GPIO_PB21, PB21_DATA),
PINMUX_GPIO(GPIO_PB20, PB20_DATA),
PINMUX_GPIO(GPIO_PB19, PB19_DATA),
PINMUX_GPIO(GPIO_PB18, PB18_DATA),
PINMUX_GPIO(GPIO_PB17, PB17_DATA),
PINMUX_GPIO(GPIO_PB16, PB16_DATA),
PINMUX_GPIO(GPIO_PB15, PB15_DATA),
PINMUX_GPIO(GPIO_PB14, PB14_DATA),
PINMUX_GPIO(GPIO_PB13, PB13_DATA),
PINMUX_GPIO(GPIO_PB12, PB12_DATA),
PINMUX_GPIO(GPIO_PB11, PB11_DATA),
PINMUX_GPIO(GPIO_PB10, PB10_DATA),
PINMUX_GPIO(GPIO_PB9, PB9_DATA),
PINMUX_GPIO(GPIO_PB8, PB8_DATA),
PINMUX_GPIO(GPIO_PB7, PB7_DATA),
PINMUX_GPIO(GPIO_PB6, PB6_DATA),
PINMUX_GPIO(GPIO_PB5, PB5_DATA),
PINMUX_GPIO(GPIO_PB4, PB4_DATA),
PINMUX_GPIO(GPIO_PB3, PB3_DATA),
PINMUX_GPIO(GPIO_PB2, PB2_DATA),
PINMUX_GPIO(GPIO_PB1, PB1_DATA),
PINMUX_GPIO(PB22),
PINMUX_GPIO(PB21),
PINMUX_GPIO(PB20),
PINMUX_GPIO(PB19),
PINMUX_GPIO(PB18),
PINMUX_GPIO(PB17),
PINMUX_GPIO(PB16),
PINMUX_GPIO(PB15),
PINMUX_GPIO(PB14),
PINMUX_GPIO(PB13),
PINMUX_GPIO(PB12),
PINMUX_GPIO(PB11),
PINMUX_GPIO(PB10),
PINMUX_GPIO(PB9),
PINMUX_GPIO(PB8),
PINMUX_GPIO(PB7),
PINMUX_GPIO(PB6),
PINMUX_GPIO(PB5),
PINMUX_GPIO(PB4),
PINMUX_GPIO(PB3),
PINMUX_GPIO(PB2),
PINMUX_GPIO(PB1),
/* Port C */
PINMUX_GPIO(GPIO_PC10, PC10_DATA),
PINMUX_GPIO(GPIO_PC9, PC9_DATA),
PINMUX_GPIO(GPIO_PC8, PC8_DATA),
PINMUX_GPIO(GPIO_PC7, PC7_DATA),
PINMUX_GPIO(GPIO_PC6, PC6_DATA),
PINMUX_GPIO(GPIO_PC5, PC5_DATA),
PINMUX_GPIO(GPIO_PC4, PC4_DATA),
PINMUX_GPIO(GPIO_PC3, PC3_DATA),
PINMUX_GPIO(GPIO_PC2, PC2_DATA),
PINMUX_GPIO(GPIO_PC1, PC1_DATA),
PINMUX_GPIO(GPIO_PC0, PC0_DATA),
PINMUX_GPIO(PC10),
PINMUX_GPIO(PC9),
PINMUX_GPIO(PC8),
PINMUX_GPIO(PC7),
PINMUX_GPIO(PC6),
PINMUX_GPIO(PC5),
PINMUX_GPIO(PC4),
PINMUX_GPIO(PC3),
PINMUX_GPIO(PC2),
PINMUX_GPIO(PC1),
PINMUX_GPIO(PC0),
/* Port D */
PINMUX_GPIO(GPIO_PD15, PD15_DATA),
PINMUX_GPIO(GPIO_PD14, PD14_DATA),
PINMUX_GPIO(GPIO_PD13, PD13_DATA),
PINMUX_GPIO(GPIO_PD12, PD12_DATA),
PINMUX_GPIO(GPIO_PD11, PD11_DATA),
PINMUX_GPIO(GPIO_PD10, PD10_DATA),
PINMUX_GPIO(GPIO_PD9, PD9_DATA),
PINMUX_GPIO(GPIO_PD8, PD8_DATA),
PINMUX_GPIO(GPIO_PD7, PD7_DATA),
PINMUX_GPIO(GPIO_PD6, PD6_DATA),
PINMUX_GPIO(GPIO_PD5, PD5_DATA),
PINMUX_GPIO(GPIO_PD4, PD4_DATA),
PINMUX_GPIO(GPIO_PD3, PD3_DATA),
PINMUX_GPIO(GPIO_PD2, PD2_DATA),
PINMUX_GPIO(GPIO_PD1, PD1_DATA),
PINMUX_GPIO(GPIO_PD0, PD0_DATA),
PINMUX_GPIO(PD15),
PINMUX_GPIO(PD14),
PINMUX_GPIO(PD13),
PINMUX_GPIO(PD12),
PINMUX_GPIO(PD11),
PINMUX_GPIO(PD10),
PINMUX_GPIO(PD9),
PINMUX_GPIO(PD8),
PINMUX_GPIO(PD7),
PINMUX_GPIO(PD6),
PINMUX_GPIO(PD5),
PINMUX_GPIO(PD4),
PINMUX_GPIO(PD3),
PINMUX_GPIO(PD2),
PINMUX_GPIO(PD1),
PINMUX_GPIO(PD0),
/* Port E */
PINMUX_GPIO(GPIO_PE5, PE5_DATA),
PINMUX_GPIO(GPIO_PE4, PE4_DATA),
PINMUX_GPIO(GPIO_PE3, PE3_DATA),
PINMUX_GPIO(GPIO_PE2, PE2_DATA),
PINMUX_GPIO(GPIO_PE1, PE1_DATA),
PINMUX_GPIO(GPIO_PE0, PE0_DATA),
PINMUX_GPIO(PE5),
PINMUX_GPIO(PE4),
PINMUX_GPIO(PE3),
PINMUX_GPIO(PE2),
PINMUX_GPIO(PE1),
PINMUX_GPIO(PE0),
/* Port F */
PINMUX_GPIO(GPIO_PF12, PF12_DATA),
PINMUX_GPIO(GPIO_PF11, PF11_DATA),
PINMUX_GPIO(GPIO_PF10, PF10_DATA),
PINMUX_GPIO(GPIO_PF9, PF9_DATA),
PINMUX_GPIO(GPIO_PF8, PF8_DATA),
PINMUX_GPIO(GPIO_PF7, PF7_DATA),
PINMUX_GPIO(GPIO_PF6, PF6_DATA),
PINMUX_GPIO(GPIO_PF5, PF5_DATA),
PINMUX_GPIO(GPIO_PF4, PF4_DATA),
PINMUX_GPIO(GPIO_PF3, PF3_DATA),
PINMUX_GPIO(GPIO_PF2, PF2_DATA),
PINMUX_GPIO(GPIO_PF1, PF1_DATA),
PINMUX_GPIO(GPIO_PF0, PF0_DATA),
PINMUX_GPIO(PF12),
PINMUX_GPIO(PF11),
PINMUX_GPIO(PF10),
PINMUX_GPIO(PF9),
PINMUX_GPIO(PF8),
PINMUX_GPIO(PF7),
PINMUX_GPIO(PF6),
PINMUX_GPIO(PF5),
PINMUX_GPIO(PF4),
PINMUX_GPIO(PF3),
PINMUX_GPIO(PF2),
PINMUX_GPIO(PF1),
PINMUX_GPIO(PF0),
/* Port G */
PINMUX_GPIO(GPIO_PG24, PG24_DATA),
PINMUX_GPIO(GPIO_PG23, PG23_DATA),
PINMUX_GPIO(GPIO_PG22, PG22_DATA),
PINMUX_GPIO(GPIO_PG21, PG21_DATA),
PINMUX_GPIO(GPIO_PG20, PG20_DATA),
PINMUX_GPIO(GPIO_PG19, PG19_DATA),
PINMUX_GPIO(GPIO_PG18, PG18_DATA),
PINMUX_GPIO(GPIO_PG17, PG17_DATA),
PINMUX_GPIO(GPIO_PG16, PG16_DATA),
PINMUX_GPIO(GPIO_PG15, PG15_DATA),
PINMUX_GPIO(GPIO_PG14, PG14_DATA),
PINMUX_GPIO(GPIO_PG13, PG13_DATA),
PINMUX_GPIO(GPIO_PG12, PG12_DATA),
PINMUX_GPIO(GPIO_PG11, PG11_DATA),
PINMUX_GPIO(GPIO_PG10, PG10_DATA),
PINMUX_GPIO(GPIO_PG9, PG9_DATA),
PINMUX_GPIO(GPIO_PG8, PG8_DATA),
PINMUX_GPIO(GPIO_PG7, PG7_DATA),
PINMUX_GPIO(GPIO_PG6, PG6_DATA),
PINMUX_GPIO(GPIO_PG5, PG5_DATA),
PINMUX_GPIO(GPIO_PG4, PG4_DATA),
PINMUX_GPIO(GPIO_PG3, PG3_DATA),
PINMUX_GPIO(GPIO_PG2, PG2_DATA),
PINMUX_GPIO(GPIO_PG1, PG1_DATA),
PINMUX_GPIO(GPIO_PG0, PG0_DATA),
PINMUX_GPIO(PG24),
PINMUX_GPIO(PG23),
PINMUX_GPIO(PG22),
PINMUX_GPIO(PG21),
PINMUX_GPIO(PG20),
PINMUX_GPIO(PG19),
PINMUX_GPIO(PG18),
PINMUX_GPIO(PG17),
PINMUX_GPIO(PG16),
PINMUX_GPIO(PG15),
PINMUX_GPIO(PG14),
PINMUX_GPIO(PG13),
PINMUX_GPIO(PG12),
PINMUX_GPIO(PG11),
PINMUX_GPIO(PG10),
PINMUX_GPIO(PG9),
PINMUX_GPIO(PG8),
PINMUX_GPIO(PG7),
PINMUX_GPIO(PG6),
PINMUX_GPIO(PG5),
PINMUX_GPIO(PG4),
PINMUX_GPIO(PG3),
PINMUX_GPIO(PG2),
PINMUX_GPIO(PG1),
PINMUX_GPIO(PG0),
/* Port H - Port H does not have a Data Register */
/* Port I - not on device */
/* Port J */
PINMUX_GPIO(GPIO_PJ11, PJ11_DATA),
PINMUX_GPIO(GPIO_PJ10, PJ10_DATA),
PINMUX_GPIO(GPIO_PJ9, PJ9_DATA),
PINMUX_GPIO(GPIO_PJ8, PJ8_DATA),
PINMUX_GPIO(GPIO_PJ7, PJ7_DATA),
PINMUX_GPIO(GPIO_PJ6, PJ6_DATA),
PINMUX_GPIO(GPIO_PJ5, PJ5_DATA),
PINMUX_GPIO(GPIO_PJ4, PJ4_DATA),
PINMUX_GPIO(GPIO_PJ3, PJ3_DATA),
PINMUX_GPIO(GPIO_PJ2, PJ2_DATA),
PINMUX_GPIO(GPIO_PJ1, PJ1_DATA),
PINMUX_GPIO(GPIO_PJ0, PJ0_DATA),
PINMUX_GPIO(PJ11),
PINMUX_GPIO(PJ10),
PINMUX_GPIO(PJ9),
PINMUX_GPIO(PJ8),
PINMUX_GPIO(PJ7),
PINMUX_GPIO(PJ6),
PINMUX_GPIO(PJ5),
PINMUX_GPIO(PJ4),
PINMUX_GPIO(PJ3),
PINMUX_GPIO(PJ2),
PINMUX_GPIO(PJ1),
PINMUX_GPIO(PJ0),
/* Port K */
PINMUX_GPIO(GPIO_PK11, PK11_DATA),
PINMUX_GPIO(GPIO_PK10, PK10_DATA),
PINMUX_GPIO(GPIO_PK9, PK9_DATA),
PINMUX_GPIO(GPIO_PK8, PK8_DATA),
PINMUX_GPIO(GPIO_PK7, PK7_DATA),
PINMUX_GPIO(GPIO_PK6, PK6_DATA),
PINMUX_GPIO(GPIO_PK5, PK5_DATA),
PINMUX_GPIO(GPIO_PK4, PK4_DATA),
PINMUX_GPIO(GPIO_PK3, PK3_DATA),
PINMUX_GPIO(GPIO_PK2, PK2_DATA),
PINMUX_GPIO(GPIO_PK1, PK1_DATA),
PINMUX_GPIO(GPIO_PK0, PK0_DATA),
PINMUX_GPIO(PK11),
PINMUX_GPIO(PK10),
PINMUX_GPIO(PK9),
PINMUX_GPIO(PK8),
PINMUX_GPIO(PK7),
PINMUX_GPIO(PK6),
PINMUX_GPIO(PK5),
PINMUX_GPIO(PK4),
PINMUX_GPIO(PK3),
PINMUX_GPIO(PK2),
PINMUX_GPIO(PK1),
PINMUX_GPIO(PK0),
};
#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
......
drivers/pinctrl/sh-pfc/pfc-sh7269.c
View file @ da52faa5
......@@ -781,8 +781,7 @@ enum {
PINMUX_MARK_END,
};
static const pinmux_enum_t pinmux_data[] = {
static const u16 pinmux_data[] = {
/* Port A */
PINMUX_DATA(PA1_DATA, PA1_IN),
PINMUX_DATA(PA0_DATA, PA0_IN),
......@@ -1454,165 +1453,165 @@ static const pinmux_enum_t pinmux_data[] = {
static struct sh_pfc_pin pinmux_pins[] = {
/* Port A */
PINMUX_GPIO(GPIO_PA1, PA1_DATA),
PINMUX_GPIO(GPIO_PA0, PA0_DATA),
PINMUX_GPIO(PA1),
PINMUX_GPIO(PA0),
/* Port B */
PINMUX_GPIO(GPIO_PB22, PB22_DATA),
PINMUX_GPIO(GPIO_PB21, PB21_DATA),
PINMUX_GPIO(GPIO_PB20, PB20_DATA),
PINMUX_GPIO(GPIO_PB19, PB19_DATA),
PINMUX_GPIO(GPIO_PB18, PB18_DATA),
PINMUX_GPIO(GPIO_PB17, PB17_DATA),
PINMUX_GPIO(GPIO_PB16, PB16_DATA),
PINMUX_GPIO(GPIO_PB15, PB15_DATA),
PINMUX_GPIO(GPIO_PB14, PB14_DATA),
PINMUX_GPIO(GPIO_PB13, PB13_DATA),
PINMUX_GPIO(GPIO_PB12, PB12_DATA),
PINMUX_GPIO(GPIO_PB11, PB11_DATA),
PINMUX_GPIO(GPIO_PB10, PB10_DATA),
PINMUX_GPIO(GPIO_PB9, PB9_DATA),
PINMUX_GPIO(GPIO_PB8, PB8_DATA),
PINMUX_GPIO(GPIO_PB7, PB7_DATA),
PINMUX_GPIO(GPIO_PB6, PB6_DATA),
PINMUX_GPIO(GPIO_PB5, PB5_DATA),
PINMUX_GPIO(GPIO_PB4, PB4_DATA),
PINMUX_GPIO(GPIO_PB3, PB3_DATA),
PINMUX_GPIO(GPIO_PB2, PB2_DATA),
PINMUX_GPIO(GPIO_PB1, PB1_DATA),
PINMUX_GPIO(PB22),
PINMUX_GPIO(PB21),
PINMUX_GPIO(PB20),
PINMUX_GPIO(PB19),
PINMUX_GPIO(PB18),
PINMUX_GPIO(PB17),
PINMUX_GPIO(PB16),
PINMUX_GPIO(PB15),
PINMUX_GPIO(PB14),
PINMUX_GPIO(PB13),
PINMUX_GPIO(PB12),
PINMUX_GPIO(PB11),
PINMUX_GPIO(PB10),
PINMUX_GPIO(PB9),
PINMUX_GPIO(PB8),
PINMUX_GPIO(PB7),
PINMUX_GPIO(PB6),
PINMUX_GPIO(PB5),
PINMUX_GPIO(PB4),
PINMUX_GPIO(PB3),
PINMUX_GPIO(PB2),
PINMUX_GPIO(PB1),
/* Port C */
PINMUX_GPIO(GPIO_PC8, PC8_DATA),
PINMUX_GPIO(GPIO_PC7, PC7_DATA),
PINMUX_GPIO(GPIO_PC6, PC6_DATA),
PINMUX_GPIO(GPIO_PC5, PC5_DATA),
PINMUX_GPIO(GPIO_PC4, PC4_DATA),
PINMUX_GPIO(GPIO_PC3, PC3_DATA),
PINMUX_GPIO(GPIO_PC2, PC2_DATA),
PINMUX_GPIO(GPIO_PC1, PC1_DATA),
PINMUX_GPIO(GPIO_PC0, PC0_DATA),
PINMUX_GPIO(PC8),
PINMUX_GPIO(PC7),
PINMUX_GPIO(PC6),
PINMUX_GPIO(PC5),
PINMUX_GPIO(PC4),
PINMUX_GPIO(PC3),
PINMUX_GPIO(PC2),
PINMUX_GPIO(PC1),
PINMUX_GPIO(PC0),
/* Port D */
PINMUX_GPIO(GPIO_PD15, PD15_DATA),
PINMUX_GPIO(GPIO_PD14, PD14_DATA),
PINMUX_GPIO(GPIO_PD13, PD13_DATA),
PINMUX_GPIO(GPIO_PD12, PD12_DATA),
PINMUX_GPIO(GPIO_PD11, PD11_DATA),
PINMUX_GPIO(GPIO_PD10, PD10_DATA),
PINMUX_GPIO(GPIO_PD9, PD9_DATA),
PINMUX_GPIO(GPIO_PD8, PD8_DATA),
PINMUX_GPIO(GPIO_PD7, PD7_DATA),
PINMUX_GPIO(GPIO_PD6, PD6_DATA),
PINMUX_GPIO(GPIO_PD5, PD5_DATA),
PINMUX_GPIO(GPIO_PD4, PD4_DATA),
PINMUX_GPIO(GPIO_PD3, PD3_DATA),
PINMUX_GPIO(GPIO_PD2, PD2_DATA),
PINMUX_GPIO(GPIO_PD1, PD1_DATA),
PINMUX_GPIO(GPIO_PD0, PD0_DATA),
PINMUX_GPIO(PD15),
PINMUX_GPIO(PD14),
PINMUX_GPIO(PD13),
PINMUX_GPIO(PD12),
PINMUX_GPIO(PD11),
PINMUX_GPIO(PD10),
PINMUX_GPIO(PD9),
PINMUX_GPIO(PD8),
PINMUX_GPIO(PD7),
PINMUX_GPIO(PD6),
PINMUX_GPIO(PD5),
PINMUX_GPIO(PD4),
PINMUX_GPIO(PD3),
PINMUX_GPIO(PD2),
PINMUX_GPIO(PD1),
PINMUX_GPIO(PD0),
/* Port E */
PINMUX_GPIO(GPIO_PE7, PE7_DATA),
PINMUX_GPIO(GPIO_PE6, PE6_DATA),
PINMUX_GPIO(GPIO_PE5, PE5_DATA),
PINMUX_GPIO(GPIO_PE4, PE4_DATA),
PINMUX_GPIO(GPIO_PE3, PE3_DATA),
PINMUX_GPIO(GPIO_PE2, PE2_DATA),
PINMUX_GPIO(GPIO_PE1, PE1_DATA),
PINMUX_GPIO(GPIO_PE0, PE0_DATA),
PINMUX_GPIO(PE7),
PINMUX_GPIO(PE6),
PINMUX_GPIO(PE5),
PINMUX_GPIO(PE4),
PINMUX_GPIO(PE3),
PINMUX_GPIO(PE2),
PINMUX_GPIO(PE1),
PINMUX_GPIO(PE0),
/* Port F */
PINMUX_GPIO(GPIO_PF23, PF23_DATA),
PINMUX_GPIO(GPIO_PF22, PF22_DATA),
PINMUX_GPIO(GPIO_PF21, PF21_DATA),
PINMUX_GPIO(GPIO_PF20, PF20_DATA),
PINMUX_GPIO(GPIO_PF19, PF19_DATA),
PINMUX_GPIO(GPIO_PF18, PF18_DATA),
PINMUX_GPIO(GPIO_PF17, PF17_DATA),
PINMUX_GPIO(GPIO_PF16, PF16_DATA),
PINMUX_GPIO(GPIO_PF15, PF15_DATA),
PINMUX_GPIO(GPIO_PF14, PF14_DATA),
PINMUX_GPIO(GPIO_PF13, PF13_DATA),
PINMUX_GPIO(GPIO_PF12, PF12_DATA),
PINMUX_GPIO(GPIO_PF11, PF11_DATA),
PINMUX_GPIO(GPIO_PF10, PF10_DATA),
PINMUX_GPIO(GPIO_PF9, PF9_DATA),
PINMUX_GPIO(GPIO_PF8, PF8_DATA),
PINMUX_GPIO(GPIO_PF7, PF7_DATA),
PINMUX_GPIO(GPIO_PF6, PF6_DATA),
PINMUX_GPIO(GPIO_PF5, PF5_DATA),
PINMUX_GPIO(GPIO_PF4, PF4_DATA),
PINMUX_GPIO(GPIO_PF3, PF3_DATA),
PINMUX_GPIO(GPIO_PF2, PF2_DATA),
PINMUX_GPIO(GPIO_PF1, PF1_DATA),
PINMUX_GPIO(GPIO_PF0, PF0_DATA),
PINMUX_GPIO(PF23),
PINMUX_GPIO(PF22),
PINMUX_GPIO(PF21),
PINMUX_GPIO(PF20),
PINMUX_GPIO(PF19),
PINMUX_GPIO(PF18),
PINMUX_GPIO(PF17),
PINMUX_GPIO(PF16),
PINMUX_GPIO(PF15),
PINMUX_GPIO(PF14),
PINMUX_GPIO(PF13),
PINMUX_GPIO(PF12),
PINMUX_GPIO(PF11),
PINMUX_GPIO(PF10),
PINMUX_GPIO(PF9),
PINMUX_GPIO(PF8),
PINMUX_GPIO(PF7),
PINMUX_GPIO(PF6),
PINMUX_GPIO(PF5),
PINMUX_GPIO(PF4),
PINMUX_GPIO(PF3),
PINMUX_GPIO(PF2),
PINMUX_GPIO(PF1),
PINMUX_GPIO(PF0),
/* Port G */
PINMUX_GPIO(GPIO_PG27, PG27_DATA),
PINMUX_GPIO(GPIO_PG26, PG26_DATA),
PINMUX_GPIO(GPIO_PG25, PG25_DATA),
PINMUX_GPIO(GPIO_PG24, PG24_DATA),
PINMUX_GPIO(GPIO_PG23, PG23_DATA),
PINMUX_GPIO(GPIO_PG22, PG22_DATA),
PINMUX_GPIO(GPIO_PG21, PG21_DATA),
PINMUX_GPIO(GPIO_PG20, PG20_DATA),
PINMUX_GPIO(GPIO_PG19, PG19_DATA),
PINMUX_GPIO(GPIO_PG18, PG18_DATA),
PINMUX_GPIO(GPIO_PG17, PG17_DATA),
PINMUX_GPIO(GPIO_PG16, PG16_DATA),
PINMUX_GPIO(GPIO_PG15, PG15_DATA),
PINMUX_GPIO(GPIO_PG14, PG14_DATA),
PINMUX_GPIO(GPIO_PG13, PG13_DATA),
PINMUX_GPIO(GPIO_PG12, PG12_DATA),
PINMUX_GPIO(GPIO_PG11, PG11_DATA),
PINMUX_GPIO(GPIO_PG10, PG10_DATA),
PINMUX_GPIO(GPIO_PG9, PG9_DATA),
PINMUX_GPIO(GPIO_PG8, PG8_DATA),
PINMUX_GPIO(GPIO_PG7, PG7_DATA),
PINMUX_GPIO(GPIO_PG6, PG6_DATA),
PINMUX_GPIO(GPIO_PG5, PG5_DATA),
PINMUX_GPIO(GPIO_PG4, PG4_DATA),
PINMUX_GPIO(GPIO_PG3, PG3_DATA),
PINMUX_GPIO(GPIO_PG2, PG2_DATA),
PINMUX_GPIO(GPIO_PG1, PG1_DATA),
PINMUX_GPIO(GPIO_PG0, PG0_DATA),
PINMUX_GPIO(PG27),
PINMUX_GPIO(PG26),
PINMUX_GPIO(PG25),
PINMUX_GPIO(PG24),
PINMUX_GPIO(PG23),
PINMUX_GPIO(PG22),
PINMUX_GPIO(PG21),
PINMUX_GPIO(PG20),
PINMUX_GPIO(PG19),
PINMUX_GPIO(PG18),
PINMUX_GPIO(PG17),
PINMUX_GPIO(PG16),
PINMUX_GPIO(PG15),
PINMUX_GPIO(PG14),
PINMUX_GPIO(PG13),
PINMUX_GPIO(PG12),
PINMUX_GPIO(PG11),
PINMUX_GPIO(PG10),
PINMUX_GPIO(PG9),
PINMUX_GPIO(PG8),
PINMUX_GPIO(PG7),
PINMUX_GPIO(PG6),
PINMUX_GPIO(PG5),
PINMUX_GPIO(PG4),
PINMUX_GPIO(PG3),
PINMUX_GPIO(PG2),
PINMUX_GPIO(PG1),
PINMUX_GPIO(PG0),
/* Port H - Port H does not have a Data Register */
/* Port I - not on device */
/* Port J */
PINMUX_GPIO(GPIO_PJ31, PJ31_DATA),
PINMUX_GPIO(GPIO_PJ30, PJ30_DATA),
PINMUX_GPIO(GPIO_PJ29, PJ29_DATA),
PINMUX_GPIO(GPIO_PJ28, PJ28_DATA),
PINMUX_GPIO(GPIO_PJ27, PJ27_DATA),
PINMUX_GPIO(GPIO_PJ26, PJ26_DATA),
PINMUX_GPIO(GPIO_PJ25, PJ25_DATA),
PINMUX_GPIO(GPIO_PJ24, PJ24_DATA),
PINMUX_GPIO(GPIO_PJ23, PJ23_DATA),
PINMUX_GPIO(GPIO_PJ22, PJ22_DATA),
PINMUX_GPIO(GPIO_PJ21, PJ21_DATA),
PINMUX_GPIO(GPIO_PJ20, PJ20_DATA),
PINMUX_GPIO(GPIO_PJ19, PJ19_DATA),
PINMUX_GPIO(GPIO_PJ18, PJ18_DATA),
PINMUX_GPIO(GPIO_PJ17, PJ17_DATA),
PINMUX_GPIO(GPIO_PJ16, PJ16_DATA),
PINMUX_GPIO(GPIO_PJ15, PJ15_DATA),
PINMUX_GPIO(GPIO_PJ14, PJ14_DATA),
PINMUX_GPIO(GPIO_PJ13, PJ13_DATA),
PINMUX_GPIO(GPIO_PJ12, PJ12_DATA),
PINMUX_GPIO(GPIO_PJ11, PJ11_DATA),
PINMUX_GPIO(GPIO_PJ10, PJ10_DATA),
PINMUX_GPIO(GPIO_PJ9, PJ9_DATA),
PINMUX_GPIO(GPIO_PJ8, PJ8_DATA),
PINMUX_GPIO(GPIO_PJ7, PJ7_DATA),
PINMUX_GPIO(GPIO_PJ6, PJ6_DATA),
PINMUX_GPIO(GPIO_PJ5, PJ5_DATA),
PINMUX_GPIO(GPIO_PJ4, PJ4_DATA),
PINMUX_GPIO(GPIO_PJ3, PJ3_DATA),
PINMUX_GPIO(GPIO_PJ2, PJ2_DATA),
PINMUX_GPIO(GPIO_PJ1, PJ1_DATA),
PINMUX_GPIO(GPIO_PJ0, PJ0_DATA),
PINMUX_GPIO(PJ31),
PINMUX_GPIO(PJ30),
PINMUX_GPIO(PJ29),
PINMUX_GPIO(PJ28),
PINMUX_GPIO(PJ27),
PINMUX_GPIO(PJ26),
PINMUX_GPIO(PJ25),
PINMUX_GPIO(PJ24),
PINMUX_GPIO(PJ23),
PINMUX_GPIO(PJ22),
PINMUX_GPIO(PJ21),
PINMUX_GPIO(PJ20),
PINMUX_GPIO(PJ19),
PINMUX_GPIO(PJ18),
PINMUX_GPIO(PJ17),
PINMUX_GPIO(PJ16),
PINMUX_GPIO(PJ15),
PINMUX_GPIO(PJ14),
PINMUX_GPIO(PJ13),
PINMUX_GPIO(PJ12),
PINMUX_GPIO(PJ11),
PINMUX_GPIO(PJ10),
PINMUX_GPIO(PJ9),
PINMUX_GPIO(PJ8),
PINMUX_GPIO(PJ7),
PINMUX_GPIO(PJ6),
PINMUX_GPIO(PJ5),
PINMUX_GPIO(PJ4),
PINMUX_GPIO(PJ3),
PINMUX_GPIO(PJ2),
PINMUX_GPIO(PJ1),
PINMUX_GPIO(PJ0),
};
#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
......
drivers/pinctrl/sh-pfc/pfc-sh7372.c
View file @ da52faa5
......@@ -30,20 +30,13 @@
#include "core.h"
#include "sh_pfc.h"
#define CPU_ALL_PORT(fn, pfx, sfx) \
PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \
PORT_10(fn, pfx##10, sfx), PORT_10(fn, pfx##11, sfx), \
PORT_10(fn, pfx##12, sfx), PORT_10(fn, pfx##13, sfx), \
PORT_10(fn, pfx##14, sfx), PORT_10(fn, pfx##15, sfx), \
PORT_10(fn, pfx##16, sfx), PORT_10(fn, pfx##17, sfx), \
PORT_10(fn, pfx##18, sfx), PORT_1(fn, pfx##190, sfx)
#undef _GPIO_PORT
#define _GPIO_PORT(gpio, sfx) \
[gpio] = { \
.name = __stringify(PORT##gpio), \
.enum_id = PORT##gpio##_DATA, \
}
#define CPU_ALL_PORT(fn, pfx, sfx) \
PORT_10(0, fn, pfx, sfx), PORT_90(0, fn, pfx, sfx), \
PORT_10(100, fn, pfx##10, sfx), PORT_10(110, fn, pfx##11, sfx), \
PORT_10(120, fn, pfx##12, sfx), PORT_10(130, fn, pfx##13, sfx), \
PORT_10(140, fn, pfx##14, sfx), PORT_10(150, fn, pfx##15, sfx), \
PORT_10(160, fn, pfx##16, sfx), PORT_10(170, fn, pfx##17, sfx), \
PORT_10(180, fn, pfx##18, sfx), PORT_1(190, fn, pfx##190, sfx)
#define IRQC_PIN_MUX(irq, pin) \
static const unsigned int intc_irq##irq##_pins[] = { \
......@@ -391,11 +384,8 @@ enum {
PINMUX_MARK_END,
};
#define _PORT_DATA(pfx, sfx) PORT_DATA_IO(pfx)
#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
static const pinmux_enum_t pinmux_data[] = {
PINMUX_DATA_GP_ALL(),
static const u16 pinmux_data[] = {
PINMUX_DATA_ALL(),
/* IRQ */
PINMUX_DATA(IRQ0_6_MARK, PORT6_FN0, MSEL1CR_0_0),
......@@ -839,13 +829,6 @@ static const pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(MFIv4_MARK, MSEL4CR_6_1),
};
#define SH7372_PIN(pin, cfgs) \
{ \
.name = __stringify(PORT##pin), \
.enum_id = PORT##pin##_DATA, \
.configs = cfgs, \
}
#define __I (SH_PFC_PIN_CFG_INPUT)
#define __O (SH_PFC_PIN_CFG_OUTPUT)
#define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
......@@ -853,15 +836,15 @@ static const pinmux_enum_t pinmux_data[] = {
#define __PU (SH_PFC_PIN_CFG_PULL_UP)
#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
#define SH7372_PIN_I_PD(pin) SH7372_PIN(pin, __I | __PD)
#define SH7372_PIN_I_PU(pin) SH7372_PIN(pin, __I | __PU)
#define SH7372_PIN_I_PU_PD(pin) SH7372_PIN(pin, __I | __PUD)
#define SH7372_PIN_IO(pin) SH7372_PIN(pin, __IO)
#define SH7372_PIN_IO_PD(pin) SH7372_PIN(pin, __IO | __PD)
#define SH7372_PIN_IO_PU(pin) SH7372_PIN(pin, __IO | __PU)
#define SH7372_PIN_IO_PU_PD(pin) SH7372_PIN(pin, __IO | __PUD)
#define SH7372_PIN_O(pin) SH7372_PIN(pin, __O)
#define SH7372_PIN_O_PU_PD(pin) SH7372_PIN(pin, __O | __PUD)
#define SH7372_PIN_I_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PD)
#define SH7372_PIN_I_PU(pin) SH_PFC_PIN_CFG(pin, __I | __PU)
#define SH7372_PIN_I_PU_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PUD)
#define SH7372_PIN_IO(pin) SH_PFC_PIN_CFG(pin, __IO)
#define SH7372_PIN_IO_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PD)
#define SH7372_PIN_IO_PU(pin) SH_PFC_PIN_CFG(pin, __IO | __PU)
#define SH7372_PIN_IO_PU_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PUD)
#define SH7372_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O)
#define SH7372_PIN_O_PU_PD(pin) SH_PFC_PIN_CFG(pin, __O | __PUD)
static struct sh_pfc_pin pinmux_pins[] = {
/* Table 57-1 (I/O and Pull U/D) */
......
drivers/pinctrl/sh-pfc/pfc-sh73a0.c
View file @ da52faa5
......@@ -31,32 +31,32 @@
#include "core.h"
#include "sh_pfc.h"
#define CPU_ALL_PORT(fn, pfx, sfx) \
PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \
PORT_10(fn, pfx##10, sfx), \
PORT_1(fn, pfx##110, sfx), PORT_1(fn, pfx##111, sfx), \
PORT_1(fn, pfx##112, sfx), PORT_1(fn, pfx##113, sfx), \
PORT_1(fn, pfx##114, sfx), PORT_1(fn, pfx##115, sfx), \
PORT_1(fn, pfx##116, sfx), PORT_1(fn, pfx##117, sfx), \
PORT_1(fn, pfx##118, sfx), \
PORT_1(fn, pfx##128, sfx), PORT_1(fn, pfx##129, sfx), \
PORT_10(fn, pfx##13, sfx), PORT_10(fn, pfx##14, sfx), \
PORT_10(fn, pfx##15, sfx), \
PORT_1(fn, pfx##160, sfx), PORT_1(fn, pfx##161, sfx), \
PORT_1(fn, pfx##162, sfx), PORT_1(fn, pfx##163, sfx), \
PORT_1(fn, pfx##164, sfx), \
PORT_1(fn, pfx##192, sfx), PORT_1(fn, pfx##193, sfx), \
PORT_1(fn, pfx##194, sfx), PORT_1(fn, pfx##195, sfx), \
PORT_1(fn, pfx##196, sfx), PORT_1(fn, pfx##197, sfx), \
PORT_1(fn, pfx##198, sfx), PORT_1(fn, pfx##199, sfx), \
PORT_10(fn, pfx##20, sfx), PORT_10(fn, pfx##21, sfx), \
PORT_10(fn, pfx##22, sfx), PORT_10(fn, pfx##23, sfx), \
PORT_10(fn, pfx##24, sfx), PORT_10(fn, pfx##25, sfx), \
PORT_10(fn, pfx##26, sfx), PORT_10(fn, pfx##27, sfx), \
PORT_1(fn, pfx##280, sfx), PORT_1(fn, pfx##281, sfx), \
PORT_1(fn, pfx##282, sfx), \
PORT_1(fn, pfx##288, sfx), PORT_1(fn, pfx##289, sfx), \
PORT_10(fn, pfx##29, sfx), PORT_10(fn, pfx##30, sfx)
#define CPU_ALL_PORT(fn, pfx, sfx) \
PORT_10(0, fn, pfx, sfx), PORT_90(0, fn, pfx, sfx), \
PORT_10(100, fn, pfx##10, sfx), \
PORT_1(110, fn, pfx##110, sfx), PORT_1(111, fn, pfx##111, sfx), \
PORT_1(112, fn, pfx##112, sfx), PORT_1(113, fn, pfx##113, sfx), \
PORT_1(114, fn, pfx##114, sfx), PORT_1(115, fn, pfx##115, sfx), \
PORT_1(116, fn, pfx##116, sfx), PORT_1(117, fn, pfx##117, sfx), \
PORT_1(118, fn, pfx##118, sfx), \
PORT_1(128, fn, pfx##128, sfx), PORT_1(129, fn, pfx##129, sfx), \
PORT_10(130, fn, pfx##13, sfx), PORT_10(140, fn, pfx##14, sfx), \
PORT_10(150, fn, pfx##15, sfx), \
PORT_1(160, fn, pfx##160, sfx), PORT_1(161, fn, pfx##161, sfx), \
PORT_1(162, fn, pfx##162, sfx), PORT_1(163, fn, pfx##163, sfx), \
PORT_1(164, fn, pfx##164, sfx), \
PORT_1(192, fn, pfx##192, sfx), PORT_1(193, fn, pfx##193, sfx), \
PORT_1(194, fn, pfx##194, sfx), PORT_1(195, fn, pfx##195, sfx), \
PORT_1(196, fn, pfx##196, sfx), PORT_1(197, fn, pfx##197, sfx), \
PORT_1(198, fn, pfx##198, sfx), PORT_1(199, fn, pfx##199, sfx), \
PORT_10(200, fn, pfx##20, sfx), PORT_10(210, fn, pfx##21, sfx), \
PORT_10(220, fn, pfx##22, sfx), PORT_10(230, fn, pfx##23, sfx), \
PORT_10(240, fn, pfx##24, sfx), PORT_10(250, fn, pfx##25, sfx), \
PORT_10(260, fn, pfx##26, sfx), PORT_10(270, fn, pfx##27, sfx), \
PORT_1(280, fn, pfx##280, sfx), PORT_1(281, fn, pfx##281, sfx), \
PORT_1(282, fn, pfx##282, sfx), \
PORT_1(288, fn, pfx##288, sfx), PORT_1(289, fn, pfx##289, sfx), \
PORT_10(290, fn, pfx##29, sfx), PORT_10(300, fn, pfx##30, sfx)
enum {
PINMUX_RESERVED = 0,
......@@ -466,12 +466,9 @@ enum {
PINMUX_MARK_END,
};
#define _PORT_DATA(pfx, sfx) PORT_DATA_IO(pfx)
#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
static const pinmux_enum_t pinmux_data[] = {
static const u16 pinmux_data[] = {
/* specify valid pin states for each pin in GPIO mode */
PINMUX_DATA_GP_ALL(),
PINMUX_DATA_ALL(),
/* Table 25-1 (Function 0-7) */
PINMUX_DATA(VBUS_0_MARK, PORT0_FN1),
......@@ -1160,13 +1157,6 @@ static const pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(EDBGREQ_PU_MARK, MSEL4CR_MSEL1_1),
};
#define SH73A0_PIN(pin, cfgs) \
{ \
.name = __stringify(PORT##pin), \
.enum_id = PORT##pin##_DATA, \
.configs = cfgs, \
}
#define __I (SH_PFC_PIN_CFG_INPUT)
#define __O (SH_PFC_PIN_CFG_OUTPUT)
#define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
......@@ -1174,14 +1164,20 @@ static const pinmux_enum_t pinmux_data[] = {
#define __PU (SH_PFC_PIN_CFG_PULL_UP)
#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
#define SH73A0_PIN_I_PD(pin) SH73A0_PIN(pin, __I | __PD)
#define SH73A0_PIN_I_PU(pin) SH73A0_PIN(pin, __I | __PU)
#define SH73A0_PIN_I_PU_PD(pin) SH73A0_PIN(pin, __I | __PUD)
#define SH73A0_PIN_IO(pin) SH73A0_PIN(pin, __IO)
#define SH73A0_PIN_IO_PD(pin) SH73A0_PIN(pin, __IO | __PD)
#define SH73A0_PIN_IO_PU(pin) SH73A0_PIN(pin, __IO | __PU)
#define SH73A0_PIN_IO_PU_PD(pin) SH73A0_PIN(pin, __IO | __PUD)
#define SH73A0_PIN_O(pin) SH73A0_PIN(pin, __O)
#define SH73A0_PIN_I_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PD)
#define SH73A0_PIN_I_PU(pin) SH_PFC_PIN_CFG(pin, __I | __PU)
#define SH73A0_PIN_I_PU_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PUD)
#define SH73A0_PIN_IO(pin) SH_PFC_PIN_CFG(pin, __IO)
#define SH73A0_PIN_IO_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PD)
#define SH73A0_PIN_IO_PU(pin) SH_PFC_PIN_CFG(pin, __IO | __PU)
#define SH73A0_PIN_IO_PU_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PUD)
#define SH73A0_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O)
/* Pin numbers for pins without a corresponding GPIO port number are computed
* from the row and column numbers with a 1000 offset to avoid collisions with
* GPIO port numbers.
*/
#define PIN_NUMBER(row, col) (1000+((row)-1)*34+(col)-1)
static struct sh_pfc_pin pinmux_pins[] = {
/* Table 25-1 (I/O and Pull U/D) */
......@@ -1454,21 +1450,11 @@ static struct sh_pfc_pin pinmux_pins[] = {
SH73A0_PIN_O(307),
SH73A0_PIN_I_PU(308),
SH73A0_PIN_O(309),
};
static const struct pinmux_range pinmux_ranges[] = {
{.begin = 0, .end = 118,},
{.begin = 128, .end = 164,},
{.begin = 192, .end = 282,},
{.begin = 288, .end = 309,},
/* Pins not associated with a GPIO port */
SH_PFC_PIN_NAMED(6, 26, F26),
};
/* Pin numbers for pins without a corresponding GPIO port number are computed
* from the row and column numbers with a 1000 offset to avoid collisions with
* GPIO port numbers.
*/
#define PIN_NUMBER(row, col) (1000+((row)-1)*34+(col)-1)
/* - BSC -------------------------------------------------------------------- */
static const unsigned int bsc_data_0_7_pins[] = {
/* D[0:7] */
......@@ -3904,8 +3890,6 @@ const struct sh_pfc_soc_info sh73a0_pinmux_info = {
.pins = pinmux_pins,
.nr_pins = ARRAY_SIZE(pinmux_pins),
.ranges = pinmux_ranges,
.nr_ranges = ARRAY_SIZE(pinmux_ranges),
.groups = pinmux_groups,
.nr_groups = ARRAY_SIZE(pinmux_groups),
.functions = pinmux_functions,
......
drivers/pinctrl/sh-pfc/pfc-sh7720.c
View file @ da52faa5
This diff is collapsed.
drivers/pinctrl/sh-pfc/pfc-sh7722.c
View file @ da52faa5
This diff is collapsed.
drivers/pinctrl/sh-pfc/pfc-sh7723.c
View file @ da52faa5
This diff is collapsed.
drivers/pinctrl/sh-pfc/pfc-sh7724.c
View file @ da52faa5
This diff is collapsed.
drivers/pinctrl/sh-pfc/pfc-sh7734.c
View file @ da52faa5
......@@ -14,40 +14,30 @@
#include "sh_pfc.h"
#define CPU_32_PORT5(fn, pfx, sfx) \
PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx), \
PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx), \
PORT_1(fn, pfx##4, sfx), PORT_1(fn, pfx##5, sfx), \
PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx), \
PORT_1(fn, pfx##8, sfx), PORT_1(fn, pfx##9, sfx), \
PORT_1(fn, pfx##10, sfx), PORT_1(fn, pfx##11, sfx)
/* GPSR0 - GPSR5 */
#define CPU_ALL_PORT(fn, pfx, sfx) \
PORT_32(fn, pfx##_0_, sfx), \
PORT_32(fn, pfx##_1_, sfx), \
PORT_32(fn, pfx##_2_, sfx), \
PORT_32(fn, pfx##_3_, sfx), \
PORT_32(fn, pfx##_4_, sfx), \
CPU_32_PORT5(fn, pfx##_5_, sfx)
#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA)
#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \
GP##pfx##_IN, GP##pfx##_OUT)
#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT
#define _GP_INDT(pfx, sfx) GP##pfx##_DATA
#define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str)
#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused)
#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused)
#define GP_INOUTSEL(bank) PORT_32_REV(_GP_INOUTSEL, _##bank##_, unused)
#define GP_INDT(bank) PORT_32_REV(_GP_INDT, _##bank##_, unused)
#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
FN_##ipsr, FN_##fn)
#define PORT_GP_12(bank, fn, sfx) \
PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \
PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \
PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \
PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \
PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \
PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx)
#define CPU_ALL_PORT(fn, sfx) \
PORT_GP_32(0, fn, sfx), \
PORT_GP_32(1, fn, sfx), \
PORT_GP_32(2, fn, sfx), \
PORT_GP_32(3, fn, sfx), \
PORT_GP_32(4, fn, sfx), \
PORT_GP_12(5, fn, sfx)
#undef _GP_DATA
#define _GP_DATA(bank, pin, name, sfx) \
PINMUX_DATA(name##_DATA, name##_FN, name##_IN, name##_OUT)
#define _GP_INOUTSEL(bank, pin, name, sfx) name##_IN, name##_OUT
#define _GP_INDT(bank, pin, name, sfx) name##_DATA
#define GP_INOUTSEL(bank) PORT_GP_32_REV(bank, _GP_INOUTSEL, unused)
#define GP_INDT(bank) PORT_GP_32_REV(bank, _GP_INDT, unused)
enum {
PINMUX_RESERVED = 0,
......@@ -592,7 +582,7 @@ enum {
PINMUX_MARK_END,
};
static const pinmux_enum_t pinmux_data[] = {
static const u16 pinmux_data[] = {
PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
PINMUX_DATA(CLKOUT_MARK, FN_CLKOUT),
......
drivers/pinctrl/sh-pfc/pfc-sh7757.c
View file @ da52faa5
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drivers/pinctrl/sh-pfc/pfc-sh7785.c
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drivers/pinctrl/sh-pfc/pfc-sh7786.c
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drivers/pinctrl/sh-pfc/pfc-shx3.c
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drivers/pinctrl/sh-pfc/pinctrl.c
View file @ da52faa5
......@@ -587,22 +587,9 @@ static const struct pinconf_ops sh_pfc_pinconf_ops = {
/* PFC ranges -> pinctrl pin descs */
static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
{
const struct pinmux_range *ranges;
struct pinmux_range def_range;
unsigned int nr_ranges;
unsigned int nr_pins;
unsigned int i;
if (pfc->info->ranges == NULL) {
def_range.begin = 0;
def_range.end = pfc->info->nr_pins - 1;
ranges = &def_range;
nr_ranges = 1;
} else {
ranges = pfc->info->ranges;
nr_ranges = pfc->info->nr_ranges;
}
/* Allocate and initialize the pins and configs arrays. */
pmx->pins = devm_kzalloc(pfc->dev,
sizeof(*pmx->pins) * pfc->info->nr_pins,
GFP_KERNEL);
......@@ -615,32 +602,24 @@ static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
if (unlikely(!pmx->configs))
return -ENOMEM;
for (i = 0, nr_pins = 0; i < nr_ranges; ++i) {
const struct pinmux_range *range = &ranges[i];
unsigned int number;
for (i = 0; i < pfc->info->nr_pins; ++i) {
const struct sh_pfc_pin *info = &pfc->info->pins[i];
struct sh_pfc_pin_config *cfg = &pmx->configs[i];
struct pinctrl_pin_desc *pin = &pmx->pins[i];
for (number = range->begin; number <= range->end;
number++, nr_pins++) {
struct sh_pfc_pin_config *cfg = &pmx->configs[nr_pins];
struct pinctrl_pin_desc *pin = &pmx->pins[nr_pins];
const struct sh_pfc_pin *info =
&pfc->info->pins[nr_pins];
pin->number = number;
pin->name = info->name;
cfg->type = PINMUX_TYPE_NONE;
}
/* If the pin number is equal to -1 all pins are considered */
pin->number = info->pin != (u16)-1 ? info->pin : i;
pin->name = info->name;
cfg->type = PINMUX_TYPE_NONE;
}
pfc->nr_pins = ranges[nr_ranges-1].end + 1;
return nr_ranges;
return 0;
}
int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
{
struct sh_pfc_pinctrl *pmx;
int nr_ranges;
int ret;
pmx = devm_kzalloc(pfc->dev, sizeof(*pmx), GFP_KERNEL);
if (unlikely(!pmx))
......@@ -649,9 +628,9 @@ int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
pmx->pfc = pfc;
pfc->pinctrl = pmx;
nr_ranges = sh_pfc_map_pins(pfc, pmx);
if (unlikely(nr_ranges < 0))
return nr_ranges;
ret = sh_pfc_map_pins(pfc, pmx);
if (ret < 0)
return ret;
pmx->pctl_desc.name = DRV_NAME;
pmx->pctl_desc.owner = THIS_MODULE;
......
drivers/pinctrl/sh-pfc/sh_pfc.h
View file @ da52faa5
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