Commit e0403cb9 authored by Lucas De Marchi's avatar Lucas De Marchi Committed by Rodrigo Vivi

drm/i915: follow single notation for workaround number

v2: Allow to have or omit space before platform

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171205190118.7088-1-lucas.demarchi@intel.com
parent 107783d0
...@@ -1380,7 +1380,7 @@ static bool hdmi_12bpc_possible(const struct intel_crtc_state *crtc_state) ...@@ -1380,7 +1380,7 @@ static bool hdmi_12bpc_possible(const struct intel_crtc_state *crtc_state)
} }
} }
/* Display Wa #1139 */ /* Display WA #1139 */
if (IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) && if (IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) &&
crtc_state->base.adjusted_mode.htotal > 5460) crtc_state->base.adjusted_mode.htotal > 5460)
return false; return false;
......
...@@ -58,7 +58,7 @@ static void gen9_init_clock_gating(struct drm_i915_private *dev_priv) ...@@ -58,7 +58,7 @@ static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
if (HAS_LLC(dev_priv)) { if (HAS_LLC(dev_priv)) {
/* /*
* WaCompressedResourceDisplayNewHashMode:skl,kbl * WaCompressedResourceDisplayNewHashMode:skl,kbl
* Display WA#0390: skl,kbl * Display WA #0390: skl,kbl
* *
* Must match Sampler, Pixel Back End, and Media. See * Must match Sampler, Pixel Back End, and Media. See
* WaCompressedResourceSamplerPbeMediaNewHashMode. * WaCompressedResourceSamplerPbeMediaNewHashMode.
...@@ -8417,7 +8417,7 @@ static void cnp_init_clock_gating(struct drm_i915_private *dev_priv) ...@@ -8417,7 +8417,7 @@ static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
if (!HAS_PCH_CNP(dev_priv)) if (!HAS_PCH_CNP(dev_priv))
return; return;
/* Wa #1181 */ /* Display WA #1181 */
I915_WRITE(SOUTH_DSPCLK_GATE_D, I915_READ(SOUTH_DSPCLK_GATE_D) | I915_WRITE(SOUTH_DSPCLK_GATE_D, I915_READ(SOUTH_DSPCLK_GATE_D) |
CNP_PWM_CGE_GATING_DISABLE); CNP_PWM_CGE_GATING_DISABLE);
} }
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment