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Commit e9a203a7 authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge tag 'v4.14-rockchip-dts64-2' of... 

Merge tag 'v4.14-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt64

Pull "second round of Rockchip dts64 changes for 4.14" from Heiko Stübner:

3 new boards, the rk3328-based Rock64 from the Pine64-makers, the
Sapphire som+baseboard which is another evaluation board for Rocckhip
customers and the rk3399-based som+baseboard from Austria-based
Theobroma Systems, which interestingly is in a miniITX formfactor
and provides a real PCIe x4 slot.

New nodes include on rk3399 graphics (vops, hdmi, etc) and more iommus,
on rk3328 iommus, pwm, thermal management, and sound as well as operating
points and rk3368 got iommu nodes and cpu operating points.

On existing boards firefly got operating points, the rk3328-evb got its
pmic and gru boards got some sound-related fixes.

* tag 'v4.14-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (29 commits)
  arm64: dts: rockchip: add Haikou baseboard with RK3399-Q7 SoM
  arm64: dts: rockchip: add RK3399-Q7 (Puma) SoM
  dt-bindings: add rk3399-q7 SoM
  arm64: dts: rockchip: add rk3328-rock64 board
  arm64: dts: rockchip: add rk3328 pdm node
  arm64: dts: rockchip: add more rk3399 iommu nodes
  arm64: dts: rockchip: add rk3368 iommu nodes
  arm64: dts: rockchip: add rk3328 iommu nodes
  arm64: dts: rockchip: Add basic cpu frequencies for RK3368
  arm64: dts: rockchip: add rk805 node for rk3328-evb
  arm64: dts: rockchip: Assign mic irq to correct device for Gru
  arm64: dts: rockchip: init rk3399 vop clock rates
  arm64: dts: rockchip: Add pwm nodes for rk3328
  arm64: dts: rockchip: Fix wrong rt5514 dmic delay property for Gru
  arm64: dts: rockchip: disable tx ipgap linecheck for rk3399 dwc3
  arm64: dts: rockchip: remove num-slots property from rk3399-sapphire
  arm64: dts: rockchip: Enable tsadc module on RK3328 eavluation board
  arm64: dts: rockchip: add thermal nodes for rk3328 SoC
  arm64: dts: rockchip: add tsadc node for rk3328 SoC
  arm64: dts: rockchip: add rk3328 i2s nodes
  ...
parents 298f2a3a 60fd9f72
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Documentation/devicetree/bindings/arm/rockchip.txt
View file @ e9a203a7
......@@ -134,6 +134,10 @@ Rockchip platforms device tree bindings
Required root node properties:
- compatible = "phytec,rk3288-pcm-947", "phytec,rk3288-phycore-som", "rockchip,rk3288";
- Pine64 Rock64 board:
Required root node properties:
- compatible = "pine64,rock64", "rockchip,rk3328";
- Rockchip PX3 Evaluation board:
Required root node properties:
- compatible = "rockchip,px3-evb", "rockchip,px3", "rockchip,rk3188";
......@@ -173,6 +177,14 @@ Rockchip platforms device tree bindings
Required root node properties:
- compatible = "rockchip,rk3399-evb", "rockchip,rk3399";
- Rockchip RK3399 Sapphire Excavator board:
Required root node properties:
- compatible = "rockchip,rk3399-sapphire-excavator", "rockchip,rk3399";
- Theobroma Systems RK3399-Q7 Haikou Baseboard:
Required root node properties:
- compatible = "tsd,rk3399-q7-haikou", "rockchip,rk3399";
- Tronsmart Orion R68 Meta
Required root node properties:
- compatible = "tronsmart,orion-r68-meta", "rockchip,rk3368";
arch/arm64/boot/dts/rockchip/Makefile
View file @ e9a203a7
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-geekbox.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-orion-r68-meta.dtb
......@@ -7,6 +8,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-firefly.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-kevin.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)
......
arch/arm64/boot/dts/rockchip/rk3328-evb.dts
View file @ e9a203a7
......@@ -50,6 +50,146 @@ / {
chosen {
stdout-path = "serial2:1500000n8";
};
dc_12v: dc-12v {
compatible = "regulator-fixed";
regulator-name = "dc_12v";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
vcc_sys: vcc-sys {
compatible = "regulator-fixed";
regulator-name = "vcc_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
vin-supply = <&dc_12v>;
};
};
&i2c1 {
status = "okay";
rk805: rk805@18 {
compatible = "rockchip,rk805";
reg = <0x18>;
interrupt-parent = <&gpio2>;
interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <1>;
clock-output-names = "xin32k", "rk805-clkout2";
gpio-controller;
#gpio-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
rockchip,system-power-controller;
wakeup-source;
vcc1-supply = <&vcc_sys>;
vcc2-supply = <&vcc_sys>;
vcc3-supply = <&vcc_sys>;
vcc4-supply = <&vcc_sys>;
vcc5-supply = <&vcc_io>;
vcc6-supply = <&vcc_io>;
regulators {
vdd_logic: DCDC_REG1 {
regulator-name = "vdd_logic";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1450000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
vdd_arm: DCDC_REG2 {
regulator-name = "vdd_arm";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1450000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <950000>;
};
};
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_io: DCDC_REG4 {
regulator-name = "vcc_io";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc_18: LDO_REG1 {
regulator-name = "vcc_18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc18_emmc: LDO_REG2 {
regulator-name = "vcc18_emmc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vdd_10: LDO_REG3 {
regulator-name = "vdd_10";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
};
};
};
&pinctrl {
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
&tsadc {
status = "okay";
};
&uart2 {
......
arch/arm64/boot/dts/rockchip/rk3328-rock64.dts 0 → 100644
View file @ e9a203a7
/*
* Copyright (c) 2017 PINE64
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "rk3328.dtsi"
/ {
model = "Pine64 Rock64";
compatible = "pine64,rock64", "rockchip,rk3328";
chosen {
stdout-path = "serial2:1500000n8";
};
gmac_clkin: external-gmac-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "gmac_clkin";
#clock-cells = <0>;
};
vcc_sd: sdmmc-regulator {
compatible = "regulator-fixed";
gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0m1_gpio>;
regulator-name = "vcc_sd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc_io>;
};
vcc_host_5v: vcc-host-5v-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&usb30_host_drv>;
regulator-name = "vcc_host_5v";
regulator-always-on;
vin-supply = <&vcc_sys>;
};
vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&usb20_host_drv>;
regulator-name = "vcc_host1_5v";
regulator-always-on;
vin-supply = <&vcc_sys>;
};
vcc_sys: vcc-sys {
compatible = "regulator-fixed";
regulator-name = "vcc_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
};
&cpu0 {
cpu-supply = <&vdd_arm>;
};
&cpu1 {
cpu-supply = <&vdd_arm>;
};
&cpu2 {
cpu-supply = <&vdd_arm>;
};
&cpu3 {
cpu-supply = <&vdd_arm>;
};
&emmc {
bus-width = <8>;
cap-mmc-highspeed;
non-removable;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
vmmc-supply = <&vcc_io>;
vqmmc-supply = <&vcc18_emmc>;
status = "okay";
};
&gmac2io {
assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
clock_in_out = "input";
phy-supply = <&vcc_io>;
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&rgmiim1_pins>;
snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
tx_delay = <0x26>;
rx_delay = <0x11>;
status = "okay";
};
&i2c1 {
status = "okay";
rk805: rk805@18 {
compatible = "rockchip,rk805";
reg = <0x18>;
interrupt-parent = <&gpio2>;
interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <1>;
clock-output-names = "xin32k", "rk805-clkout2";
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
rockchip,system-power-controller;
wakeup-source;
vcc1-supply = <&vcc_sys>;
vcc2-supply = <&vcc_sys>;
vcc3-supply = <&vcc_sys>;
vcc4-supply = <&vcc_sys>;
vcc5-supply = <&vcc_io>;
vcc6-supply = <&vcc_sys>;
regulators {
vdd_logic: DCDC_REG1 {
regulator-name = "vdd_logic";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1450000>;
regulator-ramp-delay = <12500>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
vdd_arm: DCDC_REG2 {
regulator-name = "vdd_arm";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1450000>;
regulator-ramp-delay = <12500>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <950000>;
};
};
vcc_ddr: DCDC_REG3 {
regulator-name = "vcc_ddr";
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
};
};
vcc_io: DCDC_REG4 {
regulator-name = "vcc_io";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vcc_18: LDO_REG1 {
regulator-name = "vdd_18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc18_emmc: LDO_REG2 {
regulator-name = "vcc_18emmc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vdd_10: LDO_REG3 {
regulator-name = "vdd_10";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
regulator-boot-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1000000>;
};
};
};
};
};
&io_domains {
status = "okay";
vccio1-supply = <&vcc_io>;
vccio2-supply = <&vcc18_emmc>;
vccio3-supply = <&vcc_io>;
vccio4-supply = <&vcc_18>;
vccio5-supply = <&vcc_io>;
vccio6-supply = <&vcc_io>;
pmuio-supply = <&vcc_io>;
};
&pinctrl {
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
usb2 {
usb20_host_drv: usb20-host-drv {
rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb3 {
usb30_host_drv: usb30-host-drv {
rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
disable-wp;
max-frequency = <150000000>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
vmmc-supply = <&vcc_sd>;
status = "okay";
};
&tsadc {
rockchip,hw-tshut-mode = <0>;
rockchip,hw-tshut-polarity = <0>;
status = "okay";
};
&uart2 {
status = "okay";
};
&u2phy {
status = "okay";
u2phy_host: host-port {
status = "okay";
};
u2phy_otg: otg-port {
status = "okay";
};
};
&usb20_otg {
dr_mode = "host";
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
arch/arm64/boot/dts/rockchip/rk3328.dtsi
View file @ e9a203a7
......@@ -47,6 +47,7 @@
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/power/rk3328-power.h>
#include <dt-bindings/soc/rockchip,boot-mode.h>
#include <dt-bindings/thermal/thermal.h>
/ {
compatible = "rockchip,rk3328";
......@@ -74,8 +75,11 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x0>;
clocks = <&cru ARMCLK>;
#cooling-cells = <2>;
dynamic-power-coefficient = <120>;
enable-method = "psci";
next-level-cache = <&l2>;
operating-points-v2 = <&cpu0_opp_table>;
};
cpu1: cpu@1 {
......@@ -83,8 +87,10 @@ cpu1: cpu@1 {
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x1>;
clocks = <&cru ARMCLK>;
dynamic-power-coefficient = <120>;
enable-method = "psci";
next-level-cache = <&l2>;
operating-points-v2 = <&cpu0_opp_table>;
};
cpu2: cpu@2 {
......@@ -92,8 +98,10 @@ cpu2: cpu@2 {
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x2>;
clocks = <&cru ARMCLK>;
dynamic-power-coefficient = <120>;
enable-method = "psci";
next-level-cache = <&l2>;
operating-points-v2 = <&cpu0_opp_table>;
};
cpu3: cpu@3 {
......@@ -101,8 +109,10 @@ cpu3: cpu@3 {
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x3>;
clocks = <&cru ARMCLK>;
dynamic-power-coefficient = <120>;
enable-method = "psci";
next-level-cache = <&l2>;
operating-points-v2 = <&cpu0_opp_table>;
};
l2: l2-cache0 {
......@@ -110,6 +120,43 @@ l2: l2-cache0 {
};
};
cpu0_opp_table: opp_table0 {
compatible = "operating-points-v2";
opp-shared;
opp-408000000 {
opp-hz = /bits/ 64 <408000000>;
opp-microvolt = <950000>;
clock-latency-ns = <40000>;
opp-suspend;
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <950000>;
clock-latency-ns = <40000>;
};
opp-816000000 {
opp-hz = /bits/ 64 <816000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <40000>;
};
opp-1008000000 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <1100000>;
clock-latency-ns = <40000>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1225000>;
clock-latency-ns = <40000>;
};
opp-1296000000 {
opp-hz = /bits/ 64 <1296000000>;
opp-microvolt = <1300000>;
clock-latency-ns = <40000>;
};
};
amba {
compatible = "simple-bus";
#address-cells = <2>;
......@@ -156,6 +203,39 @@ xin24m: xin24m {
clock-output-names = "xin24m";
};
i2s0: i2s@ff000000 {
compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
reg = <0x0 0xff000000 0x0 0x1000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
clock-names = "i2s_clk", "i2s_hclk";
dmas = <&dmac 11>, <&dmac 12>;
dma-names = "tx", "rx";
status = "disabled";
};
i2s1: i2s@ff010000 {
compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
reg = <0x0 0xff010000 0x0 0x1000>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
clock-names = "i2s_clk", "i2s_hclk";
dmas = <&dmac 14>, <&dmac 15>;
dma-names = "tx", "rx";
status = "disabled";
};
i2s2: i2s@ff020000 {
compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
reg = <0x0 0xff020000 0x0 0x1000>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
clock-names = "i2s_clk", "i2s_hclk";
dmas = <&dmac 0>, <&dmac 1>;
dma-names = "tx", "rx";
status = "disabled";
};
spdif: spdif@ff030000 {
compatible = "rockchip,rk3328-spdif";
reg = <0x0 0xff030000 0x0 0x1000>;
......@@ -169,6 +249,27 @@ spdif: spdif@ff030000 {
status = "disabled";
};
pdm: pdm@ff040000 {
compatible = "rockchip,pdm";
reg = <0x0 0xff040000 0x0 0x1000>;
clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
clock-names = "pdm_clk", "pdm_hclk";
dmas = <&dmac 16>;
dma-names = "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pdmm0_clk
&pdmm0_sdi0
&pdmm0_sdi1
&pdmm0_sdi2
&pdmm0_sdi3>;
pinctrl-1 = <&pdmm0_clk_sleep
&pdmm0_sdi0_sleep
&pdmm0_sdi1_sleep
&pdmm0_sdi2_sleep
&pdmm0_sdi3_sleep>;
status = "disabled";
};
grf: syscon@ff100000 {
compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
reg = <0x0 0xff100000 0x0 0x1000>;
......@@ -326,6 +427,108 @@ wdt: watchdog@ff1a0000 {
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
};
pwm0: pwm@ff1b0000 {
compatible = "rockchip,rk3328-pwm";
reg = <0x0 0xff1b0000 0x0 0x10>;
clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
clock-names = "pwm", "pclk";
pinctrl-names = "default";
pinctrl-0 = <&pwm0_pin>;
#pwm-cells = <3>;
status = "disabled";
};
pwm1: pwm@ff1b0010 {
compatible = "rockchip,rk3328-pwm";
reg = <0x0 0xff1b0010 0x0 0x10>;
clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
clock-names = "pwm", "pclk";
pinctrl-names = "default";
pinctrl-0 = <&pwm1_pin>;
#pwm-cells = <3>;
status = "disabled";
};
pwm2: pwm@ff1b0020 {
compatible = "rockchip,rk3328-pwm";
reg = <0x0 0xff1b0020 0x0 0x10>;
clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
clock-names = "pwm", "pclk";
pinctrl-names = "default";
pinctrl-0 = <&pwm2_pin>;
#pwm-cells = <3>;
status = "disabled";
};
pwm3: pwm@ff1b0030 {
compatible = "rockchip,rk3328-pwm";
reg = <0x0 0xff1b0030 0x0 0x10>;
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
clock-names = "pwm", "pclk";
pinctrl-names = "default";
pinctrl-0 = <&pwmir_pin>;
#pwm-cells = <3>;
status = "disabled";
};
thermal-zones {
soc_thermal: soc-thermal {
polling-delay-passive = <20>;
polling-delay = <1000>;
sustainable-power = <1000>;
thermal-sensors = <&tsadc 0>;
trips {
threshold: trip-point0 {
temperature = <70000>;
hysteresis = <2000>;
type = "passive";
};
target: trip-point1 {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
soc_crit: soc-crit {
temperature = <95000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&target>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
contribution = <4096>;
};
};
};
};
tsadc: tsadc@ff250000 {
compatible = "rockchip,rk3328-tsadc";
reg = <0x0 0xff250000 0x0 0x100>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
assigned-clocks = <&cru SCLK_TSADC>;
assigned-clock-rates = <50000>;
clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
clock-names = "tsadc", "apb_pclk";
pinctrl-names = "init", "default", "sleep";
pinctrl-0 = <&otp_gpio>;
pinctrl-1 = <&otp_out>;
pinctrl-2 = <&otp_gpio>;
resets = <&cru SRST_TSADC>;
reset-names = "tsadc-apb";
rockchip,grf = <&grf>;
rockchip,hw-tshut-temp = <100000>;
#thermal-sensor-cells = <1>;
status = "disabled";
};
saradc: adc@ff280000 {
compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
reg = <0x0 0xff280000 0x0 0x100>;
......@@ -338,6 +541,51 @@ saradc: adc@ff280000 {
status = "disabled";
};
h265e_mmu: iommu@ff330200 {
compatible = "rockchip,iommu";
reg = <0x0 0xff330200 0 0x100>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "h265e_mmu";
#iommu-cells = <0>;
status = "disabled";
};
vepu_mmu: iommu@ff340800 {
compatible = "rockchip,iommu";
reg = <0x0 0xff340800 0x0 0x40>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vepu_mmu";
#iommu-cells = <0>;
status = "disabled";
};
vpu_mmu: iommu@ff350800 {
compatible = "rockchip,iommu";
reg = <0x0 0xff350800 0x0 0x40>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vpu_mmu";
#iommu-cells = <0>;
status = "disabled";
};
rkvdec_mmu: iommu@ff360480 {
compatible = "rockchip,iommu";
reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "rkvdec_mmu";
#iommu-cells = <0>;
status = "disabled";
};
vop_mmu: iommu@ff373f00 {
compatible = "rockchip,iommu";
reg = <0x0 0xff373f00 0x0 0x100>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "vop_mmu";
#iommu-cells = <0>;
status = "disabled";
};
cru: clock-controller@ff440000 {
compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
reg = <0x0 0xff440000 0x0 0x1000>;
......@@ -704,6 +952,62 @@ hdmii2c_xfer: hdmii2c-xfer {
};
};
pdm-0 {
pdmm0_clk: pdmm0-clk {
rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>;
};
pdmm0_fsync: pdmm0-fsync {
rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>;
};
pdmm0_sdi0: pdmm0-sdi0 {
rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>;
};
pdmm0_sdi1: pdmm0-sdi1 {
rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>;
};
pdmm0_sdi2: pdmm0-sdi2 {
rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>;
};
pdmm0_sdi3: pdmm0-sdi3 {
rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>;
};
pdmm0_clk_sleep: pdmm0-clk-sleep {
rockchip,pins =
<2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>;
};
pdmm0_sdi0_sleep: pdmm0-sdi0-sleep {
rockchip,pins =
<2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>;
};
pdmm0_sdi1_sleep: pdmm0-sdi1-sleep {
rockchip,pins =
<2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>;
};
pdmm0_sdi2_sleep: pdmm0-sdi2-sleep {
rockchip,pins =
<2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
};
pdmm0_sdi3_sleep: pdmm0-sdi3-sleep {
rockchip,pins =
<2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
};
pdmm0_fsync_sleep: pdmm0-fsync-sleep {
rockchip,pins =
<2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
};
};
tsadc {
otp_gpio: otp-gpio {
rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
......
arch/arm64/boot/dts/rockchip/rk3368.dtsi
View file @ e9a203a7
......@@ -113,7 +113,8 @@ cpu_l0: cpu@0 {
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>; /* min followed by max */
};
......@@ -122,6 +123,8 @@ cpu_l1: cpu@1 {
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
operating-points-v2 = <&cluster0_opp>;
};
cpu_l2: cpu@2 {
......@@ -129,6 +132,8 @@ cpu_l2: cpu@2 {
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
operating-points-v2 = <&cluster0_opp>;
};
cpu_l3: cpu@3 {
......@@ -136,6 +141,8 @@ cpu_l3: cpu@3 {
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
operating-points-v2 = <&cluster0_opp>;
};
cpu_b0: cpu@100 {
......@@ -143,7 +150,8 @@ cpu_b0: cpu@100 {
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x100>;
enable-method = "psci";
clocks = <&cru ARMCLKB>;
operating-points-v2 = <&cluster1_opp>;
#cooling-cells = <2>; /* min followed by max */
};
......@@ -152,6 +160,8 @@ cpu_b1: cpu@101 {
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x101>;
enable-method = "psci";
clocks = <&cru ARMCLKB>;
operating-points-v2 = <&cluster1_opp>;
};
cpu_b2: cpu@102 {
......@@ -159,6 +169,8 @@ cpu_b2: cpu@102 {
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x102>;
enable-method = "psci";
clocks = <&cru ARMCLKB>;
operating-points-v2 = <&cluster1_opp>;
};
cpu_b3: cpu@103 {
......@@ -166,6 +178,62 @@ cpu_b3: cpu@103 {
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x0 0x103>;
enable-method = "psci";
clocks = <&cru ARMCLKB>;
operating-points-v2 = <&cluster1_opp>;
};
};
cluster0_opp: opp-table0 {
compatible = "operating-points-v2";
opp-shared;
opp00 {
opp-hz = /bits/ 64 <312000000>;
opp-microvolt = <950000>;
clock-latency-ns = <40000>;
};
opp01 {
opp-hz = /bits/ 64 <408000000>;
opp-microvolt = <950000>;
};
opp02 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <950000>;
};
opp03 {
opp-hz = /bits/ 64 <816000000>;
opp-microvolt = <1025000>;
};
opp04 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <1125000>;
};
};
cluster1_opp: opp-table1 {
compatible = "operating-points-v2";
opp-shared;
opp00 {
opp-hz = /bits/ 64 <312000000>;
opp-microvolt = <950000>;
clock-latency-ns = <40000>;
};
opp01 {
opp-hz = /bits/ 64 <408000000>;
opp-microvolt = <950000>;
};
opp02 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <950000>;
};
opp03 {
opp-hz = /bits/ 64 <816000000>;
opp-microvolt = <975000>;
};
opp04 {
opp-hz = /bits/ 64 <1008000000>;
opp-microvolt = <1050000>;
};
};
......@@ -737,6 +805,55 @@ i2s_8ch: i2s-8ch@ff898000 {
status = "disabled";
};
iep_mmu: iommu@ff900800 {
compatible = "rockchip,iommu";
reg = <0x0 0xff900800 0x0 0x100>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "iep_mmu";
#iommu-cells = <0>;
status = "disabled";
};
isp_mmu: iommu@ff914000 {
compatible = "rockchip,iommu";
reg = <0x0 0xff914000 0x0 0x100>,
<0x0 0xff915000 0x0 0x100>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "isp_mmu";
#iommu-cells = <0>;
rockchip,disable-mmu-reset;
status = "disabled";
};
vop_mmu: iommu@ff930300 {
compatible = "rockchip,iommu";
reg = <0x0 0xff930300 0x0 0x100>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vop_mmu";
#iommu-cells = <0>;
status = "disabled";
};
hevc_mmu: iommu@ff9a0440 {
compatible = "rockchip,iommu";
reg = <0x0 0xff9a0440 0x0 0x40>,
<0x0 0xff9a0480 0x0 0x40>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hevc_mmu";
#iommu-cells = <0>;
status = "disabled";
};
vpu_mmu: iommu@ff9a0800 {
compatible = "rockchip,iommu";
reg = <0x0 0xff9a0800 0x0 0x100>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vepu_mmu", "vdpu_mmu";
#iommu-cells = <0>;
status = "disabled";
};
gic: interrupt-controller@ffb71000 {
compatible = "arm,gic-400";
interrupt-controller;
......
arch/arm64/boot/dts/rockchip/rk3399-firefly.dts
View file @ e9a203a7
......@@ -43,6 +43,7 @@
/dts-v1/;
#include <dt-bindings/pwm/pwm.h>
#include "rk3399.dtsi"
#include "rk3399-opp.dtsi"
/ {
model = "Firefly-RK3399 Board";
......
arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
View file @ e9a203a7
......@@ -612,12 +612,7 @@ ap_i2c_mic: &i2c1 {
headsetcodec: rt5514@57 {
compatible = "realtek,rt5514";
reg = <0x57>;
interrupt-parent = <&gpio1>;
interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&mic_int>;
realtek,dmic-init-delay = <20>;
wakeup-source;
realtek,dmic-init-delay-ms = <20>;
};
};
......@@ -826,9 +821,13 @@ &spi2 {
wacky_spi_audio: spi2@0 {
compatible = "realtek,rt5514";
reg = <0>;
interrupt-parent = <&gpio1>;
interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&mic_int>;
/* May run faster once verified. */
spi-max-frequency = <10000000>;
wakeup-source;
};
};
......
arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dts 0 → 100644
View file @ e9a203a7
/*
* Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "rk3399-puma.dtsi"
/ {
model = "Theobroma Systems RK3399-Q7 SoM";
compatible = "tsd,rk3399-puma-haikou", "rockchip,rk3399";
chosen {
stdout-path = "serial0:115200n8";
};
leds {
pinctrl-0 = <&led_pin_module>, <&led_sd_haikou>;
sd-card-led {
label = "sd_card_led";
gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc0";
};
};
dc_12v: dc-12v {
compatible = "regulator-fixed";
regulator-name = "dc_12v";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
};
vcc3v3_baseboard: vcc3v3-baseboard {
compatible = "regulator-fixed";
regulator-name = "vcc3v3_baseboard";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&dc_12v>;
};
vcc5v0_otg: vcc5v0-otg-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&otg_vbus_drv>;
regulator-name = "vcc5v0_otg";
regulator-always-on;
};
};
&i2c1 {
status = "okay";
clock-frequency = <400000>;
};
&i2c2 {
status = "okay";
clock-frequency = <400000>;
};
&i2c3 {
i2c-scl-rising-time-ns = <450>;
i2c-scl-falling-time-ns = <15>;
status = "okay";
};
&i2c4 {
status = "okay";
clock-frequency = <400000>;
};
&i2c6 {
status = "okay";
clock-frequency = <400000>;
};
&i2s0 {
status = "okay";
rockchip,playback-channels = <8>;
rockchip,capture-channels = <8>;
#sound-dai-cells = <0>;
status = "okay";
};
&pcie_phy {
status = "okay";
};
&pcie0 {
ep-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>;
num-lanes = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_clkreqn_cpm>;
status = "okay";
};
&pinctrl {
pinctrl-names = "default";
pinctrl-0 = <&haikou_pin_hog>;
hog {
haikou_pin_hog: haikou-pin-hog {
rockchip,pins =
/* LID_BTN */
<RK_GPIO0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>,
/* BATLOW# */
<RK_GPIO0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>,
/* SLP_BTN# */
<RK_GPIO0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>,
/* BIOS_DISABLE# */
<RK_GPIO0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
leds {
led_sd_haikou: led-sd-gpio {
rockchip,pins =
<RK_GPIO1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
usb2 {
otg_vbus_drv: otg-vbus-drv {
rockchip,pins =
<RK_GPIO0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pwm0 {
status = "okay";
};
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>;
disable-wp;
max-frequency = <150000000>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
vmmc-supply = <&vcc3v3_baseboard>;
status = "okay";
};
&spi5 {
status = "okay";
};
&u2phy0 {
status = "okay";
};
&usbdrd3_0 {
status = "okay";
};
&usbdrd_dwc3_0 {
dr_mode = "otg";
status = "okay";
};
&u2phy0_host {
phy-supply = <&vcc5v0_otg>;
status = "okay";
};
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
status = "okay";
};
&uart2 {
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_host0_ohci {
status = "okay";
};
arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi 0 → 100644
View file @ e9a203a7
This diff is collapsed.
arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts 0 → 100644
View file @ e9a203a7
/*
* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "rk3399-sapphire.dtsi"
/ {
model = "Excavator-RK3399 Board";
compatible = "rockchip,rk3399-sapphire-excavator", "rockchip,rk3399";
adc-keys {
compatible = "adc-keys";
io-channels = <&saradc 1>;
io-channel-names = "buttons";
keyup-threshold-microvolt = <1800000>;
poll-interval = <100>;
button-up {
label = "Volume Up";
linux,code = <KEY_VOLUMEUP>;
press-threshold-microvolt = <100000>;
};
button-down {
label = "Volume Down";
linux,code = <KEY_VOLUMEDOWN>;
press-threshold-microvolt = <300000>;
};
back {
label = "Back";
linux,code = <KEY_BACK>;
press-threshold-microvolt = <985000>;
};
menu {
label = "Menu";
linux,code = <KEY_MENU>;
press-threshold-microvolt = <1314000>;
};
};
edp_panel: edp-panel {
compatible ="lg,lp079qx1-sp0v", "simple-panel";
backlight = <&backlight>;
enable-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&lcd_panel_reset>;
power-supply = <&vcc3v3_s0>;
ports {
panel_in_edp: endpoint {
remote-endpoint = <&edp_out_panel>;
};
};
};
keys: gpio-keys {
compatible = "gpio-keys";
autorepeat;
power {
debounce-interval = <100>;
gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
label = "GPIO Power";
linux,code = <KEY_POWER>;
linux,input-type = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pwr_btn>;
wakeup-source;
};
};
rt5651-sound {
compatible = "simple-audio-card";
simple-audio-card,name = "realtek,rt5651-codec";
simple-audio-card,format = "i2s";
simple-audio-card,mclk-fs = <256>;
simple-audio-card,widgets =
"Microphone", "Mic Jack",
"Headphone", "Headphone Jack";
simple-audio-card,routing =
"Mic Jack", "MICBIAS1",
"IN1P", "Mic Jack",
"Headphone Jack", "HPOL",
"Headphone Jack", "HPOR";
simple-audio-card,cpu {
sound-dai = <&i2s0>;
};
simple-audio-card,codec {
sound-dai = <&rt5651>;
};
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&rk808 1>;
clock-names = "ext_clock";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h>;
/*
* On the module itself this is one of these (depending
* on the actual card populated):
* - SDIO_RESET_L_WL_REG_ON
* - PDN (power down when low)
*/
reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
};
};
&backlight {
enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&edp {
status = "okay";
ports {
edp_out: port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
edp_out_panel: endpoint@0 {
reg = <0>;
remote-endpoint = <&panel_in_edp>;
};
};
};
};
&i2c1 {
i2c-scl-rising-time-ns = <300>;
i2c-scl-falling-time-ns = <15>;
status = "okay";
rt5651: rt5651@1a {
compatible = "rockchip,rt5651";
reg = <0x1a>;
clocks = <&cru SCLK_I2S_8CH_OUT>;
clock-names = "mclk";
hp-det-gpio = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>;
spk-con-gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
#sound-dai-cells = <0>;
};
};
&i2c4 {
i2c-scl-rising-time-ns = <600>;
i2c-scl-falling-time-ns = <20>;
status = "okay";
accelerometer@68 {
compatible = "invensense,mpu6500";
reg = <0x68>;
interrupt-parent = <&gpio1>;
interrupts = <RK_PC6 IRQ_TYPE_EDGE_RISING>;
};
};
&i2s0 {
rockchip,playback-channels = <8>;
rockchip,capture-channels = <8>;
#sound-dai-cells = <0>;
status = "okay";
};
&i2s2 {
#sound-dai-cells = <0>;
status = "okay";
};
&pinctrl {
buttons {
pwr_btn: pwr-btn {
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
lcd-panel {
lcd_panel_reset: lcd-panel-reset {
rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
&spdif {
i2c-scl-rising-time-ns = <450>;
i2c-scl-falling-time-ns = <15>;
#sound-dai-cells = <0>;
status = "okay";
};
arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi 0 → 100644
View file @ e9a203a7
This diff is collapsed.
arch/arm64/boot/dts/rockchip/rk3399.dtsi
View file @ e9a203a7
......@@ -160,6 +160,11 @@ cpu_b1: cpu@101 {
};
};
display-subsystem {
compatible = "rockchip,display-subsystem";
ports = <&vopl_out>, <&vopb_out>;
};
pmu_a53 {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
......@@ -407,6 +412,7 @@ usbdrd_dwc3_0: dwc3 {
snps,dis-u2-freeclk-exists-quirk;
snps,dis_u2_susphy_quirk;
snps,dis-del-phy-power-chg-quirk;
snps,dis-tx-ipgap-linecheck-quirk;
status = "disabled";
};
};
......@@ -434,6 +440,7 @@ usbdrd_dwc3_1: dwc3 {
snps,dis-u2-freeclk-exists-quirk;
snps,dis_u2_susphy_quirk;
snps,dis-del-phy-power-chg-quirk;
snps,dis-tx-ipgap-linecheck-quirk;
status = "disabled";
};
};
......@@ -956,6 +963,10 @@ pd_gpu@RK3399_PD_GPU {
};
/* These power domains are grouped by VD_LOGIC */
pd_edp@RK3399_PD_EDP {
reg = <RK3399_PD_EDP>;
clocks = <&cru PCLK_EDP_CTRL>;
};
pd_emmc@RK3399_PD_EMMC {
reg = <RK3399_PD_EMMC>;
clocks = <&cru ACLK_EMMC>;
......@@ -1164,6 +1175,33 @@ pwm3: pwm@ff420030 {
status = "disabled";
};
vpu_mmu: iommu@ff650800 {
compatible = "rockchip,iommu";
reg = <0x0 0xff650800 0x0 0x40>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "vpu_mmu";
#iommu-cells = <0>;
status = "disabled";
};
vdec_mmu: iommu@ff660480 {
compatible = "rockchip,iommu";
reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "vdec_mmu";
#iommu-cells = <0>;
status = "disabled";
};
iep_mmu: iommu@ff670800 {
compatible = "rockchip,iommu";
reg = <0x0 0xff670800 0x0 0x40>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "iep_mmu";
#iommu-cells = <0>;
status = "disabled";
};
efuse0: efuse@ff690000 {
compatible = "rockchip,rk3399-efuse";
reg = <0x0 0xff690000 0x0 0x80>;
......@@ -1443,6 +1481,211 @@ i2s2: i2s@ff8a0000 {
status = "disabled";
};
vopl: vop@ff8f0000 {
compatible = "rockchip,rk3399-vop-lit";
reg = <0x0 0xff8f0000 0x0 0x3efc>;
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
assigned-clock-rates = <400000000>, <100000000>;
clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
iommus = <&vopl_mmu>;
power-domains = <&power RK3399_PD_VOPL>;
resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
reset-names = "axi", "ahb", "dclk";
status = "disabled";
vopl_out: port {
#address-cells = <1>;
#size-cells = <0>;
vopl_out_mipi: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi_in_vopl>;
};
vopl_out_edp: endpoint@1 {
reg = <1>;
remote-endpoint = <&edp_in_vopl>;
};
vopl_out_hdmi: endpoint@2 {
reg = <2>;
remote-endpoint = <&hdmi_in_vopl>;
};
};
};
vopl_mmu: iommu@ff8f3f00 {
compatible = "rockchip,iommu";
reg = <0x0 0xff8f3f00 0x0 0x100>;
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "vopl_mmu";
clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
clock-names = "aclk", "hclk";
power-domains = <&power RK3399_PD_VOPL>;
#iommu-cells = <0>;
status = "disabled";
};
vopb: vop@ff900000 {
compatible = "rockchip,rk3399-vop-big";
reg = <0x0 0xff900000 0x0 0x3efc>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
assigned-clock-rates = <400000000>, <100000000>;
clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
iommus = <&vopb_mmu>;
power-domains = <&power RK3399_PD_VOPB>;
resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
reset-names = "axi", "ahb", "dclk";
status = "disabled";
vopb_out: port {
#address-cells = <1>;
#size-cells = <0>;
vopb_out_edp: endpoint@0 {
reg = <0>;
remote-endpoint = <&edp_in_vopb>;
};
vopb_out_mipi: endpoint@1 {
reg = <1>;
remote-endpoint = <&mipi_in_vopb>;
};
vopb_out_hdmi: endpoint@2 {
reg = <2>;
remote-endpoint = <&hdmi_in_vopb>;
};
};
};
vopb_mmu: iommu@ff903f00 {
compatible = "rockchip,iommu";
reg = <0x0 0xff903f00 0x0 0x100>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "vopb_mmu";
clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
clock-names = "aclk", "hclk";
power-domains = <&power RK3399_PD_VOPB>;
#iommu-cells = <0>;
status = "disabled";
};
isp0_mmu: iommu@ff914000 {
compatible = "rockchip,iommu";
reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "isp0_mmu";
#iommu-cells = <0>;
rockchip,disable-mmu-reset;
status = "disabled";
};
isp1_mmu: iommu@ff924000 {
compatible = "rockchip,iommu";
reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "isp1_mmu";
#iommu-cells = <0>;
rockchip,disable-mmu-reset;
status = "disabled";
};
hdmi: hdmi@ff940000 {
compatible = "rockchip,rk3399-dw-hdmi";
reg = <0x0 0xff940000 0x0 0x20000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru PLL_VPLL>, <&cru PCLK_VIO_GRF>;
clock-names = "iahb", "isfr", "vpll", "grf";
power-domains = <&power RK3399_PD_HDCP>;
reg-io-width = <4>;
rockchip,grf = <&grf>;
status = "disabled";
ports {
hdmi_in: port {
#address-cells = <1>;
#size-cells = <0>;
hdmi_in_vopb: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopb_out_hdmi>;
};
hdmi_in_vopl: endpoint@1 {
reg = <1>;
remote-endpoint = <&vopl_out_hdmi>;
};
};
};
};
mipi_dsi: mipi@ff960000 {
compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
reg = <0x0 0xff960000 0x0 0x8000>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
<&cru SCLK_DPHY_TX0_CFG>;
clock-names = "ref", "pclk", "phy_cfg";
power-domains = <&power RK3399_PD_VIO>;
rockchip,grf = <&grf>;
status = "disabled";
ports {
mipi_in: port {
#address-cells = <1>;
#size-cells = <0>;
mipi_in_vopb: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopb_out_mipi>;
};
mipi_in_vopl: endpoint@1 {
reg = <1>;
remote-endpoint = <&vopl_out_mipi>;
};
};
};
};
edp: edp@ff970000 {
compatible = "rockchip,rk3399-edp";
reg = <0x0 0xff970000 0x0 0x8000>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
clock-names = "dp", "pclk";
pinctrl-names = "default";
pinctrl-0 = <&edp_hpd>;
power-domains = <&power RK3399_PD_EDP>;
resets = <&cru SRST_P_EDP_CTRL>;
reset-names = "dp";
rockchip,grf = <&grf>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
edp_in: port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
edp_in_vopb: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopb_out_edp>;
};
edp_in_vopl: endpoint@1 {
reg = <1>;
remote-endpoint = <&vopl_out_edp>;
};
};
};
};
gpu: gpu@ff9a0000 {
compatible = "rockchip,rk3399-mali", "arm,mali-t860";
reg = <0x0 0xff9a0000 0x0 0x10000>;
......
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