e1000e: long access timeouts when I217/I218 MAC and PHY are out of sync
When the MAC and PHY are in two different modes (different power levels and interconnect speeds), it could take a long time before a PHY register access timed out using the existing MAC-PHY interconnect configuration coded into the driver for ICH- and PCH-based LOMs. Introduce an I217/I218- specific .setup_physical_interface operation which does not override the interconnect configuration in the NVM. Signed-off-by: Bruce Allan <bruce.w.allan@intel.com> Tested-by: Jeff Pieper <jeffrey.e.pieper@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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