Commit f121edb6 authored by Phil Reid's avatar Phil Reid Committed by Stephen Boyd

dt-bindings: clock: cdce925: Add regulator documentation

The cdce925 has two separate supply pins. Document the bindings
for them.
Signed-off-by: default avatarPhil Reid <preid@electromag.com.au>
Link: https://lkml.kernel.org/r/1561691950-42154-2-git-send-email-preid@electromag.com.auReviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 5f9e832c
...@@ -24,6 +24,8 @@ Required properties: ...@@ -24,6 +24,8 @@ Required properties:
Optional properties: Optional properties:
- xtal-load-pf: Crystal load-capacitor value to fine-tune performance on a - xtal-load-pf: Crystal load-capacitor value to fine-tune performance on a
board, or to compensate for external influences. board, or to compensate for external influences.
- vdd-supply: A regulator node for Vdd
- vddout-supply: A regulator node for Vddout
For all PLL1, PLL2, ... an optional child node can be used to specify spread For all PLL1, PLL2, ... an optional child node can be used to specify spread
spectrum clocking parameters for a board. spectrum clocking parameters for a board.
...@@ -41,6 +43,8 @@ Example: ...@@ -41,6 +43,8 @@ Example:
clocks = <&xtal_27Mhz>; clocks = <&xtal_27Mhz>;
#clock-cells = <1>; #clock-cells = <1>;
xtal-load-pf = <5>; xtal-load-pf = <5>;
vdd-supply = <&1v8-reg>;
vddout-supply = <&3v3-reg>;
/* PLL options to get SSC 1% centered */ /* PLL options to get SSC 1% centered */
PLL2 { PLL2 {
spread-spectrum = <4>; spread-spectrum = <4>;
......
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