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Commit f35ece20 authored by Dave Jiang's avatar Dave Jiang Committed by Russell King
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[ARM PATCH] 2039/1: 2033/6 resubmission 

Patch from Dave Jiang

Rewrite if uncompress.h to use the proper machine_is_X function call.
parent 2a3350b6
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Showing with 793 additions and 88 deletions
include/asm-arm/arch-iop3xx/dma.h
View file @ f35ece20
......@@ -11,44 +11,6 @@
#ifndef _IOP3XX_DMA_H_P
#define _IOP3XX_DMA_H_P
/* 80310 not supported */
#define MAX_IOP3XX_DMA_CHANNEL 2
#define MAX_DMA_DESC 64 /*128 */
#define DMA_FREE 0x0
#define DMA_ACTIVE 0x1
#define DMA_COMPLETE 0x2
#define DMA_ERROR 0x4
/*
* Make the generic DMA bits go away since we don't use it
*/
#define MAX_DMA_CHANNELS 0
#define MAX_DMA_ADDRESS 0xffffffff
#define DMA_POLL 0x0
#define DMA_INTERRUPT 0x1
#define DMA_DCR_MTM 0x00000040 /* memory to memory transfer */
#define DMA_DCR_DAC 0x00000020 /* Dual Addr Cycle Enab */
#define DMA_DCR_IE 0x00000010 /* Interrupt Enable */
#define DMA_DCR_PCI_IOR 0x00000002 /* I/O Read */
#define DMA_DCR_PCI_IOW 0x00000003 /* I/O Write */
#define DMA_DCR_PCI_MR 0x00000006 /* Memory Read */
#define DMA_DCR_PCI_MW 0x00000007 /* Memory Write */
#define DMA_DCR_PCI_CR 0x0000000A /* Configuration Read */
#define DMA_DCR_PCI_CW 0x0000000B /* Configuration Write */
#define DMA_DCR_PCI_MRM 0x0000000C /* Memory Read Multiple */
#define DMA_DCR_PCI_MRL 0x0000000E /* Memory Read Line */
#define DMA_DCR_PCI_MWI 0x0000000F /* Mem Write and Inval */
//extern iop3xx_dma_t dma_chan[2];
/* function prototypes */
#ifdef CONFIG_IOP3XX_DMACOPY
extern int iop_memcpy;
void * dma_memcpy(void * to, const void* from, __kernel_size_t n);
#endif
#endif /* _ASM_ARCH_DMA_H_P */
include/asm-arm/arch-iop3xx/hardware.h
View file @ f35ece20
......@@ -4,8 +4,6 @@
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
#include <linux/config.h>
/*
* Note about PCI IO space mappings
*
......@@ -15,24 +13,42 @@
* The PCI IO space is located at virtual 0xfe000000 from physical
* 0x90000000. The PCI BARs must be programmed with physical addresses,
* but when we read them, we convert them to virtual addresses. See
* arch/arm/mach-iop3xx/iop3XX-pci.c
* arch/arm/mach-iop3xx/iop3xx-pci.c
*/
#define pcibios_assign_all_busses() 1
#ifdef CONFIG_ARCH_IOP321
#define PCIBIOS_MIN_IO 0x90000000
#define PCIBIOS_MIN_MEM 0x80000000
#include "iop321.h"
/*
* The min PCI I/O and MEM space are dependent on what specific
* chipset/platform we are running on, so instead of hardcoding with
* #ifdefs, we just fill these in the platform level PCI init code.
*/
#ifndef __ASSEMBLY__
extern unsigned long iop3xx_pcibios_min_io;
extern unsigned long iop3xx_pcibios_min_mem;
#ifdef CONFIG_ARCH_IQ80321
#include "iq80321.h"
#endif
extern unsigned int processor_id;
#endif
/*
* We just set these to zero since they are really bogus anyways
*/
#define PCIBIOS_MIN_IO (iop3xx_pcibios_min_io)
#define PCIBIOS_MIN_MEM (iop3xx_pcibios_min_mem)
/*
* Generic chipset bits
*
*/
#include "iop321.h"
#include "iop331.h"
/*
* Board specific bits
*/
#include "iq80321.h"
#include "iq31244.h"
#include "iq80331.h"
#endif /* _ASM_ARCH_HARDWARE_H */
include/asm-arm/arch-iop3xx/iop321-irqs.h
View file @ f35ece20
......@@ -9,8 +9,8 @@
* published by the Free Software Foundation.
*
*/
#include <linux/config.h>
#ifndef _IOP321_IRQS_H_
#define _IOP321_IRQS_H_
/*
* IOP80321 chipset interrupts
......@@ -62,7 +62,6 @@
/*
* Interrupts available on the IQ80321 board
*/
#ifdef CONFIG_ARCH_IQ80321
/*
* On board devices
......@@ -78,7 +77,24 @@
#define IRQ_IQ80321_INTC IRQ_IOP321_XINT2
#define IRQ_IQ80321_INTD IRQ_IOP321_XINT3
#endif // CONFIG_ARCH_IQ80321
/*
* Interrupts on the IQ31244 board
*/
/*
* On board devices
*/
#define IRQ_IQ31244_UART IRQ_IOP321_XINT1
#define IRQ_IQ31244_I82546 IRQ_IOP321_XINT0
#define IRQ_IQ31244_SATA IRQ_IOP321_XINT2
#define IRQ_IQ31244_PCIX_SLOT IRQ_IOP321_XINT3
#define XSCALE_PMU_IRQ IRQ_IOP321_CORE_PMU
/*
* PCI interrupts
*/
#define IRQ_IQ31244_INTA IRQ_IOP321_XINT0
#define IRQ_IQ31244_INTB IRQ_IOP321_XINT1
#define IRQ_IQ31244_INTC IRQ_IOP321_XINT2
#define IRQ_IQ31244_INTD IRQ_IOP321_XINT3
#endif // _IOP321_IRQ_H_
include/asm-arm/arch-iop3xx/iop321.h
View file @ f35ece20
......@@ -20,23 +20,29 @@
* IOP3xx variants but behave slightly differently on each.
*/
#ifndef __ASSEMBLY__
#define iop_is_321() ((processor_id & 0xfffff7e0) == 0x69052420)
#ifdef CONFIG_ARCH_IOP321
#define iop_is_321() (((processor_id & 0xfffff5e0) == 0x69052420))
#else
#define iop_is_321() 0
#endif
#endif
/*
* IOP321 I/O and Mem space regions for PCI autoconfiguration
*/
#define IOP321_PCI_LOWER_IO 0x90000000
#define IOP321_PCI_UPPER_IO 0x9000ffff
#define IOP321_PCI_LOWER_MEM 0x80000000
#define IOP321_PCI_UPPER_MEM 0x83ffffff
#define IOP321_PCI_WINDOW_SIZE 64 * 0x100000
#define IOP321_PCI_IO_BASE 0x90000000
#define IOP321_PCI_IO_SIZE 0x00010000
#define IOP321_PCI_MEM_BASE 0x80000000
#define IOP321_PCI_MEM_SIZE 0x40000000
/*
* IOP321 chipset registers
*/
#define IOP321_VIRT_MEM_BASE 0xfff00000 /* chip virtual mem address*/
#define IOP321_VIRT_MEM_BASE 0xfeffe000 /* chip virtual mem address*/
//#define IOP321_VIRT_MEM_BASE 0xfff00000 /* chip virtual mem address*/
#define IOP321_PHY_MEM_BASE 0xffffe000 /* chip physical memory address */
#define IOP321_REG_ADDR(reg) (IOP321_VIRT_MEM_BASE | (reg))
......@@ -134,6 +140,16 @@
#define IOP321_OPHPR (volatile u32 *)IOP321_REG_ADDR(0x00000378)
#define IOP321_OPTPR (volatile u32 *)IOP321_REG_ADDR(0x0000037C)
#define IOP321_IAR (volatile u32 *)IOP321_REG_ADDR(0x00000380)
#define IOP321_IIxR_MASK 0x7f /* masks all */
#define IOP321_IIxR_IRI 0x40 /* RC Index Register Interrupt */
#define IOP321_IIxR_OFQF 0x20 /* RC Output Free Q Full (ERROR) */
#define IOP321_IIxR_ipq 0x10 /* RC Inbound Post Q (post) */
#define IOP321_IIxR_ERRDI 0x08 /* RO Error Doorbell Interrupt */
#define IOP321_IIxR_IDI 0x04 /* RO Inbound Doorbell Interrupt */
#define IOP321_IIxR_IM1 0x02 /* RC Inbound Message 1 Interrupt */
#define IOP321_IIxR_IM0 0x01 /* RC Inbound Message 0 Interrupt */
/* Reserved 0x00000384 through 0x000003FF */
/* DMA Controller 0x00000400 through 0x000004FF */
......@@ -186,10 +202,21 @@
#define IOP321_PBISR_BOOR_ERR 0x1
/* Peripheral performance monitoring unit 0x00000700 through 0x00077F */
#define IOP321_GTMR (volatile u32 *)IOP321_REG_ADDR(0x00000700)
#define IOP321_ESR (volatile u32 *)IOP321_REG_ADDR(0x00000704)
#define IOP321_EMISR (volatile u32 *)IOP321_REG_ADDR(0x00000708)
/* reserved 0x00000070c */
#define IOP321_GTSR (volatile u32 *)IOP321_REG_ADDR(0x00000710)
/* PERC0 DOESN'T EXIST - index from 1! */
#define IOP321_PERCR0 (volatile u32 *)IOP321_REG_ADDR(0x00000710)
#define IOP321_GTMR_NGCE 0x04 /* (Not) Global Counter Enable */
/* Peripheral performance monitoring unit 0x00000700 through 0x00077F */
/* Internal arbitration unit 0x00000780 through 0x0007BF */
#define IOP321_IACR (volatile u32 *)IOP321_REG_ADDR(0x00000780)
#define IOP321_MTTR1 (volatile u32 *)IOP321_REG_ADDR(0x00000784)
#define IOP321_MTTR2 (volatile u32 *)IOP321_REG_ADDR(0x00000788)
/* General Purpose I/O Registers */
#define IOP321_GPOE (volatile u32 *)IOP321_REG_ADDR(0x000007C4)
......@@ -207,6 +234,17 @@
#define IOP321_TU_TMR0 (volatile u32 *)IOP321_REG_ADDR(0x000007E0)
#define IOP321_TU_TMR1 (volatile u32 *)IOP321_REG_ADDR(0x000007E4)
#ifdef CONFIG_ARCH_IQ80321
#define IOP321_TICK_RATE 200000000 /* 200 MHz clock */
#elif defined(CONFIG_ARCH_IQ31244)
#define IOP321_TICK_RATE 198000000 /* 33.000 MHz crystal */
#endif
#ifdef CONFIG_ARCH_EP80219
#undef IOP321_TICK_RATE
#define IOP321_TICK_RATE 200000000 /* 33.333333 Mhz crystal */
#endif
#define IOP321_TMR_TC 0x01
#define IOP321_TMR_EN 0x02
#define IOP321_TMR_RELOAD 0x04
......@@ -224,15 +262,43 @@
#define IOP321_TU_TISR (volatile u32 *)IOP321_REG_ADDR(0x000007F8)
#define IOP321_TU_WDTCR (volatile u32 *)IOP321_REG_ADDR(0x000007FC)
/* Application accelerator unit 0x00000800 - 0x000008FF */
#define IOP321_AAU_ACR (volatile u32 *)IOP321_REG_ADDR(0x00000800)
#define IOP321_AAU_ASR (volatile u32 *)IOP321_REG_ADDR(0x00000804)
#define IOP321_AAU_ADAR (volatile u32 *)IOP321_REG_ADDR(0x00000808)
#define IOP321_AAU_ANDAR (volatile u32 *)IOP321_REG_ADDR(0x0000080C)
#define IOP321_AAU_SAR1 (volatile u32 *)IOP321_REG_ADDR(0x00000810)
/* SAR2...SAR32 0x00000814 - 0x000008A4 */
#define IOP321_AAU_SAR2 (volatile u32 *)IOP321_REG_ADDR(0x00000814)
#define IOP321_AAU_SAR3 (volatile u32 *)IOP321_REG_ADDR(0x00000818)
#define IOP321_AAU_SAR4 (volatile u32 *)IOP321_REG_ADDR(0x0000081C)
#define IOP321_AAU_SAR5 (volatile u32 *)IOP321_REG_ADDR(0x0000082C)
#define IOP321_AAU_SAR6 (volatile u32 *)IOP321_REG_ADDR(0x00000830)
#define IOP321_AAU_SAR7 (volatile u32 *)IOP321_REG_ADDR(0x00000834)
#define IOP321_AAU_SAR8 (volatile u32 *)IOP321_REG_ADDR(0x00000838)
#define IOP321_AAU_SAR9 (volatile u32 *)IOP321_REG_ADDR(0x00000840)
#define IOP321_AAU_SAR10 (volatile u32 *)IOP321_REG_ADDR(0x00000844)
#define IOP321_AAU_SAR11 (volatile u32 *)IOP321_REG_ADDR(0x00000848)
#define IOP321_AAU_SAR12 (volatile u32 *)IOP321_REG_ADDR(0x0000084C)
#define IOP321_AAU_SAR13 (volatile u32 *)IOP321_REG_ADDR(0x00000850)
#define IOP321_AAU_SAR14 (volatile u32 *)IOP321_REG_ADDR(0x00000854)
#define IOP321_AAU_SAR15 (volatile u32 *)IOP321_REG_ADDR(0x00000858)
#define IOP321_AAU_SAR16 (volatile u32 *)IOP321_REG_ADDR(0x0000085C)
#define IOP321_AAU_SAR17 (volatile u32 *)IOP321_REG_ADDR(0x00000864)
#define IOP321_AAU_SAR18 (volatile u32 *)IOP321_REG_ADDR(0x00000868)
#define IOP321_AAU_SAR19 (volatile u32 *)IOP321_REG_ADDR(0x0000086C)
#define IOP321_AAU_SAR20 (volatile u32 *)IOP321_REG_ADDR(0x00000870)
#define IOP321_AAU_SAR21 (volatile u32 *)IOP321_REG_ADDR(0x00000874)
#define IOP321_AAU_SAR22 (volatile u32 *)IOP321_REG_ADDR(0x00000878)
#define IOP321_AAU_SAR23 (volatile u32 *)IOP321_REG_ADDR(0x0000087C)
#define IOP321_AAU_SAR24 (volatile u32 *)IOP321_REG_ADDR(0x00000880)
#define IOP321_AAU_SAR25 (volatile u32 *)IOP321_REG_ADDR(0x00000888)
#define IOP321_AAU_SAR26 (volatile u32 *)IOP321_REG_ADDR(0x0000088C)
#define IOP321_AAU_SAR27 (volatile u32 *)IOP321_REG_ADDR(0x00000890)
#define IOP321_AAU_SAR28 (volatile u32 *)IOP321_REG_ADDR(0x00000894)
#define IOP321_AAU_SAR29 (volatile u32 *)IOP321_REG_ADDR(0x00000898)
#define IOP321_AAU_SAR30 (volatile u32 *)IOP321_REG_ADDR(0x0000089C)
#define IOP321_AAU_SAR31 (volatile u32 *)IOP321_REG_ADDR(0x000008A0)
#define IOP321_AAU_SAR32 (volatile u32 *)IOP321_REG_ADDR(0x000008A4)
#define IOP321_AAU_DAR (volatile u32 *)IOP321_REG_ADDR(0x00000820)
#define IOP321_AAU_ABCR (volatile u32 *)IOP321_REG_ADDR(0x00000824)
#define IOP321_AAU_ADCR (volatile u32 *)IOP321_REG_ADDR(0x00000828)
......@@ -260,4 +326,11 @@
/* for I2C bit defs see drivers/i2c/i2c-iop3xx.h */
#ifndef __ASSEMBLY__
extern void iop321_map_io(void);
extern void iop321_init_irq(void);
extern void iop321_time_init(void);
#endif
#endif // _IOP321_HW_H_
include/asm-arm/arch-iop3xx/iop331-irqs.h 0 → 100644
View file @ f35ece20
/*
* linux/include/asm-arm/arch-iop3xx/irqs.h
*
* Author: Dave Jiang (dave.jiang@intel.com)
* Copyright: (C) 2003 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef _IOP331_IRQS_H_
#define _IOP331_IRQS_H_
/*
* IOP80331 chipset interrupts
*/
#define IOP331_IRQ_OFS 0
#define IOP331_IRQ(x) (IOP331_IRQ_OFS + (x))
/*
* On IRQ or FIQ register
*/
#define IRQ_IOP331_DMA0_EOT IOP331_IRQ(0)
#define IRQ_IOP331_DMA0_EOC IOP331_IRQ(1)
#define IRQ_IOP331_DMA1_EOT IOP331_IRQ(2)
#define IRQ_IOP331_DMA1_EOC IOP331_IRQ(3)
#define IRQ_IOP331_RSVD_4 IOP331_IRQ(4)
#define IRQ_IOP331_RSVD_5 IOP331_IRQ(5)
#define IRQ_IOP331_AA_EOT IOP331_IRQ(6)
#define IRQ_IOP331_AA_EOC IOP331_IRQ(7)
#define IRQ_IOP331_TIMER0 IOP331_IRQ(8)
#define IRQ_IOP331_TIMER1 IOP331_IRQ(9)
#define IRQ_IOP331_I2C_0 IOP331_IRQ(10)
#define IRQ_IOP331_I2C_1 IOP331_IRQ(11)
#define IRQ_IOP331_MSG IOP331_IRQ(12)
#define IRQ_IOP331_MSGIBQ IOP331_IRQ(13)
#define IRQ_IOP331_ATU_BIST IOP331_IRQ(14)
#define IRQ_IOP331_PERFMON IOP331_IRQ(15)
#define IRQ_IOP331_CORE_PMU IOP331_IRQ(16)
#define IRQ_IOP331_RSVD_17 IOP331_IRQ(17)
#define IRQ_IOP331_RSVD_18 IOP331_IRQ(18)
#define IRQ_IOP331_RSVD_19 IOP331_IRQ(19)
#define IRQ_IOP331_RSVD_20 IOP331_IRQ(20)
#define IRQ_IOP331_RSVD_21 IOP331_IRQ(21)
#define IRQ_IOP331_RSVD_22 IOP331_IRQ(22)
#define IRQ_IOP331_RSVD_23 IOP331_IRQ(23)
#define IRQ_IOP331_XINT0 IOP331_IRQ(24)
#define IRQ_IOP331_XINT1 IOP331_IRQ(25)
#define IRQ_IOP331_XINT2 IOP331_IRQ(26)
#define IRQ_IOP331_XINT3 IOP331_IRQ(27)
#define IRQ_IOP331_RSVD_28 IOP331_IRQ(28)
#define IRQ_IOP331_RSVD_29 IOP331_IRQ(29)
#define IRQ_IOP331_RSVD_30 IOP331_IRQ(30)
#define IRQ_IOP331_RSVD_31 IOP331_IRQ(31)
#define IRQ_IOP331_XINT8 IOP331_IRQ(32) // 0
#define IRQ_IOP331_XINT9 IOP331_IRQ(33) // 1
#define IRQ_IOP331_XINT10 IOP331_IRQ(34) // 2
#define IRQ_IOP331_XINT11 IOP331_IRQ(35) // 3
#define IRQ_IOP331_XINT12 IOP331_IRQ(36) // 4
#define IRQ_IOP331_XINT13 IOP331_IRQ(37) // 5
#define IRQ_IOP331_XINT14 IOP331_IRQ(38) // 6
#define IRQ_IOP331_XINT15 IOP331_IRQ(39) // 7
#define IRQ_IOP331_RSVD_40 IOP331_IRQ(40) // 8
#define IRQ_IOP331_RSVD_41 IOP331_IRQ(41) // 9
#define IRQ_IOP331_RSVD_42 IOP331_IRQ(42) // 10
#define IRQ_IOP331_RSVD_43 IOP331_IRQ(43) // 11
#define IRQ_IOP331_RSVD_44 IOP331_IRQ(44) // 12
#define IRQ_IOP331_RSVD_45 IOP331_IRQ(45) // 13
#define IRQ_IOP331_RSVD_46 IOP331_IRQ(46) // 14
#define IRQ_IOP331_RSVD_47 IOP331_IRQ(47) // 15
#define IRQ_IOP331_RSVD_48 IOP331_IRQ(48) // 16
#define IRQ_IOP331_RSVD_49 IOP331_IRQ(49) // 17
#define IRQ_IOP331_RSVD_50 IOP331_IRQ(50) // 18
#define IRQ_IOP331_UART0 IOP331_IRQ(51) // 19
#define IRQ_IOP331_UART1 IOP331_IRQ(52) // 20
#define IRQ_IOP331_PBIE IOP331_IRQ(53) // 21
#define IRQ_IOP331_ATU_CRW IOP331_IRQ(54) // 22
#define IRQ_IOP331_ATU_ERR IOP331_IRQ(55) // 23
#define IRQ_IOP331_MCU_ERR IOP331_IRQ(56) // 24
#define IRQ_IOP331_DMA0_ERR IOP331_IRQ(57) // 25
#define IRQ_IOP331_DMA1_ERR IOP331_IRQ(58) // 26
#define IRQ_IOP331_RSVD_59 IOP331_IRQ(59) // 27
#define IRQ_IOP331_AA_ERR IOP331_IRQ(60) // 28
#define IRQ_IOP331_RSVD_61 IOP331_IRQ(61) // 29
#define IRQ_IOP331_MSG_ERR IOP331_IRQ(62) // 30
#define IRQ_IOP331_HPI IOP331_IRQ(63) // 31
#define NR_IOP331_IRQS (IOP331_IRQ(63) + 1)
#define NR_IRQS NR_IOP331_IRQS
/*
* Interrupts available on the IQ80331 board
*/
/*
* On board devices
*/
#define IRQ_IQ80331_I82544 IRQ_IOP331_XINT0
#define IRQ_IQ80331_UART0 IRQ_IOP331_UART0
#define IRQ_IQ80331_UART1 IRQ_IOP331_UART1
/*
* PCI interrupts
*/
#define IRQ_IQ80331_INTA IRQ_IOP331_XINT0
#define IRQ_IQ80331_INTB IRQ_IOP331_XINT1
#define IRQ_IQ80331_INTC IRQ_IOP331_XINT2
#define IRQ_IQ80331_INTD IRQ_IOP331_XINT3
#endif // _IOP331_IRQ_H_
include/asm-arm/arch-iop3xx/iop331.h 0 → 100644
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include/asm-arm/arch-iop3xx/iq31244.h 0 → 100644
View file @ f35ece20
/*
* linux/include/asm/arch-iop3xx/iq31244.h
*
* Intel IQ31244 evaluation board registers
*/
#ifndef _IQ31244_H_
#define _IQ31244_H_
#define IQ31244_RAMBASE 0xa0000000
#define IQ31244_FLASHBASE 0xf0000000 /* Flash */
#define IQ31244_FLASHSIZE 0x00800000
#define IQ31244_FLASHWIDTH 2
#define IQ31244_UART 0xfe800000 /* UART #1 */
#define IQ31244_7SEG_1 0xfe840000 /* 7-Segment MSB */
#define IQ31244_7SEG_0 0xfe850000 /* 7-Segment LSB (WO) */
#define IQ31244_ROTARY_SW 0xfe8d0000 /* Rotary Switch */
#define IQ31244_BATT_STAT 0xfe8f0000 /* Battery Status */
/*
* IQ31244 PCI I/O and Mem space regions
*/
#define IQ31244_PCI_IO_BASE 0x90000000
#define IQ31244_PCI_IO_SIZE 0x00010000
#define IQ31244_PCI_MEM_BASE 0x80000000
//#define IQ31244_PCI_MEM_SIZE 0x04000000
#define IQ31244_PCI_MEM_SIZE 0x08000000
#define IQ31244_PCI_IO_OFFSET 0x6e000000
#ifndef __ASSEMBLY__
extern void iq31244_map_io(void);
#endif
#endif // _IQ31244_H_
include/asm-arm/arch-iop3xx/iq80321.h
View file @ f35ece20
/*
* linux/include/asm/arch-iop3xx/iq80321.h
*
* Intel IQ-80321 evaluation board registers
* Intel IQ80321 evaluation board registers
*/
#ifndef _IQ80321_H_
#define _IQ80321_H_
#define IQ80321_RAMBASE 0xa0000000
#define IQ80321_UART1 0xfe800000 /* UART #1 */
#define IQ80321_7SEG_1 0xfe840000 /* 7-Segment MSB */
#define IQ80321_7SEG_0 0xfe850000 /* 7-Segment LSB (WO) */
#define IQ80321_ROTARY_SW 0xfe8d0000 /* Rotary Switch */
#define IQ80321_BATT_STAT 0xfe8f0000 /* Battery Status */
#define IQ80321_RAMBASE 0xa0000000
#define IQ80321_FLASHBASE 0xf0000000 /* Flash */
#define IQ80321_FLASHSIZE 0x00800000
#define IQ80321_FLASHWIDTH 1
#define IQ80321_UART 0xfe800000 /* UART #1 */
#define IQ80321_7SEG_1 0xfe840000 /* 7-Segment MSB */
#define IQ80321_7SEG_0 0xfe850000 /* 7-Segment LSB (WO) */
#define IQ80321_ROTARY_SW 0xfe8d0000 /* Rotary Switch */
#define IQ80321_BATT_STAT 0xfe8f0000 /* Battery Status */
/*
* IQ80321 PCI I/O and Mem space regions
*/
#define IQ80321_PCI_IO_BASE 0x90000000
#define IQ80321_PCI_IO_SIZE 0x00010000
#define IQ80321_PCI_MEM_BASE 0x80000000
#define IQ80321_PCI_MEM_SIZE 0x04000000
#define IQ80321_PCI_IO_OFFSET 0x6e000000
#ifndef __ASSEMBLY__
extern void iq80321_map_io(void);
#endif
#endif // _IQ80321_H_
include/asm-arm/arch-iop3xx/iq80331.h 0 → 100644
View file @ f35ece20
/*
* linux/include/asm/arch-iop3xx/iq80331.h
*
* Intel IQ80331 evaluation board registers
*/
#ifndef _IQ80331_H_
#define _IQ80331_H_
#define IQ80331_RAMBASE 0x00000000
#define IQ80331_FLASHBASE 0xc0000000 /* Flash */
#define IQ80331_FLASHSIZE 0x00800000
#define IQ80331_FLASHWIDTH 1
#define IQ80331_UART0_PHYS (IOP331_PHYS_MEM_BASE | 0x00001700) /* UART #1 physical */
#define IQ80331_UART1_PHYS (IOP331_PHYS_MEM_BASE | 0x00001740) /* UART #2 physical */
#define IQ80331_UART0_VIRT (IOP331_VIRT_MEM_BASE | 0x00001700) /* UART #1 virtual addr */
#define IQ80331_UART1_VIRT (IOP331_VIRT_MEM_BASE | 0x00001740) /* UART #2 virtual addr */
#define IQ80331_7SEG_1 0xce840000 /* 7-Segment MSB */
#define IQ80331_7SEG_0 0xce850000 /* 7-Segment LSB (WO) */
#define IQ80331_ROTARY_SW 0xce8d0000 /* Rotary Switch */
#define IQ80331_BATT_STAT 0xce8f0000 /* Battery Status */
/*
* IQ80331 PCI I/O and Mem space regions
*/
#define IQ80331_PCI_IO_BASE 0x90000000
#define IQ80331_PCI_IO_SIZE 0x00010000
#define IQ80331_PCI_MEM_BASE 0x80000000
#define IQ80331_PCI_MEM_SIZE 0x08000000
#define IQ80331_PCI_IO_OFFSET 0x6e000000
#ifndef __ASSEMBLY__
extern void iq80331_map_io(void);
#endif
#endif // _IQ80331_H_
include/asm-arm/arch-iop3xx/irqs.h
View file @ f35ece20
/*
* linux/include/asm-arm/arch-iop3xx/irqs.h
*
* Copyright: (C) 2001 MontaVista Software Inc.
* Copyright: (C) 2001-2003 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*
*/
#include <linux/config.h>
/*
* Whic iop3xx implementation is this?
* Chipset-specific bits
*/
#ifdef CONFIG_ARCH_IOP321
#include "iop321-irqs.h"
#endif
#ifdef CONFIG_ARCH_IOP331
#include "iop331-irqs.h"
#endif
include/asm-arm/arch-iop3xx/memory.h
View file @ f35ece20
......@@ -6,15 +6,19 @@
#define __ASM_ARCH_MEMORY_H
#include <linux/config.h>
#include <asm/arch/iop321.h>
#include <asm/hardware.h>
/*
* Physical DRAM offset.
*/
#ifndef CONFIG_ARCH_IOP331
#define PHYS_OFFSET (0xa0000000UL)
#else
#define PHYS_OFFSET (0x00000000UL)
#endif
/*
* Virtual view <-> DMA view memory address translations
* Virtual view <-> PCI DMA view memory address translations
* virt_to_bus: Used to translate the virtual address to an
* address suitable to be passed to set_dma_addr
* bus_to_virt: Used to convert an address for DMA operations
......@@ -25,6 +29,11 @@
#define __virt_to_bus(x) (((__virt_to_phys(x)) & ~(*IOP321_IATVR2)) | ((*IOP321_IABAR2) & 0xfffffff0))
#define __bus_to_virt(x) (__phys_to_virt(((x) & ~(*IOP321_IALR2)) | ( *IOP321_IATVR2)))
#elif defined(CONFIG_ARCH_IOP331)
#define __virt_to_bus(x) (((__virt_to_phys(x)) & ~(*IOP331_IATVR2)) | ((*IOP331_IABAR2) & 0xfffffff0))
#define __bus_to_virt(x) (__phys_to_virt(((x) & ~(*IOP331_IALR2)) | ( *IOP331_IATVR2)))
#endif
#define PFN_TO_NID(addr) (0)
......
include/asm-arm/arch-iop3xx/serial.h
View file @ f35ece20
......@@ -19,11 +19,58 @@
#define IRQ_UART1 IRQ_IQ80321_UART
#define RS_TABLE_SIZE 1
#define STD_SERIAL_PORT_DEFNS \
/* UART CLK PORT IRQ FLAGS */ \
{ 0, BASE_BAUD, 0xfe800000, IRQ_UART1, STD_COM_FLAGS }, /* ttyS0 */
#endif // CONFIG_ARCH_IQ80321
#ifdef CONFIG_ARCH_IQ31244
#define IRQ_UART1 IRQ_IQ31244_UART
#define RS_TABLE_SIZE 1
#define STD_SERIAL_PORT_DEFNS \
/* UART CLK PORT IRQ FLAGS */ \
{ 0, BASE_BAUD, 0xfe800000, IRQ_UART1, STD_COM_FLAGS }, /* ttyS0 */
#endif // CONFIG_ARCH_IQ31244
#ifdef CONFIG_ARCH_IQ80331
#undef BASE_BAUD
#define BASE_BAUD ( 33334000 / 16 )
#define IRQ_UART0 IRQ_IQ80331_UART0
#define IRQ_UART1 IRQ_IQ80331_UART1
#define RS_TABLE_SIZE 2
#define STD_SERIAL_PORT_DEFNS \
{ \
/*type: PORT_XSCALE,*/ \
/*xmit_fifo_size: 32,*/ \
baud_base: BASE_BAUD, \
irq: IRQ_UART0, \
flags: STD_COM_FLAGS, \
iomem_base: IQ80331_UART0_VIRT, \
io_type: SERIAL_IO_MEM, \
iomem_reg_shift: 2 \
}, /* ttyS0 */ \
{ \
/*type: PORT_XSCALE,*/ \
/*xmit_fifo_size: 32,*/ \
baud_base: BASE_BAUD, \
irq: IRQ_UART1, \
flags: STD_COM_FLAGS, \
iomem_base: IQ80331_UART1_VIRT, \
io_type: SERIAL_IO_MEM, \
iomem_reg_shift: 2 \
} /* ttyS1 */
#endif // CONFIG_ARCH_IQ80331
#define EXTRA_SERIAL_PORT_DEFNS
include/asm-arm/arch-iop3xx/system.h
View file @ f35ece20
......@@ -16,6 +16,14 @@ static inline void arch_idle(void)
static inline void arch_reset(char mode)
{
#ifdef CONFIG_ARCH_IOP321
*IOP321_PCSR = 0x30;
#endif
#ifdef CONFIG_ARCH_IOP331
*IOP331_PCSR = 0x30;
#endif
if ( 1 && mode == 's') {
/* Jump into ROM at address 0 */
cpu_reset(0);
......
include/asm-arm/arch-iop3xx/timex.h
View file @ f35ece20
......@@ -6,9 +6,13 @@
#include <linux/config.h>
#if defined(CONFIG_ARCH_IQ80321)
#if defined(CONFIG_ARCH_IQ80321) || defined(CONFIG_ARCH_IQ31244)
#define CLOCK_TICK_RATE 200000000
#define CLOCK_TICK_RATE IOP321_TICK_RATE
#elif defined(CONFIG_ARCH_IQ80331)
#define CLOCK_TICK_RATE IOP331_TICK_RATE
#else
......
include/asm-arm/arch-iop3xx/uncompress.h
View file @ f35ece20
......@@ -2,17 +2,25 @@
* linux/include/asm-arm/arch-iop3xx/uncompress.h
*/
#include <linux/config.h>
#include <asm/types.h>
#include <asm/mach-types.h>
#include <linux/serial_reg.h>
#include <asm/hardware.h>
#if defined(CONFIG_ARCH_IQ80321)
#define UART2_BASE ((volatile unsigned char *)IQ80321_UART1)
#ifdef CONFIG_ARCH_IOP321
#define UTYPE unsigned char *
#else
#define UTYPE u32 *
#endif
static volatile UTYPE uart_base;
#define TX_DONE (UART_LSR_TEMT|UART_LSR_THRE)
static __inline__ void putc(char c)
{
while ((UART2_BASE[5] & 0x60) != 0x60);
UART2_BASE[0] = c;
while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE);
*uart_base = c;
}
/*
......@@ -28,8 +36,20 @@ static void puts(const char *s)
}
}
static __inline__ void __arch_decomp_setup(unsigned long arch_id)
{
if(machine_is_iq80321())
uart_base = (volatile UTYPE)IQ80321_UART;
else if(machine_is_iq31244())
uart_base = (volatile UTYPE)IQ31244_UART;
else if(machine_is_iq80331())
uart_base = (volatile UTYPE)IQ80331_UART0_PHYS;
else
uart_base = (volatile UTYPE)0xfe800000;
}
/*
* nothing to do
*/
#define arch_decomp_setup()
#define arch_decomp_setup() __arch_decomp_setup(arch_id)
#define arch_decomp_wdog()
include/asm-arm/arch-iop3xx/vmalloc.h
View file @ f35ece20
......@@ -12,4 +12,5 @@
*/
#define VMALLOC_OFFSET (8*1024*1024)
#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
#define VMALLOC_VMADDR(x) ((unsigned long)(x))
#define VMALLOC_END (0xe8000000)
include/asm-arm/mach/pci.h
View file @ f35ece20
......@@ -56,6 +56,10 @@ extern int iop321_setup(int nr, struct pci_sys_data *);
extern struct pci_bus *iop321_scan_bus(int nr, struct pci_sys_data *);
extern void iop321_init(void);
extern int iop331_setup(int nr, struct pci_sys_data *);
extern struct pci_bus *iop331_scan_bus(int nr, struct pci_sys_data *);
extern void iop331_init(void);
extern int dc21285_setup(int nr, struct pci_sys_data *);
extern struct pci_bus *dc21285_scan_bus(int nr, struct pci_sys_data *);
extern void dc21285_preinit(void);
......
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