- 02 May, 2019 40 commits
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Anju T Sudhakar authored
Add PMU functions to support trace-imc. Signed-off-by:
Anju T Sudhakar <anju@linux.vnet.ibm.com> Reviewed-by:
Madhavan Srinivasan <maddy@linux.vnet.ibm.com> Signed-off-by:
Michael Ellerman <mpe@ellerman.id.au>
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Anju T Sudhakar authored
Patch detects trace-imc events, does memory initilizations for each online cpu, and registers cpuhotplug call-backs. Signed-off-by:
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Madhavan Srinivasan authored
Add code to restrict user access to thread_imc pmu since some event report privilege level information. Fixes: f74c89bd ("powerpc/perf: Add thread IMC PMU support") Signed-off-by:
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Anju T Sudhakar authored
LDBAR holds the memory address allocated for each cpu. For thread-imc the mode bit (i.e bit 1) of LDBAR is set to accumulation. Currently, ldbar is loaded with per cpu memory address and mode set to accumulation at boot time. To enable trace-imc, the mode bit of ldbar should be set to 'trace'. So to accommodate trace-mode of IMC, reposition setting of ldbar for thread-imc to thread_imc_event_add(). Also reset ldbar at thread_imc_event_del(). Signed-off-by:
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Anju T Sudhakar authored
Add the macros needed for IMC (In-Memory Collection Counters) trace-mode and data structure to hold the trace-imc record data. Also, add the new type "OPAL_IMC_COUNTERS_TRACE" in 'opal-api.h', since there is a new switch case added in the opal-calls for IMC. Signed-off-by:
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Anju T Sudhakar authored
The data structure (i.e struct imc_mem_info) to hold the memory address information for nest imc units is allocated based on the number of nodes in the system. nest_imc_event_init() traverse this struct array to calculate the memory base address for the event-cpu. If we fail to find a match for the event cpu's chip-id in imc_mem_info struct array, then the do-while loop will iterate until we crash. Fix this by changing the loop exit condition based on the number of non zero vbase elements in the array, since the allocation is done for nr_chips + 1. Reported-by:
Dan Carpenter <dan.carpenter@oracle.com> Fixes: 885dcd70 ("powerpc/perf: Add nest IMC PMU support") Signed-off-by:
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Anju T Sudhakar authored
Nest hardware counter memory resides in a per-chip reserve-memory. During nest_imc_event_init(), chip-id of the event-cpu is considered to calculate the base memory addresss for that cpu. Return, proper error condition if the chip_id calculated is invalid. Reported-by:
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Madhavan Srinivasan authored
PM_BR_CMPL_ALT event is not supported, remove it from the power9 event list. Fixes: 24bedcb7 ("powerpc/perf: Fix branch event code for power9") Signed-off-by:
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Madhavan Srinivasan authored
Most of the power processor generation performance monitoring unit (PMU) driver code is bundled in the kernel and one of those is enabled/registered based on the oprofile_cpu_type check at the boot. But things get little tricky incase of "compat" mode boot. IBM POWER System Server based processors has a compactibility mode feature, which simpily put is, Nth generation processor (lets say POWER8) will act and appear in a mode consistent with an earlier generation (N-1) processor (that is POWER7). And in this "compat" mode boot, kernel modify the "oprofile_cpu_type" to be Nth generation (POWER8). If Nth generation pmu driver is bundled (POWER8), it gets registered. Key dependency here is to have distro support for latest processor performance monitoring support. Patch here adds a generic "compat-mode" performance monitoring driver to be register in absence of powernv platform specific pmu driver. Driver supports only "cycles" and "instruction" events. "0x0001e" used as event code for "cycles" and "0x00002" used as event code for "instruction" events. New file called "generic-compat-pmu.c" is created to contain the driver specific code. And base raw event code format modeled on PPMU_ARCH_207S. Signed-off-by:
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Madhavan Srinivasan authored
Currenty pmu driver file for each ppc64 generation processor has a __init call in itself. Refactor the code by moving the __init call to core-books.c. This also clean's up compat mode pmu driver registration. Suggested-by:
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Joe Perches authored
Fix fallout too. Signed-off-by:
Joe Perches <joe@perches.com> Signed-off-by:
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Joel Stanley authored
Those not of us not drowning in POWER might not know what this means. Signed-off-by:
Joel Stanley <joel@jms.id.au> Acked-by:
Michael Neuling <mikey@neuling.org> Signed-off-by:
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Joel Stanley authored
It turns out that some defconfig changes and kernel config option changes meant we accidentally dropped Ethernet support for Mellanox CLX5 cards. Fixes: cbc39809 ("powerpc/configs: Update skiroot defconfig") Reported-by:
Carol L Soto <clsoto@us.ibm.com> Suggested-by:
Stewart Smith <stewart@linux.ibm.com> Signed-off-by:
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Mahesh Salgaonkar authored
On TOD/TB errors timebase register stops/freezes until HMI error recovery gets TOD/TB back into running state. On successful recovery, TB starts running again and udelay() that relies on TB value continues to function properly. But in case when HMI fails to recover from TOD/TB errors, the TB register stay freezed. With TB not running the __delay() function keeps looping and never return. If __delay() is called while in panic path then system hangs and never reboots after panic. Signed-off-by:
Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> Signed-off-by:
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Christopher M. Riedl authored
Operations which write to memory and special purpose registers should be restricted on systems with integrity guarantees (such as Secure Boot) and, optionally, to avoid self-destructive behaviors. Add a config option, XMON_DEFAULT_RO_MODE, to set default xmon behavior. The kernel cmdline options xmon=ro and xmon=rw override this default. The following xmon operations are affected: memops: disable memmove disable memset disable memzcan memex: no-op'd mwrite super_regs: no-op'd write_spr bpt_cmds: disable proc_call: disable Signed-off-by:
Christopher M. Riedl <cmr@informatik.wtf> Reviewed-by:
Oliver O'Halloran <oohall@gmail.com> Reviewed-by:
Andrew Donnellan <andrew.donnellan@au1.ibm.com> Signed-off-by:
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Bo YU authored
This is detected by Coverity scan: CID: 1440481 Signed-off-by:
Bo YU <tsu.yubo@gmail.com> Signed-off-by:
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Valentin Schneider authored
Since the enabling and disabling of IRQs within preempt_schedule_irq() is contained in a need_resched() loop, we don't need the outer arch code loop. Signed-off-by:
Valentin Schneider <valentin.schneider@arm.com> [mpe: Rebase since CURRENT_THREAD_INFO() removal] Signed-off-by:
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Horia Geantă authored
crypto node alias is needed by U-boot to identify the node and perform fix-ups, like adding "fsl,sec-era" property. Signed-off-by:
Horia Geantă <horia.geanta@nxp.com> Signed-off-by:
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Christophe Leroy authored
PROM_SCRATCH_SIZE is same as sizeof(prom_scratch) Signed-off-by:
Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by:
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Michael Ellerman authored
This can be helpful for debugging problems with the security feature flags, especially on guests where the flags come from the hypervisor via an hcall and so can't be observed in the device tree. Signed-off-by:
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Russell Currey authored
Implement code to walk all pages and warn if any are found to be both writable and executable. Depends on STRICT_KERNEL_RWX enabled, and is behind the DEBUG_WX config option. This only runs on boot and has no runtime performance implications. Very heavily influenced (and in some cases copied verbatim) from the ARM64 code written by Laura Abbott (thanks!), since our ptdump infrastructure is similar. Signed-off-by:
Russell Currey <ruscur@russell.cc> [mpe: Fixup build error when disabled] Signed-off-by:
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Russell Currey authored
Lovingly borrowed from the arch/arm64 ptdump code. This doesn't seem to be an issue in practice, but is necessary for my upcoming commit. Signed-off-by:
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Christoph Hellwig authored
This export was added in this merge window, but without any actual user, or justification for a modular user. Fixes: a35a3c6f ("powerpc/mm/hash64: Add a variable to track the end of IO mapping") Signed-off-by:
Christoph Hellwig <hch@lst.de> Signed-off-by:
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Andrew Donnellan authored
Use my @linux.ibm.com email to avoid a layer of redirection. Signed-off-by:
Andrew Donnellan <ajd@linux.ibm.com> Signed-off-by:
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Nicholas Piggin authored
"Reconciling" in terms of interrupt handling, is to bring the soft irq mask state in to synch with the hardware, after an interrupt causes MSR[EE] to be cleared (while the soft mask may be enabled, and hard irqs not marked disabled). General kernel code should not be called while unreconciled, because local_irq_disable, etc. manipulations can cause surprising irq traces, and it's fragile because the soft irq code does not really expect to be called in this situation. When exiting from an interrupt, MSR[EE] is cleared to prevent races, but soft irq state is enabled for the returned-to context, so this is now an unreconciled state. restore_math is called in this state, and that can be ftraced, and the ftrace subsystem disables local irqs. Mark restore_math and its callees as notrace. Restore a sanity check in the soft irq code that had to be disabled for this case, by commit 4da1f792 ("powerpc/64: Disable irq restore warning for now"). Signed-off-by:
Nicholas Piggin <npiggin@gmail.com> Signed-off-by:
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Christophe Leroy authored
This patch drops__irq_offset_value which has not been used since commit 9c4cb825 ("powerpc: Remove use of CONFIG_PPC_MERGE") This removes a sparse warning. Fixes: 9c4cb825 ("powerpc: Remove use of CONFIG_PPC_MERGE") Signed-off-by:
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Christophe Leroy authored
Compared to ifdefs, IS_ENABLED() provide a cleaner code and allows to detect compilation failure regardless of the selected options. Signed-off-by:
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Christophe Leroy authored
Use cpu_has_feature() instead of opencoding Use IS_ENABLED() instead of #ifdef for CONFIG_TAU_AVERAGE Signed-off-by:
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Christophe Leroy authored
Use IS_ENABLED() instead of #ifdefs Signed-off-by:
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Christophe Leroy authored
CPU_FTR_ALTIVEC is only set when CONFIG_ALTIVEC is selected, so the ifdef is unnecessary. Signed-off-by:
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Christophe Leroy authored
To avoid ifdefs, define a empty static inline mm_iommu_init() function when CONFIG_SPAPR_TCE_IOMMU is not selected. Signed-off-by:
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Christophe Leroy authored
To avoid #ifdefs, define an static inline fadump_cleanup() function when CONFIG_FADUMP is not selected Signed-off-by:
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Christophe Leroy authored
No need to add dummy frames when calling trace_hardirqs_on or trace_hardirqs_off. GCC properly handles empty stacks. In addition, powerpc doesn't set CONFIG_FRAME_POINTER, therefore __builtin_return_address(1..) returns NULL at all time. So the dummy frames are definitely unneeded here. In the meantime, avoid reading memory for loading r1 with a value we already know. Signed-off-by:
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Christophe Leroy authored
As syscalls are now handled via a fast entry path, syscall related actions can be removed from the generic transfer_to_handler path. Signed-off-by:
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Christophe Leroy authored
This patch implements a fast entry for syscalls. Syscalls don't have to preserve non volatile registers except LR. This patch then implement a fast entry for syscalls, where volatile registers get clobbered. As this entry is dedicated to syscall it always sets MSR_EE and warns in case MSR_EE was previously off It also assumes that the call is always from user, system calls are unexpected from kernel. Signed-off-by:
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Christophe Leroy authored
This patch implements a fast entry for syscalls. Syscalls don't have to preserve non volatile registers except LR. This patch then implement a fast entry for syscalls, where volatile registers get clobbered. As this entry is dedicated to syscall it always sets MSR_EE and warns in case MSR_EE was previously off It also assumes that the call is always from user, system calls are unexpected from kernel. The overall series improves null_syscall selftest by 12,5% on an 83xx and by 17% on a 8xx. Signed-off-by:
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Christophe Leroy authored
[text mostly copied from benh's RFC/WIP] ppc32 are still doing something rather gothic and wrong on 32-bit which we stopped doing on 64-bit a while ago. We have that thing where some handlers "copy" the EE value from the original stack frame into the new MSR before transferring to the handler. Thus for a number of exceptions, we enter the handlers with interrupts enabled. This is rather fishy, some of the stuff that handlers might do early on such as irq_enter/exit or user_exit, context tracking, etc... should be run with interrupts off afaik. Generally our handlers know when to re-enable interrupts if needed. The problem we were having is that we assumed these interrupts would return with interrupts enabled. However that isn't the case. Instead, this patch changes things so that we always enter exception handlers with interrupts *off* with the notable exception of syscalls which are special (and get a fast path). Suggested-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by:
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Christophe Leroy authored
EXC_XFER_TEMPLATE() is not called with COPY_EE anymore so we can get rid of copyee parameters and related COPY_EE and NOCOPY macros. Suggested-by:
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Christophe Leroy authored
All exceptions handlers know when to reenable interrupts, so it is safer to enter all of them with MSR_EE unset, except for syscalls. Suggested-by:
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Christophe Leroy authored
syscalls are expected to be entered with MSR_EE set. Lets make it inconditional by forcing MSR_EE on syscalls. This patch adds EXC_XFER_SYS for that. Suggested-by:
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