- 09 Apr, 2020 32 commits
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Nicholas Kazlauskas authored
[Why] Cursor pos is correctly adjusted from DC side for source rect offset on DCN ASIC, but only on the overlay. This is because DM places offsets the cursor for primary planes only to workaround missing code in DCE for the adjustment we're now correctly doing in DC for DCN ASIC. [How] Drop the adjustment for source rect from the DM side of things and put the code where it actually belongs - in DC on the pipe level. This matches what we do for DCN now. Signed-off-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by:
Zhan Liu <Zhan.Liu@amd.com> Acked-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Eric Yang authored
[Why] Changing policy to dynamic will allow 4k multi display configs to be supported at DPM0 Signed-off-by:
Eric Yang <Eric.Yang2@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Nicholas Kazlauskas authored
[Why] Cursor is drawn as part of the framebuffer for a plane on AMD hardware. The cursor position on the framebuffer does not change even if the source rect viewport for the cursor does. This causes the cursor to be clipped. The following IGT tests fail as a result of this issue: - kms_plane_cursor@pipe-*-viewport-size-* [How] Offset cursor position by plane source rect viewport. If the viewport is unscaled then the cursor is now correctly positioned on any plane - primary or overlay. There is still a hardware limitation for dealing with the cursor size being incorrectly scaled but that's not something we can address. Add some documentation explaining some of this in the code while we're at it. Signed-off-by:
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Wyatt Wood authored
Decouple dmcub config copy from dmcu iram copy. Signed-off-by:
Wyatt Wood <wyatt.wood@amd.com> Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Xiaodong Yan authored
[why] blank all dp stream would impact edp [how] only blank the one which will be powered off Signed-off-by:
Xiaodong Yan <Xiaodong.Yan@amd.com> Reviewed-by:
Yongqiang Sun <yongqiang.sun@amd.com> Acked-by:
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Joseph Gravenor authored
[why] MOD_HDCP_STATUS_HDCP1_ENABLE_ENCRYPTION and MOD_HDCP_STATUS_HDCP2_ENABLE_ENCRYPTION were supposed to be MOD_HDCP_STATUS_HDCP1_ENABLE_ENCRYPTION_FAILURE and MOD_HDCP_STATUS_HDCP2_ENABLE_ENCRYPTION_FAILURE. Because of this it always seems like mod_hdcp_hdcp1_enable_encryption and mod_hdcp_hdcp2_enable_encryption are always passing [how] rename the elements to what they were supposed to be called Signed-off-by:
Joseph Gravenor <joseph.gravenor@amd.com> Reviewed-by:
Wenjing Liu <Wenjing.Liu@amd.com> Acked-by:
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Wyatt Wood authored
[Why] When dmcub is the default we no longer wish to create the psr and dmcu objects. Currently a dc debug flag is used to implement this, but these flags aren't populated until after dcn21_resource_construct is called. This means the dmcub objects will never be created. Therefore we must use a dc config flag, which is populated before dc resource construct. [How] Add a dc config flag. Signed-off-by:
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Sung Lee authored
[WHY] The power_down() function was only defined for specific asics and will crash the system if it is called by an asic with eDP connected that does not have it defined. [HOW] Add a check for the function's existence before calling it. Signed-off-by:
Sung Lee <sung.lee@amd.com> Reviewed-by:
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Nicholas Kazlauskas authored
[Why] Overlay planes disappear when the plane's alpha blending mode or global opacity is modified. These are considered UPDATE_TYPE_MEDIUM and trigger the update_mpcc path in the DCN hardware sequencer. On DCN10 we have an "optimization" to avoid touching the blending tree on these updates, but this is actually required behavior based on how update_mpcc is structured. For full updates we acquire a MPCC for the plane, remove it if it already exists then reinsert it after with insert_plane. The call to insert_plane can take an optional mpcc to insert the new one above to preserve the current blending order. The update_mpcc hwseq function doesn't do this so the overlay gets sent to the very bottom of the tree. [How] Copy the check over from DCN10 to DCN20. The only time we need to actually touch the tree really is the full update, so this is also an optimization on top of the fix. Fixing the logic for insert_plane is rather simple (cache the bot_mpcc and pass it to insert_plane) but is a change that impacts most display usecases. For now stick with the optimization. Signed-off-by:
Chris Park <Chris.Park@amd.com> Acked-by:
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Xiaodong Yan authored
[why] power off dp receiver directly cause garbage during hw init [how] blank dp stream and then power off receiver Signed-off-by:
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Sung Lee authored
[WHY] On headless boot a DIG may be turned on by VBIOS on RN. This leads to display_count being non-zero in hybrid graphics cases leading to SMU DISPLAY_OFF message not being sent. [HOW] Power down hardware on boot if seamless boot is not occurring (power_down_display_on_boot == 1) Signed-off-by:
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Isabel Zhang authored
[Why] Due to previous code changes, displays transition from active to active and added state immediately, making it redundant to have both display states. Previous change to fix this caused HDCP to get into a bad state when monitor is connected to MST hub, this change fixes that issue. [How] Change code behavior so when a device is added successfully the state remains as active and when addition is unsuccessful change state to inactive. This removes need for added and active state. Signed-off-by:
Isabel Zhang <isabel.zhang@amd.com> Reviewed-by:
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Wyatt Wood authored
[Why] Driver must pass abm config table to dmub fw. This provides various parameters for abm functionality. [How] There is too much data to be passed in an inbox message, so we must pass this data using an indirect buffer. Copy the table to cw7 via x86, driver copies to fw_state structure. Signed-off-by:
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Nikola Cornij authored
[why] Link or DIG BE can't be exposed to a higher stream bandwidth than they can handle. When DSC is required to fit the stream into the link bandwidth, DSC has to be programmed before the link is enabled to ensure this. Without it, intermittent issues such as black screen after S3 or a hot-plug can be seen with DSC timings like 4k144Hz or 8k60Hz. [how] Move DSC programming from before enabling stream to before enabling link Signed-off-by:
Nikola Cornij <nikola.cornij@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Josip Pavic authored
[Why] If no free pipes are available, acquire_first_split_pipe is called to get a pipe to use. This call may alter the ordering of the pipes in the list so that, for example, the tail pipe changes. If acquire_first_split_pipe returns the tail pipe, we'll have free_pipe == tail_pipe. What tail_pipe refers to is not the current tail_pipe, but what was previously the tail pipe - i.e. prior to the call to acquire_first_split_pipe The logic that follows will link free_pipe to the tail pipe, referring to the current tail pipe. However, since tail_pipe is cached from before the call to acquire_first_split_pipe, the wrong tail pipe will be used, and it will end up being linked to itself, creating a loop that, if traversed, will result in a soft hang. [How] Do not cache the tail pipe. Instead, check the tail pipe after the call to acquire_first_split_pipe is made. Signed-off-by:
Josip Pavic <Josip.Pavic@amd.com> Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
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Aric Cyr authored
Signed-off-by:
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Jack Zhang authored
[PATCH 2/2] kfd_pre_reset will free mem_objs allocated by kfd_gtt_sa_allocate Without this change, sriov tdr code path will never free those allocated memories and get memory leak. Signed-off-by:
Jack Zhang <Jack.Zhang1@amd.com> Reviewed-by:
Monk Liu <monk.liu@amd.com> Signed-off-by:
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Jack Zhang authored
This reverts commit 5161bba4311f in order to split it into two different patches, and this will make it easier to understand. [PATCH 1/2] porting to gfx10 from commit 1b0bfcff ("drm/amdgpu: Avoid destroy hqd when GPU is on reset") Originally, MEC is touched without GPU initialized first. Signed-off-by:
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John Clements authored
prefix RAS error related dmesg print with pci device info Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
John Clements <john.clements@amd.com> Signed-off-by:
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John Clements authored
upon receiving uncorrectable error, query every GPU node for ras errors Reviewed-by:
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Chengming Gui authored
Incorrect CG sequence will cause gfx timedout, if we keep switching power profile mode (enter profile mod such as PEAK will disable CG, exit profile mode EXIT will enable CG) when run Vulkan test case(case used for test: vkexample). Signed-off-by:
Chengming Gui <Jack.Gui@amd.com> Reviewed-by:
Kenneth Feng <kenneth.feng@amd.com> Acked-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Tianci.Yin authored
Add RLC_SPM golden settings Reviewed-by:
Tianci.Yin <tianci.yin@amd.com> Signed-off-by:
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Tianci.Yin authored
Add RLC_SPM golden settings Reviewed-by:
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Tianci.Yin authored
Add RLC_SPM golden settings Reviewed-by:
Feifei Xu <Feifei.Xu@amd.com> Signed-off-by:
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Oak Zeng authored
UTCL2 client ID is useful information to get which UTCL2 client caused the gpuvm fault. Print it out for debug purpose Signed-off-by:
Oak Zeng <Oak.Zeng@amd.com> Reviewed-by:
Christian Konig <christian.koenig@amd.com> Signed-off-by:
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Nirmoy Das authored
Util -> Until Fixes: 567c8fc4 ("drm/amd/powerplay: implement the is_dpm_running()") Signed-off-by:
Nirmoy Das <nirmoy.das@amd.com> Reviewed-by:
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James Zhu authored
VCN shared memory needs restore after wake up during S3 test. v2: Allocate shared memory saved_bo at sw_init and free it in sw_fini. Signed-off-by:
James Zhu <James.Zhu@amd.com> Reviewed-by:
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Aaron Ma authored
On ARCTURUS and RENOIR, powerplay is not supported yet. When plug in or unplug power jack, ACPI event will issue. Then kernel NULL pointer BUG will be triggered. Check for NULL pointers before calling. Signed-off-by:
Aaron Ma <aaron.ma@canonical.com> Signed-off-by:
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Alex Deucher authored
Replace dev_warn() with dev_info() and note that they are optional to avoid confusing users. The RAS TAs only exist on server boards and the HDCP and DTM TAs only exist on client boards. They are optional either way. Acked-by:
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Nirmoy Das authored
Generate HW IP's sched_list in amdgpu_ring_init() instead of amdgpu_ctx.c. This makes amdgpu_ctx_init_compute_sched(), ring.has_high_prio and amdgpu_ctx_init_sched() unnecessary. This patch also stores sched_list for all HW IPs in one big array in struct amdgpu_device which makes amdgpu_ctx_init_entity() much more leaner. v2: fix a coding style issue do not use drm hw_ip const to populate amdgpu_ring_type enum v3: remove ctx reference and move sched array and num_sched to a struct use num_scheds to detect uninitialized scheduler list v4: use array_index_nospec for user space controlled variables fix possible checkpatch.pl warnings Signed-off-by:
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Nirmoy Das authored
Use AMDGPU_HW_IP_* to set amdgpu_ring_type enum values Signed-off-by:
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Jack Zhang authored
kfd_pre_reset will free mem_objs allocated by kfd_gtt_sa_allocate Without this change, sriov tdr code path will never free those allocated memories and get memory leak. v2:add a bugfix for kiq ring test fail Signed-off-by:
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- 03 Apr, 2020 8 commits
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Yifan Zhang authored
Add missing braces. Signed-off-by:
Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by:
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Tiecheng Zhou authored
hwmgr->pm_en is initialized at hwmgr_hw_init. during amdgpu_device_init, there is amdgpu_asic_reset that calls to pp_get_asic_baco_capability, while hwmgr->pm_en has not yet been initialized. so avoid using pm_en in pp_get_asic_baco_capability. Reviewed-by:
Emily Deng <Emily.Deng@amd.com> Signed-off-by:
Tiecheng Zhou <Tiecheng.Zhou@amd.com> Signed-off-by:
Yintian Tao <yttao@amd.com> Signed-off-by:
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Prike Liang authored
As the pmfw hasn't exported the interface of SMU feature mask to APU SKU so just force on all the features to driver inquired interface at early initial stage. Signed-off-by:
Prike Liang <Prike.Liang@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Shirish S authored
Fixes build error of: "use of undeclared identifier 'RENOIR_A0'" To fix the same, this patch re-orders the ASIC declarations accordingly. Fixes: 41ef3dcd ("drm/amd/display: Fix RV2 Variant Detection") Signed-off-by:
Shirish S <shirish.s@amd.com> Reviewed-by:
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Yuxian Dai authored
1.Using the FCLK DPM table to set the MCLK for DPM states consist of three entities: FCLK UCLK MEMCLK All these three clk change together, MEMCLK from FCLK, so use the fclk frequency. 2.we should show the current working clock freqency from clock table metric Signed-off-by:
Yuxian Dai <Yuxian.Dai@amd.com> Reviewed-by:
Kevin Wang <Kevin1.Wang@amd.com> Signed-off-by:
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Alex Sierra authored
Navi ASICs don't require to access through PSP to osssys registers. This on SR-IOV configuration. Signed-off-by:
Alex Sierra <alex.sierra@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Bhawanpreet Lakha authored
[Why] The buffer used when calling psp is a shared buffer. If we have multiple calls at the same time we can overwrite the buffer. [How] Add mutex to guard the shared buffer. Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by:
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Bhawanpreet Lakha authored
It is not being used, so remove it Signed-off-by:
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