- 23 Nov, 2016 16 commits
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Alex Deucher authored
UVD 5 and newer do not have the same placement limitations as older chips, so skip the first pass since it's just overhead on chips where we don't have to force placement. v2: fix inverted logic Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Same code duplicated in both functions. Reviewed-by:
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Trigger Huang authored
This patch is used for virtualization support. In virtualization, only SMU manager is needed, DPM should be disabled. This is a use case for commit 2f9346b6f984 ("drm/amdgpu/powerplay: pp module only enable smu when dpm disabled.") Signed-off-by:Trigger Huang <trigger.huang@amd.com> Reviewed-by:
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Christian König authored
Doesn't make much sense to have the same functionality twice. v2: rebase on dma_fence renaming Signed-off-by:
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Christian König authored
Drop this whole reserve/unreserve dance, just lock the reservation object manually when creating the BO. v2: rebase on dma_fence renaming Signed-off-by:
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Christian König authored
Manually checking why a function could fail is not a good idea if you can just check the functions return code. Signed-off-by:
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Christian König authored
The mem start is relative to the domain in the address space, so this worked only when VRAM was mapped at offset 0. It also didn't handled multiple drm_mm_nodes for split VRAM. v2: rebase on dma_fence renaming Signed-off-by:
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Christian König authored
Not used any more. Signed-off-by:
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Edward O'Callaghan authored
It can be the case that upon GPU page faults we start trashing the logs, and so let us ratelimit here to avoid that. V2. Fix issue where calling dev_err_ratelimited separately for each line means that some lines corresponding to a single VM fault may or may not appear depending on the rate. - Michel Dänzer. Reviewed-by: Christian König <christian.koenig@amd.com> (v1) Signed-off-by:Edward O'Callaghan <funfunctor@folklore1984.net> Signed-off-by:
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Edward O'Callaghan authored
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Tom St Denis authored
Port of SI DCE v6 over to new AMDGPU headers. Tested on a Tahiti with GNOME through various hot plugs/rotations/sizes/fullscreen/windowed and staging drm/xf86-video-amdgpu. (v2) Re-factored to remove formatting changes to si_enums.h as well rename various defines. (v3) Rebase on upstream Signed-off-by:Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
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Huang Rui authored
Signed-off-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
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Huang Rui authored
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Monk Liu authored
when shadowing enabled, tesselation app will trigger vm fault because below three tesselation registers: VGT_TF_RING_SIZE__CI__VI, VGT_HS_OFFCHIP_PARAM__CI__VI, VGT_TF_MEMORY_BASE__CI__VI, need to be programed after vgt-flush. Tesselation picture vm fault disappeared after vgt-flush introduced. v2:implement vgt-flush for CI & SI. v3:move vgt flush inside of cntx_cntrl v4:count vgt flush in frame_size v5:squash in typo fix Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Reviewed-by:
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Rex Zhu authored
Signed-off-by:
Rex Zhu <Rex.Zhu@amd.com> Reviewed-by:
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Rex Zhu authored
sw clockgate was used on uvd6.0. when uvd is idle, we gate the uvd clock. when decode, we ungate the uvd clock. Signed-off-by:
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- 15 Nov, 2016 3 commits
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Rex Zhu authored
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Rex Zhu authored
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Alex Deucher authored
Use the correct define. No functional change as both defines are equivalent. Reviewed-by:
Chunming Zhou <david1.zhou@amd.com> Reviewed-by:
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- 11 Nov, 2016 21 commits
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Tom St Denis authored
Port the GMC v6 driver over to the new SI headers. Tested with a Tahiti SI ASIC. (v2) Fixed a couple of typos (in commented code) and moved defines to si_enums.h Signed-off-by: -
Rex Zhu authored
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Christian König authored
This only has the effect of scanning the invisible range twice since the topdown flag is given anyway. Signed-off-by:
JimQu <Jim.Qu@amd.com> Signed-off-by:
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Christian König authored
This disables the VRAM manager when a special placement is requested, otherwise we play ping/pong with the buffers on every command submission. v2: only check lpfn Signed-off-by:
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Rex Zhu authored
1. fix uvd cg status not correct. 2. fix uvd pg can't work on tonga. 3. enable uvd mgcg. Signed-off-by:
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Rex Zhu authored
when uvd is idle, we gate uvd clock. and uvd is busy, we ungate uvd clock. Reviewed-by:
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Rex Zhu authored
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Tom St Denis authored
Add support for the debugfs wave reader. Signed-off-by:
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Tom St Denis authored
This changes the gfx v6 driver to use the new AMDGPU style SI headers. Also fixes a variety of coding style issues, white space issues, and uses WREG32_FIELD in a few places where appropriate. Tested with a Tahiti 0x679A. v2: Squash in typo fix patch Signed-off-by:
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Tom St Denis authored
Add missing gca MMIO registers and defines necessary for the next patch which re-works a lot of gfx v6 to use the new SI headers. Signed-off-by:
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Tom St Denis authored
This introduces the SI registers in the amdgpu driver style. v2: squash duplicates fix Signed-off-by:
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Ravikant B Sharma authored
Replace direct comparisons to NULL i.e. 'x == NULL' with '!x'. As per coding standard. Reviewed-by:
Ravikant B Sharma <ravikant.s2@samsung.com> Signed-off-by:
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Tom St Denis authored
De-numberify indirect register access for gfx v8. Signed-off-by:
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Tom St Denis authored
De-numberify indirect register access for gfx v7. Signed-off-by:
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jimqu authored
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Trigger Huang authored
This patch is used for virtualization support. In virtualization case, Tonga SMC should not be started and SMU firmware should not be loaded if in SRIOV environment. The same operation will be applied on FIJI in other patch. Signed-off-by:
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Rex Zhu authored
1. partial revert commit 91db308d6e96. not set uvd bypass mode. 2. enable uvd cg before initialize uvd. 3. set uvd clock to default value 100MHz. Signed-off-by:
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Rex Zhu authored
Voltage Controller have been enabled (SMC message) before ULV enablement. Reviewed-by:
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Rex Zhu authored
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Rex Zhu authored
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Rex Zhu authored
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