- 02 Apr, 2013 12 commits
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Bastian Hecht authored
With the added capabilty of the intc_irqpin driver to handle shared external IRQs, all prerequisites are fulfilled and we are ready to migrate completely to GIC. This includes the following steps: - Kconfig: select ARM_GIC and RENESAS_INTC_IRQPIN - intc-r8a7740: Throw out all legacy INTC code and init the GIC. We need to mask out all shared IRQs as it is needed by the shared intc_irqpin driver. - setup-r8a7740: Add 4 irqpin devices to handle external IRQs and update all IRQ numbers to point to the GIC SPI. - board-armadillo: Update all IRQ numbers to point to the GIC SPI. - pfc-r8a7740: Update all IRQ numbers of the GPIOs to point to the GIC SPI. Signed-off-by:
Bastian Hecht <hechtb+renesas@gmail.com> Acked-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Kuninori Morimoto authored
You can get current thermal by > cat /sys/class/thermal/thermal_zone?/temp Signed-off-by:
Magnus Damm <damm@opensource.se> Signed-off-by:
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Magnus Damm authored
Modify mach-shmobile to only select PINCTRL in case of ARCH_WANT_OPTIONAL_GPIOLIB is set. This fixes a build error triggered when adding a new SoC lacking GPIO software support (ARCH_WANT_OPTIONAL_GPIOLIB=n): CC drivers/tty/vt/keyboard.o In file included from drivers/pinctrl/core.c:30:0: include/asm-generic/gpio.h: In function 'gpio_get_value_cansleep': include/asm-generic/gpio.h:270:2: error: implicit declaration of function '__gpio_get_value' include/asm-generic/gpio.h: In function 'gpio_set_value_cansleep': include/asm-generic/gpio.h:276:2: error: implicit declaration of function '__gpio_set_value' drivers/pinctrl/core.c: In function 'pinctrl_ready_for_gpio_range': drivers/pinctrl/core.c:297:9: error: implicit declaration of function 'gpio_to_chip' drivers/pinctrl/core.c:297:27: warning: initialization makes pointer from integer without a cast drivers/pinctrl/core.c:304:45: error: dereferencing pointer to incomplete type drivers/pinctrl/core.c:305:26: error: dereferencing pointer to incomplete type drivers/pinctrl/core.c:305:39: error: dereferencing pointer to incomplete type make[2]: *** [drivers/pinctrl/core.o] Error 1 make[1]: *** [drivers/pinctrl] Error 2 make[1]: *** Waiting for unfinished jobs.... LD drivers/sh/built-in.o Signed-off-by:
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Guennadi Liakhovetski authored
Add DT nodes for the 4 irqpin interrupt controllers on sh73a0. We add them to sh73a0.dtsi, which is also used by configurations, doing all their device instantiation from board the .c code. We rely on the fact, that such configurations don't instantiate devices from the device-tree. Signed-off-by:
Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by:
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Kuninori Morimoto authored
Add SCIF serial port support to the r8a7778 SoC by adding platform devices together with clock bindings. DT device description is excluded at this point since such bindings are still under development. Signed-off-by:
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Kuninori Morimoto authored
Add initial support for the R8A7778 R-Car M1A SoC. No static virtual mappings are used, all the components make use of ioremap(). DT_MACHINE_START is still wrapped in CONFIG_USE_OF to match other mach-shmobile code. It is based on v1.0 datasheet Signed-off-by:
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Guennadi Liakhovetski authored
To reconfigure clocks, controlled by FRQCRA and FRQCRB, a kick bit has to be set and to make sure the setting has taken effect, it has to be read back repeatedly until it is cleared by the hardware. This patch adds the waiting part, that was missing until now. Signed-off-by:
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Magnus Damm authored
Add a platform device for the r8a73a4 PFC. Signed-off-by:
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Magnus Damm authored
Add IRQC interrupt controller support to r8a73a4 by hooking up two IRQC instances to handle 58 external IRQ signals. There IRQC controllers are tied to SPIs of the GIC. On r8a73a4 exact IRQ pin routing is handled by the PFC which is excluded from this patch. Both platform devices and DT devices are added in this patch. The platform device versions are used to provide a static interrupt map configuration for board code written in C. Signed-off-by:
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Magnus Damm authored
V3 of SCIF serial port support for the r8a73a4 SoC. This is done by adding platform devices for SCIFA0 -> SCIFA1 as well as SCIFB0 -> SCIFB3 together with clock bindings. DT device description is excluded at this point since such bindings are still under development. Signed-off-by:
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Magnus Damm authored
V3 of initial support for the r8a73a4 SoC including: - Single Cortex-A15 CPU Core - GIC - Architecture timer No static virtual mappings are used, all the components make use of ioremap(). DT_MACHINE_START is still wrapped in CONFIG_USE_OF to match other mach-shmobile code. Signed-off-by:
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Simon Horman authored
Update for Renesas INTC External IRQ pin driver for v3.10 This adds support for shared interrupt lines to the Renesas INTC External IRQ pin driver which has already been queued up for v3.10 (tag renesas-intc-external-irq-for-v3.10). The patch "irqchip: intc-irqpin: Add support for shared interrupt lines" in renesas-intc-external-irq2-for-v3.10 is a dependency for "ARM: shmobile: r8a7740: Migrate from INTC to GIC". That dependency is the reason for this merge.
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- 28 Mar, 2013 1 commit
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Bastian Hecht authored
On some hardware we don't have a 1-1 mapping from the external interrupts coming from INTC to the GIC SPI pins. We can however share lines to demux incoming IRQs on these SoCs. This patch enables the intc_irqpin driver to detect requests for shared interrupt lines and demuxes them properly by querying the INTC INTREQx0A registers. If you need multiple shared intc_irqpin device instances, be sure to mask out all interrupts on the INTC that share the one line before you start to register them. Else you run into IRQ floods that would be caused by interrupts for which no handler has been set up yet when the first intc_irqpin device is registered. Signed-off-by:
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- 18 Mar, 2013 15 commits
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Magnus Damm authored
Add DT support to the IRQC External IRQ Pin driver. Signed-off-by:
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Magnus Damm authored
Add initial DT support to the INTC External IRQ Pin driver. At this point only hardware with 4-bit wide sense registers is supported via DT. Signed-off-by:
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Magnus Damm authored
The platform data for the INTC irq pin driver seems to be global symbols, make it static to allow multi-soc build. Signed-off-by:
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Magnus Damm authored
The platform data for the INTC irq pin driver seems to be global symbols, make it static to allow multi-soc build. Signed-off-by:
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Magnus Damm authored
This patch adds a driver for external IRQ pins connected to the IRQC hardware block on recent SoCs from Renesas. The IRQC hardware block is used together with more recent ARM based SoCs using the GIC. As usual the GIC requires external IRQ trigger setup somewhere else which in this particular case happens to be IRQC. This driver implements the glue code needed to configure IRQ trigger and also handle mask/unmask and demux of external IRQ pins hooked up from the IRQC to the GIC. Tested on r8a73a4 but is designed to work with a wide range of SoCs. The driver requires one GIC SPI per external IRQ pin to operate. Each driver instance will handle up to 32 external IRQ pins. The SoCs using this driver are currently mainly used together with regular platform devices so this driver allows configuration via platform data to support things like static interrupt base address. DT support will be added incrementally in the not so distant future. Signed-off-by:
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Magnus Damm authored
Add GPL header to platform data include file. Signed-off-by:
Thomas Gleixner <tglx@linutronix.de> Tested-by:
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Magnus Damm authored
Use devm_kzalloc(), devm_ioremap_nocache() and devm_request_irq() to simplify error handling. Signed-off-by:
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Magnus Damm authored
Add comments to describe the special case for "force" versions of enable and disable functions. Signed-off-by:
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Magnus Damm authored
Cache IRQ in domain_irq variable instead of making use of irq_find_mapping(). While at it rename the irq variable to requested_irq. Signed-off-by:
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Magnus Damm authored
Remove whitespace damage and add newline between variables and code. Signed-off-by:
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Magnus Damm authored
Update the r8a7779 IRQ code to make use of the INTC External IRQ pin driver for external interrupt pins IRQ0 -> IRQ3. The r8a7779 SoC can like older SH SoCs configure to use the IRQ0 -> IRQ3 signals as individual interrupts or a combined IRL mode. Without this patch the r8a7779 SoC code does not fully support external IRQ pins in individual IRQ mode. The r8a7779 PFC code does not yet have gpio_to_irq() support so no need to update such code. At this point the DT reference implementations are not covered. In the future such code shall tie in the INTC External IRQ pin driver via DT, so this kind of verbose code is not needed for the long term DT case. Signed-off-by:
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Magnus Damm authored
Adjust the sh73a0 IRQ code to make use of the INTC External IRQ pin driver for external interrupt pins IRQ0 -> IRQ31. This removes quite a bit of special-case code in intc-sh73a0.c but the number of lines get replaced with platform device information in setup-sh73a0.c. The PFC code is also adjusted to make gpio_to_irq() return the correct interrupt number. At this point the DT reference implementations are not covered. In the future such code shall tie in the INTC External IRQ pin driver via DT, so this kind of verbose code is not needed for the long term DT case. Signed-off-by:
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Magnus Damm authored
Add the macro irq_pin() to let board-specific code using platform devices tie in external IRQn pins in a common way. Signed-off-by:
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Magnus Damm authored
This patch adds a driver for external IRQ pins connected to the INTC block on recent SoCs from Renesas. The INTC hardware block usually contains a rather wide range of features ranging from external IRQ pin handling to legacy interrupt controller support. On older SoCs the INTC is used as a general purpose interrupt controller both for external IRQ pins and on-chip devices. On more recent ARM based SoCs with Cortex-A9 the main interrupt controller is the GIC, but IRQ trigger setup still need to happen in the INTC hardware block. This driver implements the glue code needed to configure IRQ trigger and also handle mask/unmask and demux of external IRQ pins hooked up from the INTC to the GIC. Tested on sh73a0 and r8a7779. The hardware varies quite a bit with SoC model, for instance register width and bitfield widths vary wildly. The driver requires one GIC SPI per external IRQ pin to operate. Each driver instance will handle up to 8 external IRQ pins. The SoCs using this driver are currently mainly used together with regular platform devices so this driver allows configuration via platform data to support things like static interrupt base address. DT support will be added incrementally in the not so distant future. Signed-off-by:
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Phil Edworthy authored
Signed-off-by:
Phil Edworthy <phil.edworthy@renesas.com> [Rename device from to rcarfb to rcar-du] Signed-off-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> [Manual conflict resolution] Signed-off-by:
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- 12 Mar, 2013 12 commits
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Sergei Shtylyov authored
Commit "ARM: shmobile: r8a7779: use gic_iid macro" switched R8A7779 platform devices to using gic_iid() macro instead of gic_spi() but commit "ARM: mach- shmobile: r8a7779: add SATA support" added another use of gic_spi(). Convert the SATA IRQ resource to using gic_iid(). Signed-off-by:
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by:
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Vladimir Barinov authored
Add SATA clock for r8a7779 SoC (for both device tree and usual cases). Register SATA controller as a "late" platform device on r8a7779 SoC. Signed-off-by:
Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by:
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Vladimir Barinov authored
Allow configuration of the r8a7779 SoC SATA controller using a flattened device tree. Signed-off-by:
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Kuninori Morimoto authored
76cc1887 (thermal: rcar: add Device Tree support) supported rcar_thermal DT probing. rcar thermal driver doesn't support IRQ on r8a7779 chip since it is using old design IRQ. R-Car/R-Mobile next generation chips are using new design IRQ, and rcar thermal driver is supporting these. This patch adds rcar_thermal DT support for r8a7779 without IRQ. Signed-off-by:
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Kuninori Morimoto authored
move r8a7740_meram_workaround() to r8a7740 area from r8a7779 area Signed-off-by:
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Kuninori Morimoto authored
"ARM: shmobile: add gic_iid macro for ICCIAR / interrupt ID" enabled to use gic_iid macro. This patch exchange current GIC interrupt setting from gic_spi() to gic_iid() Signed-off-by:
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Kuninori Morimoto authored
r8a7779 is not sh73a0 Signed-off-by:
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Kuninori Morimoto authored
r8a7779 is not r8a7740 chip Signed-off-by:
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Kuninori Morimoto authored
R-Car H1 datasheet GIC number is indicating GIC ICCIAR / interrupt ID number, not SPI number, but current marzen board code is using gic_spi() with un-understandable calculation. This patch adds new gic_iid() macro which means ICCIAR / interrupt ID, and used the number currently written on datasheet. Signed-off-by:
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Bastian Hecht authored
This adds temporarily the alternative device names to the clock list that are used when booting via Device Tree setup. Signed-off-by:
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Magnus Damm authored
Each CPU Hotplug implementation for mach-shmobile is now self-contained, so this change removes unused helper code in hotplug.c. The two CPU Hotplug capable SoCs sh73a0 and r8a7779 remain unchanged. Signed-off-by:
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Magnus Damm authored
Update the r8a7779 SMP code and CPU Hotplug in particular to follow the same style as sh73a0. This means dropping __maybe_unused for #ifdef CONFIG_HOTPLUG_CPU. Signed-off-by:
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