- 16 Feb, 2009 40 commits
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Eilon Greenstein authored
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Harvey Harrison <harvey.harrison@gmail.com> Signed-off-by:
Eilon Greenstein <eilong@broadcom.com> Signed-off-by:
David S. Miller <davem@davemloft.net>
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Eilon Greenstein authored
Resolving the majority of the issues, but there are still some left for future patches. Signed-off-by:
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Eilon Greenstein authored
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Eilon Greenstein authored
This is the device info from the chip shared memory - rename to avoid confusion Signed-off-by:
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Eilon Greenstein authored
When loading in diag mode, set the device to loopback instead of normal link and then changing it to loopback mode Signed-off-by:
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Eilon Greenstein authored
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Eilon Greenstein authored
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Eilon Greenstein authored
The driver default WoL setting is set to the nvram default value Signed-off-by:
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Eilon Greenstein authored
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Eilon Greenstein authored
When enabling many debug prints, it can take a while before processing an event. To ease the debug process, allow bigger timeout before giving up Signed-off-by:
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Eilon Greenstein authored
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Eilon Greenstein authored
Allows better debug capabilities if the user wants to force an MRRS value Signed-off-by:
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Eilon Greenstein authored
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Eilon Greenstein authored
Supporting non-default pre-emphasis settings for the internal and some external PHYs Signed-off-by:
Yaniv Rosner <yanivr@broadcom.com> Signed-off-by:
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Eilon Greenstein authored
Fixing the function name Signed-off-by:
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Eilon Greenstein authored
This code is disabled, so removing it to avoid confusion Signed-off-by:
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Eilon Greenstein authored
This 1G interface (on top of the 4 lanes 10G interface) requires additional setting to work in CL45 Signed-off-by:
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Eilon Greenstein authored
The NIG_ENABLE does not reset the emac. Replace it with explicit reset Signed-off-by:
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Eilon Greenstein authored
Some PHYs (like the BCM8726) FW version cannot be read after activating the PHY, so we need to save this information Signed-off-by:
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Eilon Greenstein authored
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Eilon Greenstein authored
Some dual port PHY require HW lock since they are used by both interfaces (different driver instances). Since this list is getting longer, update a parameter at load time instead of calculating it on runtime Signed-off-by:
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Eilon Greenstein authored
Also adding the ability to recognize the optic module and disable it if it is not authorized for safety reasons - since this feature might upset some users which are willing to take the risk, it is optional and can be disabled by setting an nvram bit (or a trivial driver patch to set this bit). This dual port PHY requires special handling if the ports are swapped. Signed-off-by:
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Eilon Greenstein authored
A GPIO is used with the 8726 PHY. Adding the GPIO related functions in this Signed-off-by:
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Eilon Greenstein authored
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Eilon Greenstein authored
There are too many different board types and this field is not scalable. Removing it and making decisions according to other fields Signed-off-by:
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Eilon Greenstein authored
Setting better HW thresholds and enabling FW capabilities for better enforcement. Also set the HW to more efficiently use the internal buffers if this is a single port design Signed-off-by:
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Eilon Greenstein authored
Some of the configuration can be set when loading the device and shouldn't be re-calculated after each link up indication since it is not dependent on the link speed Signed-off-by:
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Eilon Greenstein authored
Should be called for all incoming packets and not just for GRO packets Signed-off-by:
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Eilon Greenstein authored
Re-ordering the statistics to enhance readability and adding per queue statistics (available via ethtool -S) Signed-off-by:
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Eilon Greenstein authored
This check is unreliable since latest MC can issue warnings on rare occasions which are not fatal errors Signed-off-by:
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Eilon Greenstein authored
Before initializing the chip after iSCSI boot, the interrupts of the function that was used to boot must be disabled. That means that the driver needs to set the chip as if it is the iSCSI PCI function - this bug is exposed only with MSI Signed-off-by:
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Eilon Greenstein authored
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Eilon Greenstein authored
Enabling MSI on top of MSI-X and INTA. Also changing the module parameter to allow choosing INTA or MSI even when MSI-X is available. The default status block should not be reversed for endianity. Since MSI can issue re-configuration, the interrupt disable function now requires mmiowb Signed-off-by:
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Eilon Greenstein authored
Adding Tx multi-queue and enabling multi-queue by default Signed-off-by:
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Eilon Greenstein authored
This is the FW blob and the relevant definitions without any logic. It also contains the minimal mandatory code changes to work with this FW but it does not contain enabling of the new features that this FW provides. This FW is needed for: - More efficient multi-queue - per queue statistics - Big-endian issue with MSI - Improved pause response Signed-off-by:
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Patrick Ohly authored
Both TX and RX hardware time stamping are implemented. Due to hardware limitations it is not possible to verify reliably which packet was time stamped when multiple were pending for sending; this could be solved by only allowing one packet marked for hardware time stamping into the queue (not implemented yet). RX time stamping relies on the flag in the packet descriptor which marks packets that were time stamped. In "all packet" mode this flag is not set. TODO: also support that mode (even though it'll suffer from race conditions). Signed-off-by:
John Ronciak <john.ronciak@intel.com> Signed-off-by:
Patrick Ohly <patrick.ohly@intel.com> Signed-off-by:
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Patrick Ohly authored
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Patrick Ohly authored
Adds the register definitions and code to read the time register. Signed-off-by:
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Patrick Ohly authored
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Patrick Ohly authored
Instructions for time stamping outgoing packets are take from the socket layer and later copied into the new skb. Signed-off-by:
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