- 22 Jun, 2019 39 commits
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Dmytro Laktyushkin authored
We shouldnt need overhead on top of dppclk when setting fclk. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Wenjing Liu authored
Remove dc_dsc hack for MST policy Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Wenjing Liu authored
[why] Clean up some dsc legacy functions that are no longer needed. [how] remove two dsc functions in dc_dsc, use dc_bandwidth_in_kbps_from_timing instead of calc_required_bandwidth_for_timing. Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Joshua Aberback authored
[Why] dcn20_apply_ctx_for_surface can be called with 0 planes, which means we should blank the display. In this case when we get down to dcn20_setup_gsl_group_as_lock, pipe_ctx->plane_state is NULL, but we don't check for it. However, this function is only called by dcn20_pipe_control_lock, and in that function we alraedy have a local for the immediate flip status, which is what we care about in the plane state. [How] - pass in immediate flip status as parameter Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Dmytro Laktyushkin authored
Currently dsc is validated not taking the image width limitation into mind. This change addresses that, but due to previous design being limited to non odm dsc validation additional sequence changes are made. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Aidan Wood authored
[Why] u clk set request was being sent in units of mts, when it needed to be in units of Mhz [How] add a division by 16 to convert from mts to Mhz Signed-off-by: Aidan Wood <Aidan.Wood@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Aidan Wood authored
[Why] If num_states == 0 we did update_bound_box which doesn't updated any max clocks if num_states == 0, therefore we need to do cap_soc_clocks instead, also SMU cannot set DCF clock to a higher than or equal to freq than SOC clock [How] Add a num_states != 0 check for update_bounding_box to be run, and after we run get_maximum_sustainable_clocks we now check if the reported max value of DCF is higher than SOC and if necessary set it to 1000 (becomes 1 after division by 1000) lower than SOC Signed-off-by: Aidan Wood <Aidan.Wood@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Nikola Cornij authored
[why] Currently link bandwidth is calculated in various places using the same multi-step formula. Doing this in one common place makes sure the same formula will indeed be applied to all link bandwidth calculations. It also makes it possible to apply link-setting-specific adjustments that affect effective link bandwidth. [how] Replace all implementations of link bandwidth calculation with a call to a function. Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Vitaly Prosyak authored
[Why & How] When TM is enabled with 3dlut, we apply conversion to dcip3 in gamut remap matrix, if source area less than dcip3. If it is bigger, we remap to bt2020. The added flags will be used to facilitate this logic. Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Dmytro Laktyushkin authored
Currently dcn2+ validation will unconditionally print a failure reason before validation completes. This change categorizes the failure reason as a warning log and only prints at the end of validation resolving false positives. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Bob Yang authored
[Description] swath_bytes_horz_wc should be 256/64/64 for 2160p 32bpp surface Signed-off-by: Bob Yang <Bob.Yang@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Leo Li authored
[Why] dcn*_disable_plane() doesn't unlock the pipe anymore, making the extra lock unnecessary. In addition - during full plane updates - all necessary pipes should be locked/unlocked together when modifying hubp to avoid tearing in pipesplit setups. [How] Remove redundant locks, and add function to lock all pipes. If an interdependent pipe update is required, lock down all pipes. Otherwise, lock only the top pipe for the updated pipe tree. Signed-off-by: Leo Li <sunpeng.li@amd.com> Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Leo Li authored
A previous fix was done for DCN1 that needed to be ported to DCN2: commit 60c677534e73 ("drm/amd/display: Disconnect mpcc when changing tg") Signed-off-by: Leo Li <sunpeng.li@amd.com> Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Hawking Zhang authored
Enable DSC (display stream compression) by default. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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hersen wu authored
not needed for bring up. Signed-off-by: hersen wu <hersenxs.wu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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hersen wu authored
[why] we meet a bug when program dsc register even dsc mode is not enabled. disable dsc config for now. we will re-visit this issue. Signed-off-by: hersen wu <hersenxs.wu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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hersen wu authored
[todo] need find caller bug. tempooariy fix Signed-off-by: hersen wu <hersenxs.wu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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hersen wu authored
[WHY] dcn20 enable usb-c dp ALT mode in dmcu. There is bug when enable abm feature which cause system crash. dal team will debug this bug later. [HOW] disable dcn abm feature for dcn20. Signed-off-by: hersen wu <hersenxs.wu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Eric Bernstein authored
* Pull duplicate audio_clock_info struct to stream_encoder.h * Generalize sec_gsp7* to sec_gsp_pps* * Expose enc1 and enc2 stream encoder audio funcs Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Jun Lei authored
[why] pstate allow/block is not being handled properly on DCN2 [how] DML needs to be updated to calculate pstate support at both min and max mpc combine rather than just min clock manager needs to update current to new pstate support before sending to pplib/smu Signed-off-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Ilya Bakoulin authored
Adding writeback_config enum to vba_vars_st, replacing old flag. Initialize to dm_normal. Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Eric Yang authored
[Why] Some HW specific implementations can be pulled out into clk_mgr.c. [How] - Pull get_active_display_cnt out to clk_mgr. - Pull out shared logic in set_dispclk and set_dprefclk Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Charlene Liu authored
[Description] DMUB is using DPREF CLK, but DMCU still use displayclk. This is for updating DMCU wait_for_loop after display clock change. Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Anthony Koo authored
[Why] Modern Standby may toggle display adapter state between D0 and D3 state unpredictably. But events that cause transition to D0 are not always resulting in a display light up scenario. Modern eDP panels should be able to power on panel logic quickly upon VDD going high. Based on spec, the T3 time between VDD on and HPD high can be between 0 and 80 ms. Doing any tricky sorts of optimization by powering on panel VDD early during D0 transition on can negatively impact other features due to unnecessary power drain and toggling when final system state does not intend for the panel to be lit up. We need OEMs to source higher end panels that have T3 time close to 0 if they want quick S3/Modern Standby resume times. [How] Remove panel VDD power on in init_hw Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Chris Park authored
[Why] link-specific functions should reside in dc_link.c [How] Move them there. Signed-off-by: Chris Park <Chris.Park@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Jun Lei authored
[why] Current calculation of bounding box will cause DML to increase voltage state due to DPP or DISPCLK, this is unnecessary since from DML perspective we can max DPP/DISP can be supported at DPM0. This is because increasing voltage for DPP/DISP is done separately via actual minimum values of DISP and DPP CLK [how] For each calculated state, DPP, DISP, PHY, and DSC clk should always be set to maximum. FCLK, SOCCLK, and DCFCLK should be based of UCLK. Signed-off-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Paul Hsieh authored
[Why] 1. DMCU is not running on some platform but driver still send ABM command. It may cause assert due to DMCU is not alive. 2. To make sure PSR disable when driver disable [How] 1. Add dmcu_is_running in ABM struct, driver can check this flag to determine driver should send ABM command or not. 2. Send PSR disable command when destroy PSR Signed-off-by: Paul Hsieh <paul.hsieh@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Eryk Brol authored
[Why] In the previous implementation DRR event sometimes came in during FP2 region which is a keep-out zone. This would cause the frame not to latch until the next frame which resulted in heavy flicker. To fix this we need to make sure that it triggers in the BP. [How] 1. Remove DRR programming during flip 2. Setup manual trigger for DRR event and trigger it after surface programming is complete Signed-off-by: Eryk Brol <eryk.brol@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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hersen wu authored
caller of pp_nv_set_pme_wa_enable pass incorrect pp_smu: dc->res_pool->pp_smu. it should be dc->res_pool->pp_smu->nv_funcs.pp_smu. with incorrect input, pp->dm = NULL. This causes system crash. Signed-off-by: hersen wu <hersenxs.wu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Joshua Aberback authored
[Why] VTG has a parameter FP2, which is defined as: if VSTARTUP is before VSYNC: FP2 = number of lines in between VSTARTUP and VSYNC else FP2 = 0 Currently, FP2 is only programmed during "program_timing". However, the position of VSTARTUP is affected by the prefetching requirements on all pipes, so the position might change when we do memory request control on another pipe, so we need to make sure that FP2 stays up-to-date whenever we adjust VSTARTUP. [How] - refactor VTG_CONTROL programming into a new function "set_vtg_params" - call it after calling "program_global_sync" - make sure it's called after because it relies on the cached dlg params Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by: Jun Lei <Jun.Lei@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Harry Wentland authored
Add support for DCN2 DSC (Display Stream Compression) HW Blocks: +--------++------+ +----------+ | HUBBUB || HUBP | <-- | MMHUBBUB | +--------++------+ +----------+ | ^ v | +--------+ +--------+ | DPP | | DWB | +--------+ +--------+ | v ^ +--------+ | | MPC | | +--------+ | | | v | +-------+ +-------+ | | OPP | <--> | DSC | | +-------+ +-------+ | | | v | +--------+ / | OPTC | -------------- +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ v2: rebase (Alex) Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Harry Wentland authored
Enable the IP for navi10. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Harry Wentland authored
Enable DCN2 support in DM (Display Manager). v2: fix spurious raven change (Alex) Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
To deal with rebasing the code. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Pass extra parameter to validate_bandwidth() callback. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
To deal with changes from rebasing. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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hersen wu authored
during bring up time, before window dc-ppplib interface design, linux dc use raven dc-pplib interface. now nvai10 dc-pplib-smu interface is changed and verified under window, navi10 need its specific dc-pplib-smu interface. todo: hook set_hard_min_uclk_by_freq, get_maximum_sustainable_clocks Signed-off-by: hersen wu <hersenxs.wu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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hersen wu authored
dc needs get uclk dpm table for bandwidth calculation Signed-off-by: hersen wu <hersenxs.wu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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hersen wu authored
dc (display component) needs maximum clock values of uclock, socclk, dcefclk, to calculate display bandwidth. Signed-off-by: hersen wu <hersenxs.wu@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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- 21 Jun, 2019 1 commit
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Harry Wentland authored
Core DC changes for DCN2. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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