- 26 Mar, 2013 4 commits
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Jesse Barnes authored
Rather than building a config which may or may not work, let the driver build an initial fb config. This allows the driver to use the BIOS boot configuration for example, displaying kernel messages and the initial fb console on the same outputs the BIOS lit up at boot time. If that fails, the driver can still fall back the same way as the core. Signed-off-by:
Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Cc: dri-devel@lists.freedesktop.org Acked-by:
Dave Airlie <airlied@gmail.com> Reviewed-by:
Imre Deak <imre.deak@intel.com> Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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Chris Wilson authored
Wrap a preallocated region of stolen memory within an ordinary GEM object, for example the BIOS framebuffer. Signed-off-by:
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Chris Wilson authored
There is a minute window for a race between put-fence removing the fence and for a new transaction by an external party on the GTT mmap. That is we must zap the mmap prior to removing the fence and not afterwards. Fixes regression from commit 61050808 Author: Chris Wilson <chris@chris-wilson.co.uk> Date: Tue Apr 17 15:31:31 2012 +0100 drm/i915: Refactor put_fence() to use the common fence writing routine v2: Remember the fence to remove with a local variable (gcc) Signed-off-by:
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Rodrigo Vivi authored
According to HSW PM programming guide, frequency bits starts at 24 instead of 25. v2: Paulo Zanoni noticed that only frequency bits can be set at GEN6_RPNSWREQ. All others are read only. CC: Ben Widawsky <ben@bwidawsk.net> CC: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by:
Rodrigo Vivi <rodrigo.vivi@gmail.com> Reviewed-by:
Ben Widawsky <ben@bwidawsk.net> Signed-off-by:
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- 25 Mar, 2013 2 commits
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Damien Lespiau authored
If TRANS_DDI_FUNC_CTL has been wrongly programmed with an incorrect port, we are currently trying to read PORT_CLK_SEL(port) with an uninitialized value. Handle that case by returning PORT_CLK_SEL_NONE and warning about it. v2: Move the warning inside intel_ddi_get_crtc_pll (Paulo Zanoni) Signed-off-by:
Damien Lespiau <damien.lespiau@intel.com> Reviewed-by:
Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by:
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Ben Widawsky authored
HSW doesn't overclock the same way as IVB or SNB. I do not know about VLV, so I've kept that off as well. I'm still working on getting the doc updates to explain how we overclock on Haswell. Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by:
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- 23 Mar, 2013 28 commits
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Paulo Zanoni authored
So don't read it when capturing the error state. This solves "unclaimed register" messages on Haswell when we have a GPU hang. V2: Check for HAS_PCH_SPLIT instead of Gen5+ because VLV still has this register. Signed-off-by:
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Paulo Zanoni authored
So don't read it when capturing the error state. This solves some "unclaimed register" messages on Haswell when we hang the GPU. Signed-off-by:
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Paulo Zanoni authored
The first version of commit "drm/i915: there's no DSPADDR register on Haswell" added 2 "!IS_HASWELL" checks. When reviewing the patch, Ben suggested to make these checks more future-proof, so when Daniel applied the patch he fixed the first check but not the second. This commit makes the second check also "future-proof". Signed-off-by:
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Damien Lespiau authored
The port number should always be correctly set. Do the same thing as the switch above and use BUG() to signal that branch is not supposed to be taken. Signed-off-by:
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Damien Lespiau authored
We are really talking about the transcoder function here and the disable version uses trancoder in its name already, so let's try to be consistent. Signed-off-by:
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Damien Lespiau authored
In the case where the hardware has been wrongly programmed and the EDP TRANS_DDI_FUNC_CTL register has a bogus value in its EDP Input field, we were using the pipe variable uninitialized. In this case, shutdown the transcoder. It will be programmed correctly the next time we try to enabled eDP. Note from Paulo's review: Wrong modeset sequence can easily lead to frozen machines hence the disable_ddi call might be risky. But since things are awry already, doesn't matter too much. Signed-off-by:
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Damien Lespiau authored
Our static analysis tool noticed that 'reg' could be used uninitialized if we are trying to get a PLL to drive VGA and SPLL is already in use (plls->spll_refcoung != 0). In the (error) case above, let's return false to the caller and emit an error. Signed-off-by:
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Ben Widawsky authored
Bspec mentions this for HSW+. I can't quite tell what the effects are, and I don't easily have a way to test this. Signed-off-by:
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Ville Syrjälä authored
We do this for HDMI already, so I don't know why we wouldn't do it for SDVO as well. This is completely untested due to lack of hardware. Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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Ville Syrjälä authored
This comment looks like some historical leftover. Get rid of it. Signed-off-by:
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Ben Widawsky authored
Change the gen6+ max delay if the pcode read was successful (not the inverse). The previous code was all sorts of wrong and has existed since I broke it: commit 42c0526c Author: Ben Widawsky <ben@bwidawsk.net> Date: Wed Sep 26 10:34:00 2012 -0700 drm/i915: Extract PCU communication I added some parentheses for clarity, and I also corrected the debug message message to use the mask (wrong before I came along) and added a print to show the value we're changing from. Looking over the code, I'm not actually sure what we're trying to do. I introduced the bug simply by extracting the function not implementing anything new. We already set max_delay based on the capabilities register (which is what we use elsewhere to determine min and max). This would potentially increase it, I suppose? Jesse, I can't find the document which explains the definitions of the pcode commands, maybe you have it around. Based on Jesse's response, this could potentially be for -fixes, or stable, or maybe lead to us dropping it entirely. As the current code is is, things won't completely break because of the aforementioned capabilities register, and in my experimentation, enabling this has no effect, it goes from 1100->1100. I found this while reviewing Jesse's VLV patches. Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by:
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Ben Widawsky authored
Recommended by Chris. v2: Make it GEN7_FEATURES, and use it for vlv and hsw also (Ben) Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
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Ben Widawsky authored
Requested by Daniel. v2: Fix incorrect num_pipe settings. (Chris) Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by:
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Daniel Vetter authored
The index variable points at a page table, not a page directory or a pde. Ben Widawsky fix this up correctly in his ppgtt cleanup, but I've botched the job and copy&pasted the old confusion from the original gen6 ppgtt code in commit def886c3 Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Thu Jan 24 14:44:56 2013 -0800 drm/i915: vfuncs for ppgtt Reviewed-by:
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Daniel Vetter authored
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Jesse Barnes authored
Port C is for eDP. Port B is shared between HDMI and DP. Signed-off-by:
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Jesse Barnes authored
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Jesse Barnes authored
We'll re-enable select bits as needed after testing and power measurement. v2: split out wake handling bits (Jani) Signed-off-by:
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Jesse Barnes authored
Can prevent a hang when we get to tessellation. We need to set bit 15 as well for this workaround. v2: update changelog with accurate info Signed-off-by:
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Jesse Barnes authored
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Jesse Barnes authored
This fixes up broken logic introduced in commit 90b107c8 Author: Shobhit Kumar <shobhit.kumar@intel.com> Date: Wed Mar 28 13:39:32 2012 -0700 drm/i915: Enable HDMI on ValleyView That one was probably a rebase fail along the way. v2: clean up init ordering (Daniel) Signed-off-by:
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Jesse Barnes authored
We could split this out into a separate routine at some point as an optimization. v2: use FORCEWAKE_KERNEL (Ville) Note: Ville mentioned in his review that he declines to be responsible if this blows up due to the lack of "readback a register != FW_ACK, but from the same cacheline" magic we have in other forcewake implementations. Signed-off-by:
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Jesse Barnes authored
Planes are fixed to pipes in VLV. Signed-off-by:
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Rahul Sharma authored
It fixes the issue arises due to passing 'nr_pages' in place of 'nents' to sg_alloc_table. When ARM_HAS_SG_CHAIN is disabled, it is causing failure in creating SG table for the buffers having more than 204 physical pages i.e. equal to SG_MAX_SINGLE_ALLOC. When using sg_alloc_table_from_pages interface, in place of sg_alloc_table, page list will be passes to get each contiguous section which is represented by a single entry in the table. For a Contiguous Buffer, number of entries should be equal to 1. Following check is causing the failure which is not applicable for Non-Contig buffers: if (WARN_ON_ONCE(nents > max_ents)) return -EINVAL; Above patch is well tested for EXYNOS4 and EXYNOS5 for with/wihtout IOMMU supprot. NOUVEAU and RADEON platforms also depends on drm_prime_pages_to_sg helper function. This set is base on "exynos-drm-fixes" branch at http://git.kernel.org/?p=linux/kernel/git/daeinki/drm-exynos.gitSigned-off-by:
Rahul Sharma <rahul.sharma@samsung.com> Acked-by:
Aaron Plattner <aplattner@nvidia.com> Tested-by:
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Imre Deak authored
The existing gtt setup code is correct - and so doesn't need to be fixed to handle compact dma scatter lists similarly to the previous patches. Still, take the for_each_sg_page macro into use, to get somewhat simpler code. Signed-off-by:
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Imre Deak authored
So far we created a sparse dma scatter list for gem objects, where each scatter list entry represented only a single page. In the future we'll have to handle compact scatter lists too where each entry can consist of multiple pages, for example for objects imported through PRIME. The previous patches have already fixed up all other places where the i915 driver _walked_ these lists. Here we have the corresponding fix to _create_ compact lists. It's not a performance or memory footprint improvement, but it helps to better exercise the new logic. Reference: http://www.spinics.net/lists/dri-devel/msg33917.htmlSigned-off-by:
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Imre Deak authored
So far the assumption was that each dma scatter list entry contains only a single page. This might not hold in the future, when we'll introduce compact scatter lists, so prepare for this everywhere in the i915 code where we walk such a list. We'll fix the place _creating_ these lists separately in the next patch to help the reviewing/bisectability. Reference: http://www.spinics.net/lists/dri-devel/msg33917.htmlSigned-off-by:
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Imre Deak authored
This is needed since currently sg_for_each_page assumes that we have a valid page in each sg item. It is only a real problem for CONFIG_SPARSEMEM where the page is dereferenced, in other cases the iterator works ok with an invalid page pointer. We can remove this workaround when we have fixed sg_page_iter to work on scatterlists without backing pages. Signed-off-by:
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- 19 Mar, 2013 3 commits
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Imre Deak authored
So far the assumption was that each scatter list entry contains a single page. This might not hold in the future, when we'll introduce compact scatter lists, so prepare for this here. Reference: http://www.spinics.net/lists/dri-devel/msg33917.htmlSigned-off-by:
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Daniel Vetter authored
Backmerge so that I can merge Imre Deak's coalesced sg entries fixes, which depend upon the new for_each_sg_page introduce in commit a321e91b Author: Imre Deak <imre.deak@intel.com> Date: Wed Feb 27 17:02:56 2013 -0800 lib/scatterlist: add simple page iterator The merge itself is just two trivial conflicts: Signed-off-by:
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Jesse Barnes authored
We need to set the 'allow force wake' bit to enable forcewake handling later on. v2: split from clock gating patch (Jani) check for allowwakeack (Ville) Signed-off-by:
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- 18 Mar, 2013 2 commits
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Ben Widawsky authored
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Ben Widawsky authored
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- 17 Mar, 2013 1 commit
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Linus Torvalds authored
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