- 30 Oct, 2015 1 commit
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Mike Looijmans authored
Supplying pinmux configuration for e.g. gpio pins leads to deferred probes because the pinctrl device is probed much later than gpio. Move the init call to a much earlier stage so it probes before the devices that may need it. Signed-off-by:
Mike Looijmans <mike.looijmans@topic.nl> Tested-by:
Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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- 27 Oct, 2015 10 commits
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Julia Lawall authored
for_each_child_of_node performs an of_node_get on each iteration, so a break out of the loop requires an of_node_put. A simplified version of the semantic patch that fixes this problem is as follows (http://coccinelle.lip6.fr): // <smpl> @@ expression root,e; local idexpression child; @@ for_each_child_of_node(root, child) { ... when != of_node_put(child) when != e = child ( return child; | + of_node_put(child); ? return ...; ) ... } // </smpl> Signed-off-by:
Julia Lawall <Julia.Lawall@lip6.fr> Acked-by:
Ludovic Desroches <ludovic.desroches@atmel.com> Signed-off-by:
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Jon Hunter authored
The description of the XUSB_PADCTL_USB3_PAD_MUX_0 register in the Tegra124 documentation implies that all functions (pcie, usb3 and sata) can be muxed onto to all lanes (pcie lanes 0-4 and sata lane 0). However, it has been confirmed that this is not the case and the mux'ing options much more limited. Unfortunately, the public documentation has not been updated to reflect this and so detail the actual mux'ing options here by function: Function: Lanes: pcie1 x2: pcie3, pcie4 pcie1 x4: pcie1, pcie2, pcie3, pcie4 pcie2 x1 (option1): pcie0 pcie2 x1 (option2): pcie2 usb3 port 0: pcie0 usb3 port 1 (option 1): pcie1 usb3 port 1 (option 2): sata0 sata: sata0 Signed-off-by:
Jon Hunter <jonathanh@nvidia.com> Acked-by:
Stephen Warren <swarren@nvidia.com> Signed-off-by:
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Mika Westerberg authored
This driver adds pinctrl/GPIO support for Intel Broxton. The GPIO controller is based on the same hardware design that is already used in Intel Sunrisepoint so we leverage the core driver here. Signed-off-by:
Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by:
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Mika Westerberg authored
Reserved for ACPI actually means that in such case the GPIO hardware will not update the interrupt status register (GPI_IS) even if the pin is configured to trigger an interrupt. It will update GPI_GPE_STS instead and does not trigger an interrupt. Allow using such pins as GPIOs, only prevent their usage as interrupts. We also rename function intel_pad_reserved_for_acpi() to be intel_pad_acpi_mode() which reflects the actual meaning better. Signed-off-by:
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Mika Westerberg authored
On Intel Broxton the GPIO hardware consists of several chips that all share the parent interrupt. It is not possible to handle this by setting chained handler for each chip (as they will overwrite each other). To overcome this we need to request the interrupt using devm_request_irq() and pass IRQF_SHARED with the flags. Signed-off-by:
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Douglas Anderson authored
For pinctrl the "default" state is applied to pins before the driver's probe function is called. This is normally a sensible thing to do, but in some cases can cause problems. That's because the pins will change state before the driver is given a chance to program how those pins should behave. As an example you might have a regulator that is controlled by a PWM (output high = high voltage, output low = low voltage). The firmware might leave this pin as driven high. If we allow the driver core to reconfigure this pin as a PWM pin before the PWM's probe function runs then you might end up running at too low of a voltage while we probe. Let's introudce a new "init" state. If this is defined we'll set pinctrl to this state before probe and then "default" after probe (unless the driver explicitly changed states already). An alternative idea that was thought of was to use the pre-existing "sleep" or "idle" states and add a boolean property that we should start in that mode. This was not done because the "init" state is needed for correctness and those other states are only present (and only transitioned in to and out of) when (optional) power management is enabled. Changes in v3: - Moved declarations to pinctrl/devinfo.h - Fixed author/SoB Changes in v2: - Added comment to pinctrl_init_done() as per Linus W. Signed-off-by:
Douglas Anderson <dianders@chromium.org> Acked-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org> Tested-by:
Caesar Wang <wxt@rock-chips.com> Signed-off-by:
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Masahiro Yamada authored
While IECTRL is disabled, input signals are pulled-down internally. If pin-muxing is set up first, glitch signals (Low to High transition) might be input to hardware blocks. Bad case scenario: [1] The hardware block is already running before pinctrl is handled. (the reset is de-asserted by default or by a firmware, for example) [2] The pin-muxing is set up. The input signals to hardware block are pulled-down by the chip-internal biasing. [3] The pins are input-enabled. The signals from the board reach the hardware block. Actually, one invalid character is input to the UART blocks for such SoCs as PH1-LD4, PH1-sLD8, where UART devices start to run at the power on reset. To avoid such problems, pins should be input-enabled before muxing. Fixes: 6e908892 ("pinctrl: UniPhier: add UniPhier pinctrl core support") Signed-off-by:Masahiro Yamada <yamada.masahiro@socionext.com> Reported-by:
Dai Okamura <okamura.dai@socionext.com> Signed-off-by:
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Pramod Kumar authored
This new compatible string, "brcm,iproc-gpio", should be used for all new iproc-based future SoCs. Signed-off-by:
Pramod Kumar <pramodku@broadcom.com> Reviewed-by:
Ray Jui <rjui@broadcom.com> Reviewed-by:
Scott Branden <sbranden@broadcom.com> Signed-off-by:
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Pramod Kumar authored
Remove gpio to pinctrl pin mapping code from driver and address this through standard property "gpio-ranges". Signed-off-by:
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Pramod Kumar authored
If GPIO controller's pins are muxed, pin-controller subsystem need to be intimated by defining mapping between gpio and pinmux controller. This patch adds required properties to define this mapping via DT. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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- 26 Oct, 2015 1 commit
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Linus Walleij authored
Merge branch 'sh-pfc-for-v4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
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- 23 Oct, 2015 2 commits
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Hans de Goede authored
Add pinmuxing for external interrupt functionality through the sun6i "r" pincontroller. Signed-off-by:
Hans de Goede <hdegoede@redhat.com> Acked-by:
Chen-Yu Tsai <wens@csie.org> Acked-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by:
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Hans de Goede authored
The r_pio gpio / pin controller has a pin_base of non 0, we need to adjust for this before calling sunxi_pinctrl_desc_find_function_by_pin. Signed-off-by:
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- 20 Oct, 2015 9 commits
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Geert Uytterhoeven authored
Since the removal of the r8a7778 legacy SoC code in commit 4baadb9e ("ARM: shmobile: r8a7778: remove obsolete setup code"), r8a7778 is only supported in generic DT-only ARM multi-platform builds. The driver doesn't need to match platform devices by name anymore, hence remove the corresponding platform_device_id entry. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Acked-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by:
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Geert Uytterhoeven authored
Since the removal of the r8a7779 legacy SoC code in commit c99cd90d ("ARM: shmobile: r8a7779: Remove legacy SoC code"), r8a7779 is only supported in generic DT-only ARM multi-platform builds. The driver doesn't need to match platform devices by name anymore, hence remove the corresponding platform_device_id entry. Signed-off-by:
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Geert Uytterhoeven authored
This header file will be removed soon. Copy the helper macro RCAR_GP_PIN(), which is used by the pinctrl drivers only, to sh_pfc.h, and drop the #include. Signed-off-by:
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Geert Uytterhoeven authored
This header file will be removed soon. Signed-off-by:
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Acked-by:
Felipe Balbi <balbi@ti.com>
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Geert Uytterhoeven authored
The sh_pfc_soc_info.gpio_data[] array contains not only GPIO data, but also various other pinmux-related data (functions and marks). Every single driver already calls its local array pinmux_data[]. Hence rename the sh_pfc_soc_info member to "pinmux_data". Signed-off-by:
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Ulrich Hecht authored
On this SoC there is no simple mapping of GP pins to pull-up register bits, so we need a table. Signed-off-by:
Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Reviewed-by:
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Ulrich Hecht authored
PORT_GP_CFG_1 and PORT_GP_CFG_32 work like their non-CFG counterparts but accept an extra argument with config flags. Signed-off-by:
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Koji Matsuoka authored
Add VIN0/1 pin groups to R8A7794 PFC driver. Sergei: rebased, renamed, added changelog, gathered 12 VIN1 data pins into a single pin group, added "vin1_data10" pin group, used 'union vin_data' and VIN_DATA_PIN_GROUP() macro to describe VIN1 pins, reversed the order of the VIN1 pin groups, removed unneeded empty lines, fixed VIN1 separator comment. Signed-off-by:
Koji Matsuoka <koji.matsuoka.xm@renesas.com> Signed-off-by:
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by:
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Sergei Shtylyov authored
R8A7790/1 PFC drivers use almost identical 'union vin_data' and completely identical VIN_DATA_PIN_GROUP() macro; we thus can move them into the shared header file... Suggested-by:
Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by:
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- 16 Oct, 2015 12 commits
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Mika Westerberg authored
When CONFIG_PM is not set we get following compilation warnings: warning: ‘byt_gpio_runtime_suspendâ€
™ defined but not used [-Wunused-function] warning: ‘byt_gpio_runtime_resume’ defined but not used [-Wunused-function] Fix this by guarding byt_gpio_runtime_suspend()/byt_gpio_runtime_resume() with #ifdef CONFIG_PM. Signed-off-by: -
Mika Westerberg authored
We get following warning when CONFIG_PM_SLEEP is not set warning: ‘intel_gpio_irq_initâ€
™ defined but not used [-Wunused-function] Since the function is only called from intel_pinctrl_resume() move it inside CONFIG_PM_SLEEP guard as well. Signed-off-by: -
Jonas Gorski authored
The DEBUG_FS=n #defines for the dbg_show functions were missed when renaming the driver from msm_ to pm8xxx_, causing it to break the build when DEBUG_FS isn't enabled: CC [M] drivers/pinctrl/qcom/pinctrl-ssbi-gpio.o drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c:597:14: error: ‘pm8xxx_gpio_dbg_showâ€
™ undeclared here (not in a function) .dbg_show = pm8xxx_gpio_dbg_show, Fix this by renaming them correctly. Fixes: b4c45fe9 ("pinctrl: qcom: ssbi: Family A gpio & mpp drivers") Signed-off-by:Jonas Gorski <jogo@openwrt.org> Reviewed-by:
Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by:
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Wei Chen authored
The the pin groups and pin functions have been changed in atlas7 step B soc. We have to update the driver to support step B chip. Changes: 1. add 5 jtag pins to IOC_TOP: "jtag_tdo", "jtag_tms","jtag_tck", "jtag_tdi", "jtag_trstn" these 5 pins can be mutiplex with other functions, so we have to conver these 5 pins in pinmux. 2. add pin groups for audio digmic, audio spdif, can transceiver en, can transceiver stb, i2s0, i2s1 and jtag. 3. serval pins can be located to more PADs: audio_uart0_urfs, audio_uart1_urfs, audio_uart2_urfs, audio_uart2_urxd, audio_uart2_usclk, audio_uart2_utfs, audio_uart2_utxd, can0_rxd, can0_txd, can1_rxd, can1_txd jtag_ntrst, jtag_swdiotms, jtag_tck, jtag_tdi, jtag_tdo, pw_cko0, pw_cko1, pw_i2s01, pw_pwm0, pw_pwm1, sd2_cdb, sd2_wpb, uart2_cts, uart2_rts, uart2_rxd, uart2_txd, uart3_cts, uart3_rts, uart3_rxd, uart3_txd, uart4_cts, uart4_rts, usb0_drvvbus, usb1_drvvbus. Because of Changes#3, some functions should have more than one pin groups. So we have to split the original pin group to serval pin groups. For example: audio_uart0 has 5 pins, on STEPA, each of these 5 pins only has one related PAD. But on STEPB, audio_uart0_urfs has 4 related PAD. So we place the 4 pins with one PAD into a single pin group: audio_uart0_basic_group. and place urfs pin wtih different PADs to 4 different pin groups: audio_uart0_urfs_group0, ..., audio_uart0_urfs_group3 A full audio_uart0 pin group can be: pinctrl-0 = <&audio_uart0_basic_group &audio_uart0_urfs_group0>; If audio_uart0 pin group encountered some confiction, we only have to change the urfs group: pinctrl-0 = <&audio_uart0_basic_group &audio_uart0_urfs_group2>; Signed-off-by:
Wei Chen <Wei.Chen@csr.com> Signed-off-by:
Barry Song <Baohua.Song@csr.com> Signed-off-by:
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Thomas Hebb authored
The previous register layout was incorrect, many of the fields having fewer bits than were needed to represent all their modes. The new layout is taken from the bootloader source of a BG2CD device. Signed-off-by:
Thomas Hebb <tommyhebb@gmail.com> Acked-by:
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by:
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Antoine Ténart authored
My family name contained an accent when I submitted the Berlin pinctrl series in the first place. There was an encoding issue when the series was applied. Fix this. Signed-off-by:
Antoine Ténart <antoine.tenart@free-electrons.com> Acked-by:
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Antoine Tenart authored
Berlin pinctrl drivers depends on CONFIG_OF. This patch adds this dependency explicitly. Signed-off-by:
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Antoine Tenart authored
This patch prepares to remove the pinctrl driver selection from the mach-berlin Kconfig. To do so, bool is replaced by def_bool. Signed-off-by:
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Jisheng Zhang authored
Add berlin4ct to existing berlin pinctrl device tree binding. Signed-off-by:
Jisheng Zhang <jszhang@marvell.com> Acked-by:
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Jisheng Zhang authored
Add the pin-controller driver for Marvell Berlin BG4CT SoC, with definition of its groups and functions. This uses the core Berlin pinctrl driver. Signed-off-by:
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Jisheng Zhang authored
It is good to allow berlin pinctrl driver to build with COMPILE_TEST, so make the it menu visible when compile-testing. Signed-off-by:
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Jisheng Zhang authored
This is to prepare for the next berlin4ct support, where we won't use simple-mfd any more. Signed-off-by:
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- 02 Oct, 2015 5 commits
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Masahiro Yamada authored
PIN_CONFIG_INPUT_SCHMITT is defined in enum_pin_config_param, but the corresponding DT property is missing. Signed-off-by:
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Masahiro Yamada authored
Currently, the dt_params array in drivers/pinctrl/pinconf-generic.c is not sorted in the same order as the enum pin_config_param in include/linux/pinctrl/pinconf-generic.h. Sort enum pin_config_param, conf_items, dt_params, alphabetically for consistency. Signed-off-by:
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Ludovic Desroches authored
Irq argument as been removed from irq flow handlers so use the irq descriptor to retrieve data we need. Signed-off-by:
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Ludovic Desroches authored
Use irq_set_handler_locked() as it avoids a redundant lookup of the irq descriptor. Signed-off-by:
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Adrian Alonso authored
Add iomuxc-lpsr devicetree bindings documentation Provide documentation context as well an example on pheriperals that could use pad from either iomuxc controller supported by iMX7D SoC Signed-off-by:
Adrian Alonso <aalonso@freescale.com> Acked-by:
Shawn Guo <shawnguo@kernel.org> Signed-off-by:
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