1. 04 Nov, 2009 7 commits
    • Tejun Heo's avatar
      pccard: configure CLS on attach · 15ea76d4
      Tejun Heo authored
      For non hotplug PCI devices, the system firmware usually configures
      CLS correctly.  For pccard devices system firmware can't do it and
      Linux PCI layer doesn't do it either.  Unfortunately this leads to
      poor performance for certain devices (sata_sil).  Unless MWI, which
      requires separate configuration, is to be used, CLS doesn't affect
      correctness, so the configuration should be harmless.
      
      This patch makes pci_set_cacheline_size() always built and export it
      and make pccard call it during attach.
      
      Please note that some other PCI hotplug drivers (shpchp and pciehp)
      also configure CLS on hotplug.
      Signed-off-by: default avatarTejun Heo <tj@kernel.org>
      Cc: Daniel Ritz <daniel.ritz@gmx.ch>
      Cc: Dominik Brodowski <linux@dominikbrodowski.net>
      Cc: Greg KH <greg@kroah.com>
      Cc: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
      Cc: Axel Birndt <towerlexa@gmx.de>
      Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
      15ea76d4
    • Tejun Heo's avatar
      sparc64/PCI: drop PCI_CACHE_LINE_BYTES · 4c0eec7a
      Tejun Heo authored
      sparc64 is now the only user of PCI_CACHE_LINE_BYTES.  Drop it and set
      pci_dfl_cache_line_size from pcibios_init() instead and drop
      PCI_CACHE_LINE_BYTES handling from generic pci code.
      
      Orignally-From: David Miller <davem@davemloft.net>
      Signed-off-by: default avatarTejun Heo <tj@kernel.org>
      Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
      4c0eec7a
    • Jesse Barnes's avatar
      PCI: determine CLS more intelligently · ac1aa47b
      Jesse Barnes authored
      Till now, CLS has been determined either by arch code or as
      L1_CACHE_BYTES.  Only x86 and ia64 set CLS explicitly and x86 doesn't
      always get it right.  On most configurations, the chance is that
      firmware configures the correct value during boot.
      
      This patch makes pci_init() determine CLS by looking at what firmware
      has configured.  It scans all devices and if all non-zero values
      agree, the value is used.  If none is configured or there is a
      disagreement, pci_dfl_cache_line_size is used.  arch can set the dfl
      value (via PCI_CACHE_LINE_BYTES or pci_dfl_cache_line_size) or
      override the actual one.
      
      ia64, x86 and sparc64 updated to set the default cls instead of the
      actual one.
      
      While at it, declare pci_cache_line_size and pci_dfl_cache_line_size
      in pci.h and drop private declarations from arch code.
      Signed-off-by: default avatarTejun Heo <tj@kernel.org>
      Acked-by: default avatarDavid Miller <davem@davemloft.net>
      Acked-by: default avatarGreg KH <gregkh@suse.de>
      Cc: Ingo Molnar <mingo@elte.hu>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Tony Luck <tony.luck@intel.com>
      Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
      ac1aa47b
    • Yinghai Lu's avatar
      x86/PCI: read root resources from IOH on Intel · 99935a7a
      Yinghai Lu authored
      For intel systems with multi IOH, we should read peer root resources
      directly from PCI config space, and don't trust _CRS.
      Signed-off-by: default avatarYinghai Lu <yinghai.lu@sun.com>
      Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
      99935a7a
    • Linus Torvalds's avatar
      Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel · 91d3f9ba
      Linus Torvalds authored
      * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel:
        drm/i915: Ironlake suspend/resume support
        drm/i915: kill warning in intel_find_pll_g4x_dp
        drm/i915: update watermarks before enabling PLLs
        drm/i915: add FIFO watermark support for G4x
        drm/i915: quiet DP i2c init
        drm/i915: fix panel fitting filter coefficient select for Ironlake
        drm/i915: fix to setup display reference clock control on Ironlake
        drm/i915: Install a fence register for fbc on g4x
        drm/i915: save/restore BLC histogram control reg across suspend/resume
        drm/i915: Fix FDI M/N setting according with correct color depth
        drm/i915: disable powersave feature for Ironlake currently
        drm/i915: Fix render reclock availability detection.
        drm/i915: Save and restore the GM45 FBC regs on suspend and resume.
        drm/i915: Set the LVDS_BORDER when using LVDS scaling mode
        drm/i915: disable FBC for Pineview, fixing a boot hang.
      91d3f9ba
    • Linus Torvalds's avatar
      Merge branch 'for-linus' of git://git.kernel.dk/linux-2.6-block · 51bb296b
      Linus Torvalds authored
      * 'for-linus' of git://git.kernel.dk/linux-2.6-block:
        cfq-iosched: limit coop preemption
        cfq-iosched: fix bad return value cfq_should_preempt()
        backing-dev: bdi sb prune should be in the unregister path, not destroy
        Fix bio_alloc() and bio_kmalloc() documentation
        bio_put(): add bio_clone() to the list of functions in the comment
      51bb296b
    • Linus Torvalds's avatar
      Merge branch 'upstream-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jgarzik/libata-dev · dc79d2f2
      Linus Torvalds authored
      * 'upstream-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jgarzik/libata-dev:
        sata_via: Remove redundant device ID for VIA VT8261
        drivers/ata/libata: Move dereference after NULL test
        ahci: Enable SB600 64bit DMA on MSI K9A2 Platinum v2
      dc79d2f2
  2. 03 Nov, 2009 32 commits
  3. 02 Nov, 2009 1 commit