- 23 Feb, 2015 40 commits
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Geert Uytterhoeven authored
Move the Ethernet node from the root of the device tree to the BSC node, as it's connected to the Bus State Controller. This allows the system to know the right position of the Ethernet node in the clock and PM domain hierarchy, and manage the clock and PM domain appropriately. Also rename the node's name from "lan9220" to "ethernet", to conform to ePAPR generic name recomendations. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Geert Uytterhoeven authored
Add a node for the Bus State Controller (BSC) on sh73a0, to which multiple external devices can be connected. The BSC is driven by the ZB clock, and located in PM domain A4S. A reference to the latter will be added later. Signed-off-by:
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Magnus Damm authored
Build the sh73a0 KZM9G board DTB in case of Multiplatform. The DT reference case will be removed in the future and can be ignored for now. Signed-off-by:
Magnus Damm <damm+renesas@opensource.se> Signed-off-by:
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Magnus Damm authored
Sync the two DTS for the KZM9G board. The target is the file "sh73a0-kzm9g.dts" and it is made identical to the DT reference case with the exception of the compatbile string. In the future the DT reference file will go away. Signed-off-by:
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Magnus Damm authored
Enable sh73a0 Multiplatform support for the generic sh73a0 machine vector. No board support is enabled, and the board code for KZM9G DT Reference is left by itself. Signed-off-by:
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Magnus Damm authored
Add a generic sh73a0 machine setup callback for the upcoming sh73a0 multiplatform case. Cache needs to be configured, and legacy clocks must be omitted. Signed-off-by:
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Simon Horman authored
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Sergei Shtylyov authored
Define the generic R8A7794 parts of the SDHI[012] device nodes. Based on the orginal patch by Shinobu Uehara <shinobu.uehara.xc@renesas.com>. Signed-off-by:
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by:
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Geert Uytterhoeven authored
Add a driver for transparent busses that don't need a real driver, but where the bus controller is part of a PM domain, or under the control of a functional clock. Typically, the bus controller's PM domain and/or clock must be enabled for child devices connected to the bus (either on-SoC or externally) to function. Hence the sole purpose of this driver is to enable its clock and PM domain (if exist(s)), which are specified in the DT and managed from platform and PM domain code, and to probe for child devices. Due to the child-parent relationship with devices connected to the bus, PM domain and clock state transitions are handled in the correct order. Signed-off-by:
Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Reviewed-by:
Kevin Hilman <khilman@linaro.org> Signed-off-by:
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Geert Uytterhoeven authored
The bindings for the BSC extend the bindings for "simple-pm-bus". Signed-off-by:
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Geert Uytterhoeven authored
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Geert Uytterhoeven authored
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Geert Uytterhoeven authored
Signed-off-by:
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Sergei Shtylyov authored
Add the ADSP clocks to the CPG and MSTP5 nodes of the R8A7790 device tree. Based on the original patch by Konstantin Kozhevnikov <konstantin.kozhevnikov@cogentembedded.com>. Signed-off-by:
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Sergei Shtylyov authored
Add the ADSP clocks to the CPG and MSTP5 nodes of the R8A7791 device tree. Based on the original patch by Konstantin Kozhevnikov <konstantin.kozhevnikov@cogentembedded.com>. Signed-off-by:
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Sergei Shtylyov authored
Define the Henninger board dependent part of the CAN0 device node. Signed-off-by:
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Sergei Shtylyov authored
Define the generic R8A7791 parts of the CAN0/1 device nodes. Signed-off-by:
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Sergei Shtylyov authored
The R-Car CAN controllers can derive the CAN bus clock not only from their peripheral clock input (clkp1) but also from the other internal clock (clkp2) and external clock fed on CAN_CLK pin. Describe those clocks in the device tree, along with the USB_EXTAL clock from which clkp2 is derived. Signed-off-by:
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Sergei Shtylyov authored
Define the generic R8A7790 parts of the CAN0/1 device nodes. Signed-off-by:
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Sergei Shtylyov authored
The R-Car CAN controllers can derive the CAN bus clock not only from their peripheral clock input (clkp1) but also from the other internal clock (clkp2) and external clock fed on CAN_CLK pin. Describe those clocks in the device tree, along with the USB_EXTAL clock from which clkp2 is derived. Signed-off-by:
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Niklas Söderlund authored
Configure the pinmux on kzm9d to use the serial connector for uart1. Signed-off-by:
Niklas Söderlund <niso@kth.se> Acked-by:
Linus Walleij <linus.walleij@linaro.org> Acked-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
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Niklas Söderlund authored
With this information all GPIOs can make use of the PFC functionality. Signed-off-by:
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Wolfram Sang authored
Documentation says the last register is at 0x184 (CAxCPUCMCR), so use proper length. Current APMU code accesses CAxCPUnCR which is currently outside of the remapped area. Signed-off-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by:
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Wolfram Sang authored
Documentation says the last register is at 0x184 (CAxCPUCMCR), so use proper length. Current APMU code accesses CAxCPUnCR which is currently outside of the remapped area. Signed-off-by:
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Laurent Pinchart authored
Add DT nodes for the ADV7511 HDMI encoder and its HDMI output connector and configure the DISP pin group that drives the HDMI transmitter DE pin. Signed-off-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by:
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Simon Horman authored
There appears to have been some inconsistency and confusion here as on the r8a7790 these clocks are referred to as SD(HI)1 and SD(HI)2 while on the r8a7791 and r8a7794 they are referred to as SD(HI)2 and SD(HI)3. Fixes: 59e79895 ("ARM: shmobile: r8a7791: Add clocks") Reported-by:
Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by:
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Simon Horman authored
* Correct base address of SD3 div6 clk. * Update div6 clock node labels There appears to have been some inconsistency and confusion here as on the r8a7790 these clocks are referred to as SD(HI)1 and SD(HI)2 while on the r8a7791 and r8a7794 they are referred to as SD(HI)2 and SD(HI)3. This has no run-time affect as the clock nodes are not currently used. Fixes: 8e181633 ("ARM: shmobile: r8a7794: Add SDHI clocks to device tree") Reported-by:
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Laurent Pinchart authored
Enable the ethernet controller for the Alt board. Pin muxing entries are currently left out as r8a7794 pin control support isn't available yet. We thus rely on the boot loader to configure ethernet pins for now. Signed-off-by:
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Laurent Pinchart authored
Add a DT node for the on-SoC ethernet controller device. Signed-off-by:
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Laurent Pinchart authored
Add the six IPMMU instances found in the r8a7794 to DT with a disabled status. Signed-off-by:
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Laurent Pinchart authored
Add the seven IPMMU instances found in the r8a7791 to DT with a disabled status. Signed-off-by:
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Laurent Pinchart authored
Add the six IPMMU instances found in the r8a7790 to DT with a disabled status. Signed-off-by:
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Laurent Pinchart authored
Instantiate the two system DMA controllers in the r8a7794 device tree. Signed-off-by:
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Geert Uytterhoeven authored
Traditionally, the first 16 MiB of RAM was reserved for the RT processor. However, this is incompatible with CONFIG_AUTO_ZRELADDR=y, which requires that the start address of physical memory is a multiple of 128 MiB. As CONFIG_AUTO_ZRELADDR=y is enabled for multi-platform kernels, declare RAM to start at 0x40000000. While at it, reclaim the last 8 MiB of RAM, too, so the full 512 MiB is available. Note that kzm9g_defconfig still has CONFIG_MEMORY_START=0x41000000 and CONFIG_MEMORY_SIZE=0x1f000000, so before the advent of DT we scribbled over the last 8 MiB, too. Signed-off-by:
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Geert Uytterhoeven authored
Traditionally, the first 16 MiB of RAM was reserved for the RT processor. However, this is incompatible with CONFIG_AUTO_ZRELADDR=y, which requires that the start address of physical memory is a multiple of 128 MiB. As CONFIG_AUTO_ZRELADDR=y is enabled for multi-platform kernels, declare RAM to start at 0x40000000. While at it, reclaim the last 8 MiB of RAM, too, so the full 512 MiB is available. Note that kzm9g_defconfig still has CONFIG_MEMORY_START=0x41000000 and CONFIG_MEMORY_SIZE=0x1f000000, so before the advent of DT we scribbled over the last 8 MiB, too. Signed-off-by:
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Ulrich Hecht authored
Specifies clock sources and register bits. Signed-off-by:
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Geert Uytterhoeven authored
This clock drives the irqpin controller modules. Before, it was assumed enabled by the bootloader or reset state. By making it available to the driver, we make sure it gets enabled when needed, and allow it to be managed by system or runtime PM. Signed-off-by:
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Laurent Pinchart authored
Enable the kzm9g touchscreen controller in the board's DT file. Signed-off-by:
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Geert Uytterhoeven authored
Add a DT node for the R2025D real-time clock, which is connected to i2c0. Signed-off-by:
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Geert Uytterhoeven authored
Add a DT node for the ADXL345 three-axis digital accelerometer sensor, which is connected to i2c0. As trivial i2c devices are matched against the first compatible entry only, compatibility is declared with "adi,adxl34x" only for now. Signed-off-by:
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