- 26 Sep, 2017 40 commits
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Tony Cheng authored
- move to new programming style - clean up table to make it obvious what we are programming Signed-off-by:
Tony Cheng <tony.cheng@amd.com> Reviewed-by:
Zeyu Fan <Zeyu.Fan@amd.com> Acked-by:
Harry Wentland <Harry.Wentland@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Roman Li authored
Signed-off-by:
Roman Li <Roman.Li@amd.com> Reviewed-by:
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Harry Wentland authored
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Harry Wentland authored
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Wenjing Liu authored
The issue causes hue adjustment for rgb limited range color space programmed wrong. Update calculation formula for rgb limited range Signed-off-by:
Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Joshua Aberback authored
- we don't yet support 3D timings in DAL3 - somehow a code path was being executed that resulted in HW programming for a 3D timing, which caused 3D displays to show half the desktop in one frame, and the other half of the desktop in the next frame - blocking all 3D timings in timing generator validation until we implement proper 3D timing support Signed-off-by:
Joshua Aberback <Joshua.Aberback@amd.com> Reviewed-by:
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jimqu authored
temp_flip_context is always same as current_context, and the current_context will be freed in dc_commit_targets(), but temp_flip_context will be used in dc_update_surfaces_for_target(). Signed-off-by:
JimQu <Jim.Qu@amd.com> Reviewed-by:
Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> Acked-by:
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Zeyu Fan authored
Signed-off-by:
Jordan Lazare <Jordan.Lazare@amd.com> Signed-off-by:
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Zeyu Fan authored
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Alex Deucher authored
Now that the mc_access functions are gone, we no longer need separate structs for all the different dce families in dm. Signed-off-by: -
Harry Wentland authored
Supported DCE versions: 8.0, 10.0, 11.0, 11.2 v2: rebase against 4.11 Signed-off-by:
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Harry Wentland authored
This is needed to ensure every single DC commit builds. Reverting this again when it's no longer needed by DC. This reverts commit 98da65d5. Signed-off-by:
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Alex Deucher authored
It was not clear. The rest of the driver is MIT/X11. Reviewed-by:
Christian König <christian.koenig@amd.com> Acked-by:
Dave Airlie <airlied@redhat.com> Signed-off-by:
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Samuel Li authored
v2: drop hdp invalidate/flush. v3: honor pgoff during prime mmap. Add a barrier after cpu access. v4: drop begin/end_cpu_access() for now, revisit later. Signed-off-by:
Samuel Li <Samuel.Li@amd.com> Reviewed-by:
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Rex Zhu authored
Reviewed-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
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Rex Zhu authored
repeated defining in hwmgr.h Reviewed-by:
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Rex Zhu authored
repeated defining in hwmgr.h use PHM_WAIT_INDIRECT_FIELD instand. Reviewed-by:
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Rex Zhu authored
repeated defining in hwmgr.h Reviewed-by:
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Rex Zhu authored
repeated defining in hwmgr.h Reviewed-by:
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Rex Zhu authored
repeated defining in hwmgr.h Reviewed-by:
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Rex Zhu authored
repeated defining in hwmgr.h Reviewed-by:
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Rex Zhu authored
the macro is as same as PHM_WRITE_FIELD Reviewed-by:
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Rex Zhu authored
the macro is as same as PHM_WRITE_INDIRECT_FIELD Reviewed-by:
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Rex Zhu authored
the macro is not relevant to SMU, so rename SMU_WAIT_FIELD_UNEQUAL to PHM_WAIT_FIELD_UNEQUAL and move to hwmgr.h Reviewed-by:
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Rex Zhu authored
the macro is not relevant to SMU, so move to hwmgr.h and rename to PHM_WAIT_VFPF_INDIRECT_FIELD Reviewed-by:
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Rex Zhu authored
the macro is not relevant to SMU, so move to hwmgr.h and rename to PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL Reviewed-by:
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Rex Zhu authored
the macro is not relevent to SMU, so move to hwmgr.h and rename to PHM_WAIT_INDIRECT_FIELD_UNEQUAL Reviewed-by:
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Rex Zhu authored
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Rex Zhu authored
in VFPF macros to support virtualization Reviewed-by:
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Rex Zhu authored
delete struct smumgr, put smu backend function table in struct hwmgr Reviewed-by:
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Rex Zhu authored
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Rex Zhu authored
unify to use struct hwmgr as function parameter in smumgr. Reviewed-by:
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Christian König authored
Just set the CPU access required flag when we pin it. Signed-off-by:
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Monk Liu authored
this fix memory leak due to request_firmware after driver unloaded v2: release gmc firmware for gmc6/7/8 as well Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Reviewed-by:
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Monk Liu authored
fix missing finish uvd enc_ring. v2: since the adev pointer check in already in ring_fini so drop the check outsider Signed-off-by:
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Monk Liu authored
this way after KIQ MQD released in drv unloading, CPC can still let KIQ access this MQD thus RLCV SAVE_VF will not fail v2: always use VRAM domain for KIQ MQD no matter BM or SRIOV Signed-off-by:
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Monk Liu authored
v2: move kcq_disable out of SRIOV, make it genearal Signed-off-by:
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Monk Liu authored
only with this way we can debug the VMC page fault issue Signed-off-by:
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Yong Zhao authored
Use it to replace the hard coded value in amdgpu_vm_bo_update_mapping(). Signed-off-by:
Yong Zhao <yong.zhao@amd.com> Reviewed-by:
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Yong Zhao authored
When max_bytes is not 8 bytes aligned and bo size is larger than max_bytes, the last 8 bytes in a ttm node may be left unchanged. For example, on pre SDMA 4.0, max_bytes = 0x1fffff, and the bo size is 0x200000, the problem will happen. In order to fix the problem, we separately store the max nums of PTEs/PDEs a single operation can set in amdgpu_vm_pte_funcs structure, rather than inferring it from bytes limit of SDMA constant fill, i.e. fill_max_bytes. Together with the fix, we replace the hard code value "10" in amdgpu_vm_bo_update_mapping() with the corresponding values from structure amdgpu_vm_pte_funcs. Signed-off-by:
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