- 25 Jan, 2020 2 commits
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Olof Johansson authored
Merge tag 'omap-for-v5.6/dt-late-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/late Late omap dts changes for v5.6 merge window This series of changes mostly configures the cameras for dra7 and am437x that have been pending for few months now because of waiting for clock dependencies to clear. So these changes are based on earlier dts changes with with Tero Kristo's for-5.6-ti-clk branch merged in. Then there's a series of changes to configure powervr sgx target module for am335x, am437x and dra7 that have been waiting to have the rstctrl reset driver dependencies to clear. Also included are few minor patches to configure 1-wire and coulomb counter calibration interrupt for droid4. * tag 'omap-for-v5.6/dt-late-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (25 commits) ARM: dts: omap4-droid4: Enable hdq for droid4 ds250x 1-wire battery nvmem ARM: dts: motorola-cpcap-mapphone: Configure calibration interrupt ARM: dts: Configure interconnect target module for am437x sgx ARM: dts: Configure sgx for dra7 ARM: dts: Configure rstctrl reset for am335x SGX ARM: dts: dra7: Add ti-sysc node for VPE ARM: dts: dra7: add vpe clkctrl node ARM: dts: am43x-epos-evm: Add VPFE and OV2659 entries ARM: dts: am437x-sk-evm: Add VPFE and OV2659 entries ARM: dts: am43xx: add support for clkout1 clock arm: dts: dra76-evm: Add CAL and OV5640 nodes arm: dtsi: dra76x: Add CAL dtsi node arm: dts: dra72-evm-common: Add entries for the CSI2 cameras ARM: dts: DRA72: Add CAL dtsi node ARM: dts: dra7-l4: Add ti-sysc node for CAM ARM: OMAP: DRA7xx: Make CAM clock domain SWSUP only ARM: dts: dra7: add cam clkctrl node ARM: dts: Add omap3-echo ARM: dts: Add dtsi files for AM3703, AM3715 and DM3725 ARM: dts: am335x-icev2: Add support for OSD9616P0899-10 at i2c0 ... Link: https://lore.kernel.org/r/pull-1579896427-50330@atomide.com-3Signed-off-by:
Olof Johansson <olof@lixom.net>
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Olof Johansson authored
Merge tag 'omap-for-v5.6/ti-sysc-drop-pdata-crypto-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/late Late changes for omap secure accelerators for v5.6 merge window A series of changes to configure secure accelerators for omap4 & 5 to finally get hardware random number generator working. Apologies on a late pull request on these changes, but this pull request could not be sent out earlier because of a dependency to recent clock changes. This is based on earlier changes to drop omap legacy platform data with Tero Kristo's for-5.6-ti-clk branch merged in. * tag 'omap-for-v5.6/ti-sysc-drop-pdata-crypto-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (98 commits) ARM: OMAP2+: Drop legacy platform data for omap4 des ARM: OMAP2+: Drop legacy platform data for omap4 sham ARM: OMAP2+: Drop legacy platform data for omap4 aes ARM: dts: Configure interconnect target module for omap4 des ARM: dts: Configure interconnect target module for omap4 aes ARM: dts: Configure interconnect target module for omap4 sham ARM: dts: Configure omap5 rng to probe with ti-sysc ARM: dts: Configure omap4 rng to probe with ti-sysc ARM: dts: Add missing omap5 secure clocks ARM: dts: Add missing omap4 secure clocks clk: ti: clkctrl: Fix hidden dependency to node name clk: ti: add clkctrl data dra7 sgx clk: ti: omap5: Add missing AESS clock clk: ti: dra7: fix parent for gmac_clkctrl clk: ti: dra7: add vpe clkctrl data clk: ti: dra7: add cam clkctrl data dt-bindings: clock: Move ti-dra7-atl.h to dt-bindings/clock dmaengine: ti: omap-dma: don't allow a null od->plat pointer to be dereferenced ARM: OMAP2+: Drop legacy platform data for sdma ARM: OMAP2+: Drop legacy init for sdma ... Link: https://lore.kernel.org/r/pull-1579896427-50330@atomide.com-2Signed-off-by:
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- 23 Jan, 2020 29 commits
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Tony Lindgren authored
With "[PATCHv3] w1: omap-hdq: Simplify driver with PM runtime autosuspend" we can read the droid4 battery information over 1-wire with this patch with something like: # modprobe omap_hdq # hd /sys/bus/w1/devices/89-*/89-*/nvmem ... Unfortunately the format of the battery data seems to be Motorola specific and is currently unusable for battery charger unless somebody figures out what it means. Note that currently keeping omap_hdq module loaded will cause extra power consumption as it seems to scan devices periodically. Cc: Merlijn Wajer <merlijn@wizzup.org> Cc: Pavel Machek <pavel@ucw.cz> Acked-by:
Pavel Machek <pavel@ucw.cz> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Tony Lindgren authored
We added coulomb counter calibration support With commit 0cb90f07 ("power: supply: cpcap-battery: Add basic coulomb counter calibrate support"), but we also need to configure the related interrupt. Without the interrupt calibration happens based on a timeout after two seconds, with the interrupt the calibration just gets done a bit faster. Cc: Merlijn Wajer <merlijn@wizzup.org> Cc: Pavel Machek <pavel@ucw.cz> Acked-by:
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Tony Lindgren authored
This seems to be similar to what we have for am335x. The following can be tested via sysfs with the to ensure the SGX module gets enabled and disabled properly: # echo on > /sys/bus/platform/devices/5600fe00.target-module/power/control # rwmem 0x5600fe00 # revision register 0x5600fe00 = 0x40000000 # echo auto > /sys/bus/platform/devices/5600fe00.target-module/power/control # rwmem 0x5000fe00 Bus error Note that this patch depends on the PRM rstctrl driver that has been recently posted. If the child device driver(s) need to prevent rstctrl reset on PM runtime suspend, the drivers need to increase the usecount for the shared rstctrl reset that can be mapped also for the child device(s) or accessed via dev->parent. Cc: Adam Ford <aford173@gmail.com> Cc: Filip Matijević <filip.matijevic.pz@gmail.com> Cc: "H. Nikolaus Schaller" <hns@goldelico.com> Cc: Ivaylo Dimitrov <ivo.g.dimitrov.75@gmail.com> Cc: moaz korena <moaz@korena.xyz> Cc: Merlijn Wajer <merlijn@wizzup.org> Cc: Paweł Chmiel <pawel.mikolaj.chmiel@gmail.com> Cc: Philipp Rossak <embed3d@gmail.com> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: -
Tony Lindgren authored
I've tested that the interconnect target module enables and idles just fine when probed with ti-sysc with PM runtime control via sys: # echo on > $(find /sys -name control | grep \/5600) # rwmem 0x5600fe00 # OCP Revision 0x5600fe00 = 0x40000000 # echo auto > $(find /sys -name control | grep \/5600) Cc: "H. Nikolaus Schaller" <hns@goldelico.com> Cc: Robert Nelson <robertcnelson@gmail.com> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: -
Tony Lindgren authored
The following can be tested via sysfs with the following to ensure the SGX module gets enabled and disabled properly: # echo on > /sys/bus/platform/devices/5600fe00.target-module/power/control # rwmem 0x5600fe00 # revision register 0x5600fe00 = 0x40000000 # echo auto > /sys/bus/platform/devices/5600fe00.target-module/power/control # rwmem 0x5000fe00 Bus error Note that this patch depends on the PRM rstctrl driver that has been recently posted. If the child device driver(s) need to prevent rstctrl reset on PM runtime suspend, the drivers need to increase the usecount for the shared rstctrl reset that can be mapped also for the child device(s) or accessed via dev->parent. Cc: Adam Ford <aford173@gmail.com> Cc: Filip Matijević <filip.matijevic.pz@gmail.com> Cc: "H. Nikolaus Schaller" <hns@goldelico.com> Cc: Ivaylo Dimitrov <ivo.g.dimitrov.75@gmail.com> Cc: moaz korena <moaz@korena.xyz> Cc: Merlijn Wajer <merlijn@wizzup.org> Cc: Paweł Chmiel <pawel.mikolaj.chmiel@gmail.com> Cc: Philipp Rossak <embed3d@gmail.com> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: -
Tony Lindgren authored
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Benoit Parrot authored
Add VPE node as a child of l4 interconnect in order for it to probe using ti-sysc. Signed-off-by:
Benoit Parrot <bparrot@ti.com> Signed-off-by:
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Benoit Parrot authored
Add clkctrl nodes for VPE module. Note that because of the current dts node name dependency for mapping to clock domain, we must still use "vpe-clkctrl@" naming instead of generic "clock@" naming for the node. And because of this, it's probably best to apply the dts node addition together along with the other clock changes. Signed-off-by:
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Benoit Parrot authored
Add VPFE device nodes entries. Add OmniVision OV2659 sensor device nodes and linkage. Since Rev1.2a on this board the sensor source clock (xvclk) has a dedicated 12Mhz oscillator instead of using clkout1. Add 'audio_mstrclk' fixed clock object to represent it. Signed-off-by:
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Benoit Parrot authored
Add VPFE device nodes entries. Add OmniVision OV2659 sensor device nodes and linkage. The sensor clock (xvclk) is sourced from clkout1. Add clock entries to properly select clkout1 and set its parent clock to sys_clkin_ck. Signed-off-by:
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Tero Kristo authored
clkout1 clock node and its generation tree was missing. Add this based on the data on TRM and PRCM functional spec. commit 664ae1ab ("ARM: dts: am43xx: add clkctrl nodes") effectively reverted this commit 8010f13a ("ARM: dts: am43xx: add support for clkout1 clock") which is needed for the ov2659 camera sensor clock definition hence it is being re-applied here. Note that because of the current dts node name dependency for mapping to clock domain, we must still use "clkout1-*ck" naming instead of generic "clock@" naming for the node. And because of this, it's probably best to apply the dts node addition together along with the other clock changes. Fixes: 664ae1ab ("ARM: dts: am43xx: add clkctrl nodes") Signed-off-by:
Tero Kristo <t-kristo@ti.com> Tested-by:
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Benoit Parrot authored
Add device nodes for CSI2 camera board OV5640. Add the CAL port nodes with the necessary linkage to the ov5640 nodes. Signed-off-by:
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Benoit Parrot authored
Add the required dtsi node to support the Camera Adaptation Layer (CAL) for the DRA76 family of devices. Signed-off-by:
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Benoit Parrot authored
Add device nodes for CSI2 camera board OV5640. Add the CAL port nodes with the necessary linkage to the ov5640 nodes. Signed-off-by:
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Benoit Parrot authored
This patch adds the required dtsi node to support the Camera Adaptation Layer (CAL) for the DRA72 family of devices. Signed-off-by:
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Benoit Parrot authored
Add CAM nodes as a child of l4 interconnect in order for it to probe using ti-sysc. Signed-off-by:
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Benoit Parrot authored
Both CAL and VIP rely on this clock domain. But CAL DPHY require LVDSRX_96M_GFCLK to be active. When this domain is set to HWSUP the LVDSRX_96M_GFCLK is on;y active when VIP1 clock is also active. If only CAL on DRA72x (which uses the VIP2 clkctrl) probes the CAM domain is enabled but the LVDSRX_96M_GFCLK is left gated. Since LVDSRX_96M_GFCLK is sourcing the input clock to the DPHY then actual frame capture cannot start as the phy are inactive. So we either have to also enabled VIP1 even if we don't intend on using it or we need to set the CAM domain to use SWSUP only. This patch implements the latter. Signed-off-by:
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Benoit Parrot authored
Add clkctrl nodes for CAM domain. Note that because of the current dts node name dependency for mapping to clock domain, we must still use "cam-clkctrl@" naming instead of generic "clock@" naming for the node. And because of this, it's probably best to apply the dts node addition together along with the other clock changes. Signed-off-by:
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Tony Lindgren authored
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Tony Lindgren authored
We can now probe devices with ti-sysc interconnect driver and dts data. Let's drop the related platform data and custom ti,hwmods dts property. As we're just dropping data, and the early platform data init is based on the custom ti,hwmods property, we want to drop both the platform data and ti,hwmods property in a single patch. Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by: -
Tony Lindgren authored
We can now probe devices with ti-sysc interconnect driver and dts data. Let's drop the related platform data and custom ti,hwmods dts property. As we're just dropping data, and the early platform data init is based on the custom ti,hwmods property, we want to drop both the platform data and ti,hwmods property in a single patch. Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by: -
Tony Lindgren authored
We can now probe devices with ti-sysc interconnect driver and dts data. Let's drop the related platform data and custom ti,hwmods dts property. As we're just dropping data, and the early platform data init is based on the custom ti,hwmods property, we want to drop both the platform data and ti,hwmods property in a single patch. Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by: -
Tony Lindgren authored
We can now probe devices with device tree only configuration using ti-sysc interconnect target module driver. Let's configure the module, but keep the legacy "ti,hwmods" peroperty to avoid new boot time warnings. The legacy property will be removed in later patches together with the legacy platform data. Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by: -
Tony Lindgren authored
We can now probe devices with device tree only configuration using ti-sysc interconnect target module driver. Let's configure the module, but keep the legacy "ti,hwmods" peroperty to avoid new boot time warnings. The legacy property will be removed in later patches together with the legacy platform data. Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by: -
Tony Lindgren authored
We can now probe devices with device tree only configuration using ti-sysc interconnect target module driver. Let's configure the module, but keep the legacy "ti,hwmods" peroperty to avoid new boot time warnings. The legacy property will be removed in later patches together with the legacy platform data. Cc: Tero Kristo <t-kristo@ti.com> Signed-off-by: -
Tony Lindgren authored
This is similar to dra7 and omap4 with different clock naming and module address. Cc: devicetree@vger.kernel.org Cc: Rob Herring <robh+dt@kernel.org> Signed-off-by: -
Tony Lindgren authored
Add RNG interconnect data for omap4 similar to what dra7 has. The clock is OMAP4_CM_L4SEC_RNG_CLKCTRL_OFFSET at offset address 0x01c0, which matches what dra7 also has with DRA7_L4SEC_CLKCTRL_INDEX(0x1c0). Note that we need to also add the related l4_secure clock entries. I've only added RNG, the others can be added as they get tested. They are probably very similar to what we already have for dra7 in dra7_l4sec_clkctrl_regs[]. With the clock tagged CLKF_SOC_NONSEC, clock is set disabled for secure devices and clk_get() will fail. Additionally we disable the RNG target module on droid4 to avoid introducing new boot time warnings. Cc: devicetree@vger.kernel.org Cc: Rob Herring <robh+dt@kernel.org> Signed-off-by: -
Tony Lindgren authored
The secure clocks on omap5 are similar to what we already have for dra7 with dra7_l4sec_clkctrl_regs and documented in the omap5432 TRM in "Table 3-1044. CORE_CM_CORE Registers Mapping Summary". The secure clocks are part of the l4per clock manager. As the l4per clock manager has now two clock domains as children, let's also update the l4per clockdomain node name to follow the "clock" node naming with a domain specific compatible property. Compared to omap4, omap5 has more clocks working in hardare autogating mode. Cc: devicetree@vger.kernel.org Cc: Rob Herring <robh+dt@kernel.org> Acked-by:
Stephen Boyd <sboyd@kernel.org> Signed-off-by:
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Tony Lindgren authored
The secure clocks on omap4 are similar to what we already have for dra7 in dra7_l4sec_clkctrl_regs and documented in the omap4460 TRM "Table 3-1346 L4PER_CM2 Registers Mapping Summary". The secure clocks are part of the l4_per clock manager. As the l4_per clock manager has now two clock domains as children, let's also update the l4_per clockdomain node name to follow the "clock" node naming with a domain specific compatible property. Cc: devicetree@vger.kernel.org Cc: Rob Herring <robh+dt@kernel.org> Acked-by:
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- 20 Jan, 2020 7 commits
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Tony Lindgren authored
We currently have a hidden dependency to the device tree node name for the clkctrl clocks. Instead of using standard node name like "clock", we must use "l4-per-clkctrl" type naming so the clock driver can find the associated clock domain. Further, if "clk" is specified for a clock node name, the driver sets TI_CLK_CLKCTRL_COMPAT flag that uses different logic for the clock name based on the parent node name for the all the clkctrl clocks for the SoC. If the clock node naming dependency is not understood, the related clockdomain is not found, or a wrong one can get used if a clock manager has multiple clock domains. As each clkctrl instance represents a single clock domain, let's allow using domain specific compatible names to specify the clock domain. This simplifies things and removes the hidden dependency to the node name. And then later on, after the node names have been standardized, we can drop the related code for parsing the node names. Let's also update the binding to use standard "clock" node naming instead of "clk" and add the missing description for reg. Cc: devicetree@vger.kernel.org Cc: Rob Herring <robh+dt@kernel.org> Signed-off-by:
Rob Herring <robh@kernel.org> Acked-by:
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Tony Lindgren authored
This is similar to what we have for omap5 except the gpu_cm address is different, the mux clocks have one more source option, and there's no divider clock. Note that because of the current dts node name dependency for mapping to clock domain, we must still use "gpu-clkctrl@" naming instead of generic "clock@" naming for the node. And because of this, it's probably best to apply the dts node addition together along with the other clock changes. For accessing the GPU, we also need to configure the interconnect target module for GPU similar to what we have for omap5, I'll send that change separately. Cc: Benoit Parrot <bparrot@ti.com> Cc: "H. Nikolaus Schaller" <hns@goldelico.com> Cc: Robert Nelson <robertcnelson@gmail.com> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by:
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Tony Lindgren authored
Looks like we're missing AESS clock for omap5. This is similar to what omap4 has. Cc: H. Nikolaus Schaller <hns@goldelico.com> Cc: Matthijs van Duin <matthijsvanduin@gmail.com> Cc: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by:
Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by:
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Grygorii Strashko authored
The parent clk for gmac clk ctrl has to be gmac_main_clk (125MHz) instead of dpll_gmac_ck (1GHz). This is caused incorrect CPSW MDIO operation. Hence, fix it. Fixes: dffa9051 ('clk: ti: dra7: add new clkctrl data') Signed-off-by:
Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by:
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Benoit Parrot authored
Add clkctrl data for VPE. Signed-off-by:
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Benoit Parrot authored
Add clkctrl data for CAM domain. Signed-off-by:
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Peter Ujfalusi authored
Most of the clock related dt-binding header files are located in dt-bindings/clock folder. It would be good to keep all the similar header files at a single location. Suggested-by:
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- 13 Jan, 2020 2 commits
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André Hentschel authored
This is the first generation Amazon Echo from 2016. Audio support is not yet implemented. Signed-off-by:
André Hentschel <nerv@dawncrow.de> Signed-off-by:
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André Hentschel authored
DM3730 is considered as omap36xx.dtsi, while the rest has: DM3730 | DM3725 | AM3715 | AM3703 IVA X | X | | SGX X | | X | Where X is "supported" Signed-off-by:
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