- 01 Sep, 2017 6 commits
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Ville Syrjälä authored
Pass the correct new crtc state to intel_update_pipe_config() instead of using crtc->state. Reviewed-by:
Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170823152226.22938-6-ville.syrjala@linux.intel.com
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Ville Syrjälä authored
Dig up the appropriate new crtc and plane states from the top level atomic state in intel_pre_plane_update() and intel_post_plane_update(). Reviewed-by:
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Ville Syrjälä authored
Eliminate plane->state and crtc->state usage from intel_plane_atomic_check_with_state() and its callers. Instead pass the proper states in or dig them up from the top level atomic state. Note that intel_plane_atomic_check_with_state() itself isn't allowed to use the top level atomic state as there is none when it gets called from the legacy cursor short circuit path. v2: Rename some variables for easier comprehension (Maarten) Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by:
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Lionel Landwerlin authored
We can now make use of the intel_device_info.gt field. Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by:
Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20170830161208.29221-4-lionel.g.landwerlin@intel.com
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Lionel Landwerlin authored
As recommended by Chris. v2: Switch from __initdata to __initconst. Signed-off-by:
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Lionel Landwerlin authored
Up to Coffeelake we could deduce this GT number from the device ID. This doesn't seem to be the case anymore. This change reorders pciids per GT and adds a gt field to intel_device_info. We set this field on the following platforms : - SNB/IVB/HSW/BDW/SKL/KBL/CFL/CNL Before & After : $ modinfo drivers/gpu/drm/i915/i915.ko | grep ^alias | wc -l 209 v2: Add SNB & IVB (Chris) v3: Fix compilation error in early-quirks (Lionel) v4: Fix inconsistency between FEATURE/PLATFORM macros (Ville) Signed-off-by:
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- 31 Aug, 2017 18 commits
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Manasi Navare authored
This patch fixes the DP AUX CH timeouts observed during CI runs causing CI Failures on a specific PCI device. This issue was fixed previously by adding a quirk but looks like we need to increase this delay even more in order to get rid all the DP AUX CH timeouts. Fixes: c99a259b ("drm/i915/edp: Add a T12 panel delay quirk to fix DP AUX CH timeouts") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101144Signed-off-by:
Manasi Navare <manasi.d.navare@intel.com> Cc: Clinton Taylor <clinton.a.taylor@intel.com> Cc: Daniel Vetter <daniel.vetter@intel.com> Cc: Tomi Sarvela <tomi.p.sarvela@intel.com> Signed-off-by:
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Ville Syrjälä authored
Use explicit old/new states instead of relying on obj->state. Reviewed-by:
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Ville Syrjälä authored
Pass the appropriate new crtc state explicitly to intel_pipe_update_start/end() instead of of mucking around with crtc->state. v2: The mmio flip stuff is gone Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> #v1 Signed-off-by:
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Ville Syrjälä authored
In an effort to eliminate the obj->state usage let's pass on the new crtc state pointer (which we already have!) to the color management code. Reviewed-by:
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Ville Syrjälä authored
Currently the .modeset_calc_cdclk() hooks check the final cdclk value against the max allowed. That's not really sufficient since the low level calc_cdclk() functions effectively clamp the minimum required cdclk to the max supported by the platform. Hence if the minimum required exceeds the platforms capabilities we'd keep going anyway using the max cdclk frequency. To fix that let's move the check earlier into intel_crtc_compute_min_cdclk() and we'll check the minimum required cdclk of the pipe against the maximum supported by the platform. Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by:
Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
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Ville Syrjälä authored
Make the min_pixclk thing less confusing by changing it to track the minimum acceptable cdclk frequency instead. This means moving the application of the guardbands to a slightly higher level from the low level platform specific calc_cdclk() functions. The immediate benefit is elimination of the confusing 2x factors on GLK/CNL+ in the audio workarounds (which stems from the fact that the pipes produce two pixels per clock). v2: Keep cdclk higher on CNL to workaround missing DDI clock voltage handling v3: Squash with the CNL cdclk limits patch (DK) v4: s/intel_min_cdclk/intel_pixel_rate_to_cdclk/ (DK) Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by:
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Rodrigo Vivi authored
On clock recovery this function is called to find out the max voltage swing level that we could go. However gen 9 functions use the old buffer translation tables to figure that out. That table is not valid for CNL causing an invalid number of entries and an invalid selection on the max voltage swing level. v2: Let's use same approach that previous platforms. v3: Actually use n_entries and avoid duplicated -1. v4: Avoid cnl_max_level and use current style. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Clint Taylor <clinton.a.taylor@intel.com> Signed-off-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by:
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Rodrigo Vivi authored
Let's get a proper HDMI DDI entry level for vswing programming sequences on CNL. Spec doesn't specify any default for HDMI tables, so let's pick the last entry as the default for now. Signed-off-by:
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Rodrigo Vivi authored
No functional changes. But those functions will be needed to get max level for HDMI and DP, so let's move those up closer to other similar functions existent for previous platforms. Signed-off-by:
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Rodrigo Vivi authored
Let's start converging CNL buf translations to same style used on previous platforms. So first thing is to use the standard signature so we don't need to propagate the voltage check into other parts of the code, but only on the parts that it is really useful. Signed-off-by:
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Rodrigo Vivi authored
Sequences for DisplayPort asks us to " Configure voltage swing and related IO settings. Refer to DDI Buffer section." before "Configure and enable DDI_BUF_CTL" On BXT and CNL this means to execute the ddi vswing sequences. At this point these sequences calls are getting duplicated for DP because they are all called from DP link trainning sequences. However this patch is not yet removing it before a futher discussion since spec also allows that during link training without disabling anything: " Notes Changing voltage swing during link training: Change the swing setting following the DDI Buffer section. The port does not need to be disabled. " Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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Rodrigo Vivi authored
Vswing sequences on BXT and CNL are equivalent to the ddi buffer registers setting on other platforms. For some reason it got aligned with skl_ddi_set_iboost what is semantically incorrect. This forced us to keep skipping ddi buffer translation tables on the platforms that has the vswing sequences. v2: Don't mess with DP signal levels on this patch. Cc: Vandana Kannan <vandana.kannan@intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Ander Conselvan de Oliveira <conselvan2@gmail.com> Signed-off-by:
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Rodrigo Vivi authored
Let's decouple bxt, glk and cnl dp signal levels from other DDIs to avoid confusion. No functional change. Only a reorg to avoid messing with currently working DP signal levels when moving voltage swing sequences around to match spec. v2: ddi_signal_levels is also called from other ddi platforms, so don't remove IS_GEN9_BC check from skl_ddi_set_iboos. (Ville). Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: -
Rodrigo Vivi authored
No functional changes. This only moves the DP level selection to a separated function that will be later used to organize better the vswing sequences. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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Rodrigo Vivi authored
Driver’s CPU access to GTT is via the GTTMMADR BAR. The current HW implementation of that BAR is to only support <= DW (and maybe QW) writes—not 16/32/64B writes that could occur with WC and/or SSE/AVX moves. GTTMMADR must be marked uncacheable (UC). Accesses to GTTMMADR(GTT), must be 64 bits or less (ie. 1 GTT entry). v2: Get clarification on the reasons and spec is getting updated to reflect it now. Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Suggested-by:Ben Widawsky <benjamin.widawsky@intel.com> Signed-off-by:
Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170829230907.21363-1-rodrigo.vivi@intel.com
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Rodrigo Vivi authored
On CNL B0 stepping GAM is not able to detect some deadlock condition and then rise the rise the gam_coh_flush. WA database and spec both mentions to set 4AB8[24]=1 as workaround. Although register offset 0x4AB8 is not documented for any platform. References: HSD#1945815, BSID#1112 Cc: Mika Kuoppala <mika.kuoppala@intel.com> Signed-off-by:
Mika Kuoppala <mika.kuoppala@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170829230751.21047-1-rodrigo.vivi@intel.com
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Rodrigo Vivi authored
WA to enable HW L1 Banking fix that allows aniso to operate at full sample rate. References: HSD#1937670 Cc: Mika Kuoppala <mika.kuoppala@intel.com> Cc: Oscar Mateo <oscar.mateo@intel.com> Cc: Ben Widawsky <ben@bwidawsk.net> Cc: Anuj Phogat <anuj.phogat@intel.com> Signed-off-by:
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Rodrigo Vivi authored
No functional changes. Our code was only a bit messy with mixed style there so let's clean up a bit using the short codenames for the platforms. Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170829052026.15038-1-rodrigo.vivi@intel.com
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- 30 Aug, 2017 3 commits
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Ville Syrjälä authored
The CCS won't have the same stride as the main surface anyway so trying to guard against the fence stride not matching the CCS stride is not sensible. Just skip the fence vs. fb alignment check for the aux plane. Cc: Ben Widawsky <ben@bwidawsk.net> Cc: Jason Ekstrand <jason@jlekstrand.net> Cc: Daniel Stone <daniels@collabora.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170824191100.10949-3-ville.syrjala@linux.intel.comReviewed-by:
Ben Widawsky <ben@bwidawsk.net> Fixes: 2e2adb05 ("drm/i915: Add render decompression support") Signed-off-by:
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Ville Syrjälä authored
Userspace wants to treat fb->offsets[] as raw byte offsets into the gem bo. Adjust the kernel code to match. Cc: Ben Widawsky <ben@bwidawsk.net> Cc: Jason Ekstrand <jason@jlekstrand.net> Cc: Daniel Stone <daniels@collabora.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170824191100.10949-2-ville.syrjala@linux.intel.comAcked-by:
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Chris Wilson authored
Since we hold the device wakeref when writing through the GTT (otherwise the writes would fail), we presumed that before the device sleeps those writes would naturally be flushed and that we wouldn't need our mmio read trick. However, that presumption seems false and a sleepy bxt seems to require us to always manually flush the GTT writes prior to direct access. Fixes: e2a2aa36 ("drm/i915: Check we have an wake device before flushing GTT writes") Signed-off-by:
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- 29 Aug, 2017 6 commits
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Chris Wilson authored
If we fail to clear the outstanding request queue before suspending, mark those requests as lost. References: https://bugs.freedesktop.org/show_bug.cgi?id=102037Signed-off-by:
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Chris Wilson authored
When we wake up from suspend, the device has been powered down and should come back afresh. We should be able to safely remove the wedged status from the previous session and start afresh. Signed-off-by:
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Chris Wilson authored
When we do a locked idle we know that afterwards all requests have been completed and the engines have been cleared of tasks. For whatever reason, this doesn't always happen and we may go into a suspend with ELSP still full, and this causes an issue upon resume as we get very, very confused. If the engines refuse to idle, mark the device as wedged. In the process we get rid of the maybe unused open-coded version of wait_for_engines reported by Nick Desaulniers and Matthias Kaehlcke. v2: Suppress the -EIO before suspend, but keep it for seqno wrap. References: https://bugs.freedesktop.org/show_bug.cgi?id=101891 References: https://bugs.freedesktop.org/show_bug.cgi?id=102456Signed-off-by:
Mika Kuoppala <mika.kuoppala@linux.intel.com>
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Chris Wilson authored
If we are using the cmdparser, we will have to copy the batch and so stall for the relocations. Rather than prolong that stall by adding more relocation requests, just use CPU relocations and do the stall upfront. Signed-off-by:
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Chris Wilson authored
Sometimes we know we are the only user of the bo, but since we take a protective pin_pages early on, an attempt to change the vmap on the object is denied because it is busy. i915_gem_object_pin_map() cannot tell from our single pin_count if the operation is safe. Instead we must pass that information down from the caller in the manner of I915_MAP_OVERRIDE. This issue has existed from the introduction of the mapping, but was never noticed as the only place where this conflict might happen is for cached kernel buffers (such as allocated by i915_gem_batch_pool_get()). Until recently there was only a single user (the cmdparser) so no conflicts ever occurred. However, we now use it to allocate batches for different operations (using MAP_WC on !llc for writes) in addition to the existing shadow batch (using MAP_WB for reads). We could either keep both mappings cached, or use a different write mechanism if we detect a MAP_WB already exists (i.e. clflush afterwards), but as we haven't seen this issue in the wild (it requires hitting the GPU reloc path in addition to the cmdparser) for simplicity just allow the mappings to be recreated. v2: Include the i915_MAP_OVERRIDE bit in the enum so the compiler knows about all the valid values. Fixes: 7dd4f672 ("drm/i915: Async GPU relocation processing") Testcase: igt/gem_lut_handle # byt, completely by accident Signed-off-by:
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Chris Wilson authored
CHECK drivers/gpu/drm/i915/intel_display.c drivers/gpu/drm/i915/intel_display.c:3753 intel_finish_reset() warn: inconsistent indenting Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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- 28 Aug, 2017 5 commits
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Marta Lofstedt authored
Commit 6e644626 ("drm/i915: Beef up the IPS vs. CRC workaround") was supposed to solve below bug. However, the patch I tested is not the same as the one that got merged. With this addition the test pass. V2: removed unused: "struct intel_crtc *intel_crtc" Fixes: 6e644626 ("drm/i915: Beef up the IPS vs. CRC workaround") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101664Signed-off-by:
Marta Lofstedt <marta.lofstedt@intel.com> Signed-off-by:
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Jani Nikula authored
Copy over some fields defined in the intel_vbt_decode tool. No functional changes. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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Jani Nikula authored
Copy over some fields defined in the intel_vbt_decode tool. No functional changes. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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Jani Nikula authored
Copy over some fields defined in the intel_vbt_tool. No functional changes. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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Jani Nikula authored
This is according to the style all over the place. No functional changes. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Suggested-by:
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- 26 Aug, 2017 2 commits
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Chris Wilson authored
Since we use a worker to enable FBC on the CRTC, it is possible for the CRTC to be switched off before we run. In this case, the CRTC will not allow us to wait upon a vblank, so remove the DRM_ERROR as this is very much expected. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102410 Fixes: ca18d51d ("drm/i915/fbc: wait for a vblank instead of 50ms when enabling") Signed-off-by:
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Praveen Paneri authored
When FBC is enabled for linear, legacy Y-tiled and Yf-tiled surfaces on gen9, the cfb stride must be programmed by SW as cfb_stride = ceiling[(at least plane width in pixels)/ (32 * compression limit factor)] * 8 v2: Minor fix for a build error v3: Fixed subject, register name and platform check (Ville) v4: Added WA details in comment (Paulo) v5: - Read modified reg write to preserve other bit values (Paulo) - Store modified stride value in reg_params (Paulo) - Keep GLK out of the WA (Paulo) v6: - added additional field in reg_params for gen9_wa_cfb_stride (Paulo) - Used appropriate bit mask while writing the register (Paulo) v7 (from Paulo): - Fix coding style and spacing issues. - Mask the old values before writing. - Bikeshed comments and unnecessary checks. Signed-off-by:
Praveen Paneri <praveen.paneri@intel.com> Signed-off-by:
Paulo Zanoni <paulo.r.zanoni@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1502389833-32621-1-git-send-email-praveen.paneri@intel.com
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