- 04 Jun, 2014 8 commits
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Thomas Bogendoerfer authored
- added interrupt support for GIO devices - improved detection of GIO cards on Indigo2 - added more known GIO cards Signed-off-by:
Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7055/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Eunbong Song authored
In octeon_3xxx.dts file, there is a definiton for twsi/twsi2 interrupts. But there is no code for initialization of this interrupts. This patch adds code for initialization of twsi interrupts. Signed-off-by:
Eunbong Song <eunb.song@samsung.com> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6816/Signed-off-by:
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Maciej W. Rozycki authored
There's an alternative 5-line mini interrupt controller in the R4k MB ASIC used on the KN04 and KN05 CPU daughtercards. The controller is cascaded from the CPU interrupt input that would be used for the Halt button on the corresponding R3k systems. This change documents the findings so far. Signed-off-by:
Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/6706/Signed-off-by:
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Maciej W. Rozycki authored
Signed-off-by:
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Steven J. Hill authored
This patch adds support for the microMIPS implementation of the MSA instructions. Signed-off-by:
Steven J. Hill <Steven.Hill@imgtec.com> Reviewed-by:
Paul Burton <Paul.Burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6763/Signed-off-by:
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Daniel Walter authored
Signed-off-by:
Daniel Walter <dwalter@google.com> Cc: linux-kernel@vger.kernel.org Cc: richard@nod.at Cc: akpm@linux-foundation.org Signed-off-by:
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Daniel Walter authored
Signed-off-by:
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Ralf Baechle authored
This keeps the if condition slightly simpler - it's going to become ore complication. Signed-off-by:
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- 02 Jun, 2014 5 commits
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Geert Uytterhoeven authored
All my Sony addresses are defunct. Signed-off-by:
Geert Uytterhoeven <geert@linux-m68k.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6817/Signed-off-by:
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Andreas Herrmann authored
Signed-off-by:
Andreas Herrmann <andreas.herrmann@caviumnetworks.com> Cc: linux-mips@linux-mips.org Cc: David Daney <ddaney.cavm@gmail.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7008/Signed-off-by:
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David Daney authored
Signed-off-by:
David Daney <david.daney@cavium.com> Signed-off-by:
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David Daney authored
Signed-off-by:
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David Daney authored
For para-virtualized guests running under KVM or other equivalent hypervisor. Signed-off-by:
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- 30 May, 2014 27 commits
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David Daney authored
Introduce kvm_hypercall[0-3]. Define three new hypercalls for MIPS: GET_CLOCK_FREQ, EXIT_VM, and CONSOLE_OUTPUT. [andreas.herrmann: * Properly define hypercalls and HC numbers for MIPS in kvm_para.h header files] Signed-off-by: -
Andreas Herrmann authored
Otherwise __builtin_unreachable might be called. Signed-off-by:
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David Daney authored
This returns the CPUNum from the low order Ebase bits. Signed-off-by:
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David Daney authored
These are needed to boot a generic mips64r2 kernel on OCTEONIII. Signed-off-by:
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David Daney authored
The fast handler only supports 64-bit kernels. Signed-off-by:
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David Daney authored
The TLB handlers cannot handle this case, so disable it for now. Signed-off-by:
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David Daney authored
CVMSEG is related to the CPU core not the SoC system. So needs to be configurable there. Signed-off-by:
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David Daney authored
They are a property of the SoC not the CPU itself. Signed-off-by:
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David Daney authored
Some versions of the assembler will not assemble CFC1 for OCTEON, so override the ISA for these. Add r4k_fpu.o to handle low level FPU initialization. Modify octeon_switch.S to save the FPU registers. And include r4k_switch.S to pick up more FPU support. Get rid of "#define cpu_has_fpu 0" Signed-off-by:
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Paul Burton authored
This patch powers down the Malta in response to a power off command (eg. poweroff or shutdown -P). It may then be powered back up by pressing the "ON/NMI" button (S4) on the board. In cases where the power off state cannot be entered (eg. because the required PCI support is disabled) the current reset behaviour will be used as a fallback. Signed-off-by:
James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6907/Signed-off-by:
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Paul Burton authored
When the system is halted it makes little sense to reset it. Instead, hang by executing an infinite loop. [ralf@linux-mips.org: Remove printk from mips_machine_halt() - this is not the place to communicate with the user.] Suggested-by:
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Paul Burton authored
This patch enables the PIIX4 to respond to special cycles on the PCI bus. One such special cycle must be used in order to enter a suspend state, and if response to it is not enabled then the suspend state will never be entered. Signed-off-by:
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Paul Burton authored
This patch introduces code which will enter a suspend state via the PIIX4. This can only be done when PCI support is enabled since it requires access to PCI I/O space and the generation of a special cycle on the PCI bus. In cases where PCI is disabled the mips_pm_suspend function will simply always return an error. Signed-off-by:
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Paul Burton authored
This patch simply adds definitions for some I/O registers in the PIIX4 PM device, and the magic data for a special cycle which must occur on the PCI bus in order for the PIIX4 to enter a suspend state. Signed-off-by:
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Maciej W. Rozycki authored
On R4k DECstations the Halt button is wired to the NMI processor input rather than an ordinary interrupt input such as on R3k DECstations. This is possible with a different design of the CPU daughtercard that routes the Halt button line from the baseboard connector. Additionally the interrupt input has been reused for a different purpose on the KN04 and KN05 R4k CPU daughtercards so it is better kept masked. Signed-off-by:
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Maciej W. Rozycki authored
R3k systems have no R4k timer so there's no point in pulling code that's going to be dead. Signed-off-by:
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Maciej W. Rozycki authored
This small update to the previous fix to __delay removes a conditional around the ABI-dependent subtraction operation within an inline asm in favor to the standard <asm/asm.h> LONG_SUBU macro. No change in code produced. Signed-off-by:
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Maciej W. Rozycki authored
Update to commit 9c9b415c [MIPS: Reimplement get_cycles().] On systems were for whatever reasons we can't use the cycle counter, fall back to the c0_random register as an entropy source. It has however a very small range that makes it suitable for random_get_entropy only and not get_cycles. This optimised version compiles to 8 instructions in the fast path even in the worst case of all the conditions to check being variable (including a MFC0 move delay slot that is only required for very old processors): 828: 8cf90000 lw t9,0(a3) 828: R_MIPS_LO16 jiffies 82c: 40057800 mfc0 a1,c0_prid 830: 3c0200ff lui v0,0xff 834: 00a21024 and v0,a1,v0 838: 1040007d beqz v0,a30 <add_interrupt_randomness+0x22c> 83c: 3c030000 lui v1,0x0 83c: R_MIPS_HI16 cpu_data 840: 40024800 mfc0 v0,c0_count 844: 00000000 nop 848: 00409021 move s2,v0 84c: 8ce20000 lw v0,0(a3) 84c: R_MIPS_LO16 jiffies On most targets the sequence will be shorter and on some it will reduce to a single `MFC0 <reg>,c0_count', as all MIPS architecture (i.e. non-legacy MIPS) processors require the CP0 Count register to be present. The only known exception that reports MIPS architecture compliance, but contrary to that lacks CP0 Count is the Ingenic JZ4740 thingy. For broken platforms like that this code requires cpu_has_counter to be hardcoded to 0 (i.e. no variable setting is permitted) so as not to penalise all the other good platforms out there. The asm barrier is required so that the compiler does not pull any potentially costly (cold cache!) `cpu_data' variable access into the fast path. Signed-off-by:
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Ganesan Ramalingam authored
The XLP9XX SoC has an on-chip SATA controller with two ports. Add ahci-init-xlp2.c to initialize the controller, setup the glue logic registers, fixup PCI quirks and setup interrupt ack logic. Signed-off-by:
Ganesan Ramalingam <ganesanr@broadcom.com> Signed-off-by:
Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6913/Signed-off-by:
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Ganesan Ramalingam authored
XLP3XX includes an on-chip SATA controller with 4 ports. The controller needs glue logic initialization and PCI fixup before it can be used with the standard AHCI driver. Signed-off-by:
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Ganesan Ramalingam authored
In XLP9XX, the interrupt routing table for MSI-X has been moved to the PCIe controller's config space from PIC. There are also 32 MSI-X interrupts available per link on XLP9XX. Update XLP MSI/MSI-X code to handle this. Signed-off-by:
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Yonghong Song authored
Add support for the XLP5XX processor which is an 8 core variant of the XLP9XX. Add XLP5XX cases to code which earlier handled XLP9XX. Signed-off-by:
Yonghong Song <ysong@broadcom.com> Signed-off-by:
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Jayachandran C authored
Calculate XLP 9XX and 2XX core frequency from the per-core PLL. This should give the correct value for all board configurations. Signed-off-by:
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Ganesan Ramalingam authored
Update PIC frequency calculation for XLP9XX and 2XX processors using the correct PLL registers. This should work for all possible board configurations. Signed-off-by:
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Jayachandran C authored
Add the compatible property to the PIC entry. Also fix up the nodename to use the correct address. Signed-off-by:
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Jayachandran C authored
Use PRID_IMP_MASK macro instead of 0xff00 to extract the processor type. Signed-off-by:
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Jayachandran C authored
Add IRQ to IRT (PIC interupt table index) mapping for SATA, GPIO, NAND and SPI interfaces on the XLP SoC. Fix offsets for few blocks and add device IDs for a few blocks. Signed-off-by:
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