Merge tag 'imx-dt64-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt64

The Freescale arm64 device tree updates for 4.8:
 - Update address-cells and reg properties of cpu nodes, considering
   MPIDR_EL1[63:32] bits are not used for CPUs identification on ls1043a
   and ls2080a
 - Adds the cache nodes and next-level-cache property for ls1043a and
   ls2080a to get cacheinfo work on these platforms
 - Add dma-coherent for ls1043a PCI nodes to utilize the hardware
   capability on data coherency
 - Add dis_rxdet_inp3_quirk property for USB3 device to disable rx
   detection in P3 PHY mode

* tag 'imx-dt64-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  arm64: dts: ls2080a: Add cache nodes for cacheinfo support
  arm64: dts: ls1043a: Add cache nodes for cacheinfo support
  arm64: dts: ls1043a: Add 'dma-coherent' for ls1043a PCI nodes
  bindings: PCI: layerscape: Add 'dma-coherent' property
  arm64: dts: ls1043a: Add dis_rxdet_inp3_quirk property to USB3 node
  arm64: dts: ls2080a: Add dis_rxdet_inp3_quirk property to USB3 node
  arm64: dts: fsl: Update address-cells and reg properties of cpu nodes
Signed-off-by: Olof Johansson <olof@lixom.net>

Merge tag 'qcom-arm64-for-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/dt64

Qualcomm ARM64 Updates for v4.8

* Enable assorted peripherals on APQ8016 SBC
* Update reserved memory on MSM8916
* Add MSM8996 peripheral support
* Add SCM firmware node on MSM8916
* Add PMU node on MSM8916
* Add PSCI cpuidle support on MSM8916

* tag 'qcom-arm64-for-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux: (22 commits)
  arm64: dts: msm8996: add sdc2 support
  arm64: dts: msm8996: add sdc2 pinctrl
  arm64: dts: msm8996: add support to blsp2_spi5
  arm64: dts: msm8996: add support to blsp2_spi5 pinctrl
  arm64: dts: msm8996: add support to blsp1_spi0
  arm64: dts: msm8996: add support to blsp1_spi0 pinctrl
  arm64: dts: msm8996: add support to blsp2_i2c0
  arm64: dts: msm8996: add support to blsp2_i2c0 pinctrl
  arm64: dts: msm8996: add support to blsp2_i2c1
  arm64: dts: msm8996: add blsp2_i2c1 pinctrl
  arm64: dts: msm8996: add support to blsp1_i2c2 device
  arm64: dts: msm8996: add blsp1_i2c2 pinctrl nodes.
  arm64: dts: msm8996: add support blsp2_uart2
  arm64: dts: msm8996: add blsp2_uart2 pinctrl nodes.
  arm64: dts: msm8996: add blsp2_uart1 pinctrl
  arm64: dts: msm8996: add msmgpio label
  ARM: dts: msm8916: Update reserved-memory
  arm64: dts: msm8916: Add SCM firmware node
  arm64: dts: qcom: Add msm8916 PMU node
  ARM64: dts: Add PSCI cpuidle support for MSM8916
  ...
Signed-off-by: Olof Johansson <olof@lixom.net>

First part of X-Gene DTS changes queued for v4.8

The changes include:
+ 2 clean-up and style-fix patches from Bjorn
+ Correct timer interrupt polarity for X-Gene 2
+ Remove unused qmlclk node on X-Gene 1

* tag 'xgene-dts-for-v4.8-part1' of https://github.com/AppliedMicro/xgene-next:
  arm64: dts: apm: Remove unused qmlclk node on X-Gene 1
  arm64: dts: apm: Fix timer interrupt polarity for X-Gene 2 SoC
  arm64: dts: apm: Remove leading '0x' from unit addresses
  arm64: dts: apm: Use lowercase consistently for hex constants
Signed-off-by: Olof Johansson <olof@lixom.net>

This patch adds support to sdc2 sdhci controller, which is used on some
of the boards.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>

This patch adds pinctrl required for sdhci for external sd card
controller.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>

This patch adds support to blsp2_spi5 device, which is used in some of
the APQ8096 based boards.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>

This patch adds pinctrl required for blsp2_spi5 device.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>

This patch adds support to blsp1_spi0 which is used on some of APQ8096
based boards.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>

This patch adds pinctrl nodes required for blsp1_spi0.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>

This patch adds support to blsp2_i2c0, which is used on some of the
APQ8096 based boards.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>

This patch adds support to blsp2_i2c0 pinctrl.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>

This patch adds support to blsp2_i2c1, which is used in one of the
apq8096 based boards.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>

This patch adds support to blsp2_i2c1 pinctrl nodes.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>

This patch adds blsp1_i2c2 support, as this bus is used on some of the
apq8096 boards.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>

This patch adds pinctrl nodes required for blsp1_i2c2.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>

This patch adds bslp2_uart2 node in soc so that boards that use this
uart can enable it.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>

This patch adds blsp2_uart2 pinctrl nodes.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>

This patch adds 2pin and 4 pin uart pinctrl support for blsp2_uart1
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>

This patch adds msmgpio label for pin and gpio controller so that
it can referenced in dedicated pins file and other board level gpios.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>

Adds the cache nodes and next-level-cache property for the
cacheinfo to work.
Signed-off-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Adds the cache nodes and next-level-cache property for the
cacheinfo to work.
Signed-off-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Node qmlclk has no consumer, so remove it.
Signed-off-by: Duc Dang <dhdang@apm.com>

Correct X-Gene 2 timer interrupt polarity as low-level triggered.
Signed-off-by: Duc Dang <dhdang@apm.com>

Unit addresses should not have a leading '0x'.  Remove them.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Duc Dang <dhdang@apm.com>

The convention in these files is to use lowercase for "0x" prefixes and for
the hex constants themselves, but a few changes didn't follow that
convention, which makes the file annoying to read.

Use lowercase consistently for the hex constants.  No functional change
intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Duc Dang <dhdang@apm.com>

This pull request contains Device Tree changes for Broadcom ARM64-based SoCS:

- Anup adds nodes for the AHCI and SATA3 PHY peripherals to the Northstar2 SoCs

- Dhanajay enables pinctrl for the Northstar2 SoCs

- Jon Mason enables all of the UART peripherals found in the NS2 SVK and
  finally adds the CCI-400 and PMU nodes

* tag 'arm-soc/for-4.8/devicetree-arm64' of http://github.com/Broadcom/stblinux:
  arm64: dts: NS2: Add CCI-400 PMU support
  arm64: dts: NS2: Add all of the UARTs
  arm64: dts: Enable GPIO for Broadcom NS2 SoC
  arm64: dts: enable pinctrl for Broadcom NS2 SoC
  arm64: dts: Add SATA3 AHCI and SATA3 PHY DT nodes for NS2
  dt-bindings: ata: add compatible string for iProc AHCI controller
Signed-off-by: Olof Johansson <olof@lixom.net>

Merge tag 'amlogic-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/dt64

Amlogic DT 64-bit changes for v4.8
- add pinctrl driver and pins for several devices
- add reset driver

* tag 'amlogic-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
  ARM64: dts: amlogic: Enable Reset Controller on GXBB-based platforms
  ARM64: dts: amlogic: gxbb: add ethernet
  ARM64: dts: amlogic: gxbb: pinctrl: add/update UART
  ARM64: dts: amlogic: add pins for EMMC, SD
  ARM64: dts: amlogic: Enable pin controller on GXBB-based platforms
  documentation: Add compatibles for Amlogic Meson GXBB pin controllers
  ARM64: dts: amlogic: Add hiu and periphs buses
Signed-off-by: Olof Johansson <olof@lixom.net>

The 'dma-coherent' indicates that the hardware IP block can ensure
the coherency of the data transferred from/to the IP block. This
can avoid the software cache flush/invalid actions, and improve
the performance significantly.

The PCI IP block of ls1043a has this capability, so adding this
feature to improve the PCI performance.
Signed-off-by: Liu Gang <Gang.Liu@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Add 'dma-coherent' description for PCI nodes.

The 'dma-coherent' indicates that the hardware IP block can ensure
the coherency of the data transferred from/to the IP block. This
can avoid the software cache flush/invalid actions, and improve
the performance significantly.

The PCI IP block of ls1043a has this capability, so adding
this feature to improve the PCI performance.
Signed-off-by: Liu Gang <Gang.Liu@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

As Documentation/arm64/booting.txt says, the cpu-release-addr
location should be reserved.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Olof Johansson <olof@lixom.net>

At first, 256 byte of the head of DRAM space was reserved for some
reasons.  However, as the progress of development, it turned out
unnecessary, and it was never used in the end.  Move the CPU release
address to leave no space.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Olof Johansson <olof@lixom.net>

This node consists of various system-level configuration registers.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Olof Johansson <olof@lixom.net>

Merge tag 'renesas-arm64-dt-for-v4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt64

Renesas ARM64 Based SoC DT Updates for v4.8

* Fix W=1 dtc warnings and other cleanups
* Enable watchdog timer
* Enable DMA for I2C
* Increase the size of GIC-400 mapped registers: be nicer to hypervisors
* Support RTS/CTS hardware flow control

* tag 'renesas-arm64-dt-for-v4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  arm64: dts: r8a7795: Drop 0x from unit address of gic
  arm64: dts: salvator-x: Fix W=1 dtc warnings
  arm64: dts: r8a7795: Fix W=1 dtc warnings
  arm64: dts: r8a7795: Use SYSC "always-on" PM Domain for RWDT node
  arm64: dts: salvator-x: Enable watchdog timer
  arm64: dts: r8a7795: Add RWDT node
  arm64: dts: r8a7795: enable DMA for I2C
  arm64: dts: r8a7795: Increase the size of GIC-400 mapped registers
  arm64: dts: salvator-x: SCIF1 supports RTS/CTS hardware flow control
Signed-off-by: Olof Johansson <olof@lixom.net>

Update reserved-memory in accordance with memory the detailed memory map
for 8916, so that we will be able to reference the firmware memory
regions.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>

This adds the devicetree node for the SCM firmware.
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>

Add the PMU so we can get proper perf event support on this SoC.
Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>

Add device bindings for CPUs to suspend using PSCI as the enable-method.

Cc: <devicetree@vger.kernel.org>
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
Tested-by: Andy Gross <andy.gross@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>

This patch enables bam dma node, dma is used for both tx and rx on spi
and on high speed serial.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>

Add the necessary properties to enable the SD-card on db410c boards.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Andy Gross <andy.gross@linaro.org>

Add "dis_rxdet_inp3_quirk" boolean property to USB3 node. This property
is used to disable rx detection in P3 PHY mode.
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>