- 13 Mar, 2018 30 commits
-
-
Mathieu Malaterre authored
A function init_IRQ() was added without a prototype declared in header irq.h. Fix the following warning (treated as error in W=1): arch/powerpc/kernel/irq.c:662:13: error: no previous prototype for ‘init_IRQ’ Signed-off-by:
Mathieu Malaterre <malat@debian.org> Signed-off-by:
Michael Ellerman <mpe@ellerman.id.au>
-
Mathieu Malaterre authored
In commit 4f8b50bb ("irq_work, ppc: Fix up arch hooks") a new function arch_irq_work_raise() was added without a prototype in header irq_work.h. Fix the following warning (treated as error in W=1): arch/powerpc/kernel/time.c:523:6: error: no previous prototype for ‘arch_irq_work_raise’ Signed-off-by:
-
Mathieu Malaterre authored
In commit 55ccf3fe ("fork: move the real prepare_to_copy() users to arch_dup_task_struct()") a new arch_dup_task_struct() was added without a prototype declared in thread_info.h header. Fix the following warning (treated as error in W=1): arch/powerpc/kernel/process.c:1609:5: error: no previous prototype for ‘arch_dup_task_struct’ Signed-off-by:
-
Mathieu Malaterre authored
The function time_init did not have a prototype defined in the time.h header. Fix the following warning (treated as error in W=1): arch/powerpc/kernel/time.c:1068:13: error: no previous prototype for ‘time_init’ Signed-off-by:
-
Mathieu Malaterre authored
In commit dabe859e ("powerpc: Give hypervisor decrementer interrupts their own handler") an empty body function was added, but no prototype was declared. Fix warning (treated as error in W=1): arch/powerpc/kernel/time.c:629:6: error: no previous prototype for ‘hdec_interrupt’ Signed-off-by:
-
Mathieu Malaterre authored
In commit f0f558b1 ("powerpc/mm: Preserve CFAR value on SLB miss caused by access to bogus address"), the function slb_miss_bad_addr() was added without a prototype. This commit adds it. Fix a warning (treated as error in W=1): arch/powerpc/kernel/traps.c:1498:6: error: no previous prototype for ‘slb_miss_bad_addr’ Signed-off-by:
-
Mathieu Malaterre authored
__giveup_fpu() is never called outside process.c, so it can be static. That also means we don't need an empty definition in switch_to.h Signed-off-by:
-
Mathieu Malaterre authored
Change signature of two functions, adding static keyword to prevent the following two warnings (treated as errors on W=1): arch/powerpc/platforms/embedded6xx/flipper-pic.c:135:28: error: no previous prototype for ‘flipper_pic_init’ arch/powerpc/platforms/embedded6xx/usbgecko_udbg.c:172:6: error: no previous prototype for ‘ug_udbg_putc’ Signed-off-by:
-
Mathieu Malaterre authored
Since the value of `tmp` is never intended to be read, declare both `tmp` variables as unused. Fix warning (treated as error in W=1): arch/powerpc/kernel/signal_32.c: In function ‘sys_swapcontext’: arch/powerpc/kernel/signal_32.c:1048:16: error: variable ‘tmp’ set but not used arch/powerpc/kernel/signal_32.c: In function ‘sys_debug_setcontext’: arch/powerpc/kernel/signal_32.c:1234:16: error: variable ‘tmp’ set but not used Signed-off-by:
-
Mathieu Malaterre authored
The inline keyword was not at the beginning of the function declaration. Fix the following warning (treated as error in W=1): arch/powerpc/lib/sstep.c:283:1: error: ‘inline’ is not at beginning of declaration static int nokprobe_inline copy_mem_in(u8 *dest, unsigned long ea, int nb, arch/powerpc/lib/sstep.c:388:1: error: ‘inline’ is not at beginning of declaration static int nokprobe_inline copy_mem_out(u8 *dest, unsigned long ea, int nb, Signed-off-by:
-
Mathieu Malaterre authored
Fix warning for all register unsigned long (0,3-12) that appear during W=1 compilation: ./arch/powerpc/include/asm/epapr_hcalls.h:479:2: warning: ‘register’ is not at beginning of declaration [-Wold-style-declaration] unsigned long register r[\d] asm("r[\d]"); Signed-off-by: -
Simon Guo authored
In pnv_php_unregister_one(), pnv_php_put_slot() might kfree php_slot structure. But there is pci_hp_deregister() after that with php_slot reference. This patch moves pnv_php_put_slot() to the end of function. Signed-off-by:
Simon Guo <wei.guo.simon@gmail.com> Signed-off-by:
-
Balbir Singh authored
On MCE the current code will restart the machine with ppc_md.restart(). This case was extremely unlikely since prior to that a skiboot call is made and that resulted in a checkstop for analysis. With newer skiboots, on P9 we don't checkstop the box by default, instead we return back to the kernel to extract useful information at the time of the MCE. While we still get this information, this patch converts the restart to a panic(), so that if configured a dump can be taken and we can track and probably debug the potential issue causing the MCE. Signed-off-by:
Balbir Singh <bsingharora@gmail.com> Reviewed-by:
Nicholas Piggin <npiggin@gmail.com> Reviewed-by:
Stewart Smith <stewart@linux.vnet.ibm.com> Signed-off-by:
-
Philippe Bergheaud authored
Configure the P9 XSL_DSNCTL register with PHB indications found in the device tree, or else use legacy hard-coded values. Signed-off-by:
Philippe Bergheaud <felix@linux.vnet.ibm.com> Reviewed-by:
Frederic Barrat <fbarrat@linux.vnet.ibm.com> Reviewed-by:
Christophe Lombard <clombard@linux.vnet.ibm.com> Signed-off-by:
-
Philippe Bergheaud authored
P9 supports PCI tunneled operations (atomics and as_notify). This patch adds support for tunneled operations on powernv, with a new API, to be called by device drivers: pnv_pci_enable_tunnel() Enable tunnel operations, tell driver the 16-bit ASN indication used by kernel. pnv_pci_disable_tunnel() Disable tunnel operations. pnv_pci_set_tunnel_bar() Tell kernel the Tunnel BAR Response address used by driver. This function uses two new OPAL calls, as the PBCQ Tunnel BAR register is configured by skiboot. pnv_pci_get_as_notify_info() Return the ASN info of the thread to be woken up. Signed-off-by:
-
Alistair Popple authored
When sending TLB invalidates to the NPU we need to send extra flushes due to a hardware issue. The original implementation would lock the all the ATSD MMIO registers sequentially before unlocking and relocking each of them sequentially to do the extra flush. This introduced a deadlock as it is possible for one thread to hold one ATSD register whilst waiting for another register to be freed while the other thread is holding that register waiting for the one in the first thread to be freed. For example if there are two threads and two ATSD registers: Thread A Thread B ---------------------- Acquire 1 Acquire 2 Release 1 Acquire 1 Wait 1 Wait 2 Both threads will be stuck waiting to acquire a register resulting in an RCU stall warning or soft lockup. This patch solves the deadlock by refactoring the code to ensure registers are not released between flushes and to ensure all registers are either acquired or released together and in order. Fixes: bbd5ff50 ("powerpc/powernv/npu-dma: Add explicit flush when sending an ATSD") Signed-off-by:
Alistair Popple <alistair@popple.id.au> Signed-off-by:
-
Christophe Leroy authored
cpm_cascade() doesn't have to call eoi() as it is already called by handle_fasteoi_irq() And cpm_get_irq() will always return an unsigned int so the test is useless Signed-off-by:
Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by:
-
Anshuman Khandual authored
This is left over from the segment table implementation and not getting called from any where now. Hence just drop it. Suggested-by:
Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by:
Anshuman Khandual <khandual@linux.vnet.ibm.com> Signed-off-by:
-
Vaibhav Jain authored
PSL9D doesn't have a data-cache that needs to be flushed before resetting the card. However when cxl tries to flush data-cache on such a card, it times-out as PSL_Control register never indicates flush operation complete due to missing data-cache. This is usually indicated in the kernel logs with this message: "WARNING: cache flush timed out" To fix this the patch checks PSL_Debug register CDC-Field(BIT:27) which indicates the absence of a data-cache and sets a flag 'no_data_cache' in 'struct cxl_native' to indicate this. When cxl_data_cache_flush() is called it checks the flag and if set bails out early without requesting a data-cache flush operation to the PSL. Signed-off-by:
Vaibhav Jain <vaibhav@linux.vnet.ibm.com> Acked-by:
Andrew Donnellan <andrew.donnellan@au1.ibm.com> Acked-by:
-
Vaibhav Jain authored
For PSL9 the contents of PSL_TB_CTLSTAT register have changed in PSL9 and all of the register is now readonly. Hence we don't need an sl_ops implementation for 'write_timebase_ctrl' for to populate this register for PSL9. Hence this patch removes function write_timebase_ctrl_psl9() and its references from the code. Signed-off-by:
-
Vaibhav Jain authored
We enable the NORST bit by default for debug afu images to prevent reset of AFU trace-data on a PCI link drop. For production AFU images this bit is always ignored and PSL gets reconfigured anyways thereby resetting the trace data. So setting this bit for non-debug images doesn't have any impact. Signed-off-by:
-
Vaibhav Jain authored
Presently when xmon is disabled by debugfs any existing instruction/data-access breakpoints set are not disabled. This may lead to kernel oops when those breakpoints are hit as the necessary debugger hooks aren't installed. Hence this patch introduces a new function named clear_all_bpt() which is called when xmon is disabled via debugfs. The function will unpatch/clear all the trap and ciabr/dab based breakpoints. Signed-off-by:
-
Vaibhav Jain authored
Presently sysrq key for xmon('x') is registered during kernel init irrespective of the value of kernel param 'xmon'. Thus xmon is enabled even if 'xmon=off' is passed on the kernel command line. However this doesn't enable the kernel debugger hooks needed for instruction or data breakpoints. Thus when a break-point is hit with xmon=off a kernel oops of the form below is reported: Oops: Exception in kernel mode, sig: 5 [#1] < snip > Trace/breakpoint trap To fix this the patch checks and enables debugger hooks when an instruction or data break-point is set via xmon console. Signed-off-by: -
Gustavo Romero authored
Some processor revisions do not support transactional memory, and additionally kernel support can be disabled. In either case the tm-unavailable test should be skipped, otherwise it will fail with a SIGILL. That commit also sets this selftest to be called through the test harness as it's done for other TM selftests. Finally, it avoids using "ping" as a thread name since it's ambiguous and can be confusing when shown, for instance, in a kernel backtrace log. Fixes: 77fad8bf ("selftests/powerpc: Check FP/VEC on exception in TM") Signed-off-by:
Gustavo Romero <gromero@linux.vnet.ibm.com> Reviewed-by:
Cyril Bur <cyrilbur@gmail.com> Signed-off-by:
-
Mathieu Malaterre authored
Make the struct via_pmu_driver const to avoid following warning: WARNING: vmlinux.o(.data+0x4739c): Section mismatch in reference from the variable via_pmu_driver to the function .init.text:pmu_init() The variable via_pmu_driver references the function __init pmu_init() If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console Signed-off-by:
Laurent Vivier <lvivier@redhat.com> Reviewed-by:
-
Sukadev Bhattiprolu authored
Fix the order of cleanup to ensure we free the name buffer in case of an error creating 'hvwc' or 'info' files. Signed-off-by:
Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> Signed-off-by:
-
Sukadev Bhattiprolu authored
Remove a bogus line from arch/powerpc/platforms/powernv/Makefile that was added by commit ece4e512 ("powerpc/vas: Export HVWC to debugfs"). Signed-off-by:
-
Laurent Dufour authored
Ensure that kernel is throwing away the suspended transaction when sigreturn() is called otherwise it if fails to restore the signal frame's TM SPRS. Signed-off-by:
Laurent Dufour <ldufour@linux.vnet.ibm.com> Reviewed-by:
-
Larry Finger authored
In kernel 4.15, the modprobe step on my PowerBook G4 started complaining that there was no module license for ans-lcd. Signed-off-by:
Larry Finger <Larry.Finger@lwfinger.net> Signed-off-by:
-
Michael Ellerman authored
This merges two commits from the `kvm-ppc-fixes` branch into next, as they fix build breaks we are seeing while testing next.
-
- 05 Mar, 2018 7 commits
-
-
Christophe Leroy authored
On the 8xx, the minimum slice size is the size of the area covered by a single PMD entry, ie 4M in 4K pages mode and 64M in 16K pages mode. This patch increases the number of slices from 16 to 64 on the 8xx. Signed-off-by:
-
Christophe Leroy authored
While the implementation of the "slices" address space allows a significant amount of high slices, it limits the number of low slices to 16 due to the use of a single u64 low_slices_psize element in struct mm_context_t On the 8xx, the minimum slice size is the size of the area covered by a single PMD entry, ie 4M in 4K pages mode and 64M in 16K pages mode. This means we could have at least 64 slices. In order to override this limitation, this patch switches the handling of low_slices_psize to char array as done already for high_slices_psize. Signed-off-by:
-
Christophe Leroy authored
On the 8xx, the page size is set in the PMD entry and applies to all pages of the page table pointed by the said PMD entry. When an app has some regular pages allocated (e.g. see below) and tries to mmap() a huge page at a hint address covered by the same PMD entry, the kernel accepts the hint allthough the 8xx cannot handle different page sizes in the same PMD entry. 10000000-10001000 r-xp 00000000 00:0f 2597 /root/malloc 10010000-10011000 rwxp 00000000 00:0f 2597 /root/malloc mmap(0x10080000, 524288, PROT_READ|PROT_WRITE, MAP_PRIVATE|MAP_ANONYMOUS|0x40000, -1, 0) = 0x10080000 This results the app remaining forever in do_page_fault()/hugetlb_fault() and when interrupting that app, we get the following warning: [162980.035629] WARNING: CPU: 0 PID: 2777 at arch/powerpc/mm/hugetlbpage.c:354 hugetlb_free_pgd_range+0xc8/0x1e4 [162980.035699] CPU: 0 PID: 2777 Comm: malloc Tainted: G W 4.14.6 #85 [162980.035744] task: c67e2c00 task.stack: c668e000 [162980.035783] NIP: c000fe18 LR: c00e1eec CTR: c00f90c0 [162980.035830] REGS: c668fc20 TRAP: 0700 Tainted: G W (4.14.6) [162980.035854] MSR: 00029032 <EE,ME,IR,DR,RI> CR: 24044224 XER: 20000000 [162980.036003] [162980.036003] GPR00: c00e1eec c668fcd0 c67e2c00 00000010 c6869410 10080000 00000000 77fb4000 [162980.036003] GPR08: ffff0001 0683c001 00000000 ffffff80 44028228 10018a34 00004008 418004fc [162980.036003] GPR16: c668e000 00040100 c668e000 c06c0000 c668fe78 c668e000 c6835ba0 c668fd48 [162980.036003] GPR24: 00000000 73ffffff 74000000 00000001 77fb4000 100fffff 10100000 10100000 [162980.036743] NIP [c000fe18] hugetlb_free_pgd_range+0xc8/0x1e4 [162980.036839] LR [c00e1eec] free_pgtables+0x12c/0x150 [162980.036861] Call Trace: [162980.036939] [c668fcd0] [c00f0774] unlink_anon_vmas+0x1c4/0x214 (unreliable) [162980.037040] [c668fd10] [c00e1eec] free_pgtables+0x12c/0x150 [162980.037118] [c668fd40] [c00eabac] exit_mmap+0xe8/0x1b4 [162980.037210] [c668fda0] [c0019710] mmput.part.9+0x20/0xd8 [162980.037301] [c668fdb0] [c001ecb0] do_exit+0x1f0/0x93c [162980.037386] [c668fe00] [c001f478] do_group_exit+0x40/0xcc [162980.037479] [c668fe10] [c002a76c] get_signal+0x47c/0x614 [162980.037570] [c668fe70] [c0007840] do_signal+0x54/0x244 [162980.037654] [c668ff30] [c0007ae8] do_notify_resume+0x34/0x88 [162980.037744] [c668ff40] [c000dae8] do_user_signal+0x74/0xc4 [162980.037781] Instruction dump: [162980.037821] 7fdff378 81370000 54a3463a 80890020 7d24182e 7c841a14 712a0004 4082ff94 [162980.038014] 2f890000 419e0010 712a0ff0 408200e0 <0fe00000> 54a9000a 7f984840 419d0094 [162980.038216] ---[ end trace c0ceeca8e7a5800a ]--- [162980.038754] BUG: non-zero nr_ptes on freeing mm: 1 [162985.363322] BUG: non-zero nr_ptes on freeing mm: -1 In order to fix this, this patch uses the address space "slices" implemented for BOOK3S/64 and enhanced to support PPC32 by the preceding patch. This patch modifies the context.id on the 8xx to be in the range [1:16] instead of [0:15] in order to identify context.id == 0 as not initialised contexts as done on BOOK3S This patch activates CONFIG_PPC_MM_SLICES when CONFIG_HUGETLB_PAGE is selected for the 8xx Alltough we could in theory have as many slices as PMD entries, the current slices implementation limits the number of low slices to 16. This limitation is not preventing us to fix the initial issue allthough it is suboptimal. It will be cured in a subsequent patch. Fixes: 4b914286 ("powerpc/8xx: Implement support of hugepages") Signed-off-by: -
Christophe Leroy authored
In preparation for the following patch which will fix an issue on the 8xx by re-using the 'slices', this patch enhances the 'slices' implementation to support 32 bits CPUs. On PPC32, the address space is limited to 4Gbytes, hence only the low slices will be used. The high slices use bitmaps. As bitmap functions are not prepared to handle bitmaps of size 0, this patch ensures that bitmap functions are called only when SLICE_NUM_HIGH is not nul. Signed-off-by:
-
Christophe Leroy authored
In preparation for the following patch which will enhance 'slices' for supporting PPC32 in order to fix an issue on hugepages on 8xx, this patch takes out of page*.h all bits related to 'slices' and put them into newly created slice.h header files. While common parts go into asm/slice.h, subarch specific parts go into respective books3s/64/slice.c and nohash/64/slice.c 'slices' Signed-off-by:
-
Christophe Leroy authored
bitmap_or() and bitmap_andnot() can work properly with dst identical to src1 or src2. There is no need of an intermediate result bitmap that is copied back to dst in a second step. Signed-off-by:
-
Segher Boessenkool authored
Newer gcc will support "-mno-readonly-in-sdata"[1], which makes sure that the optimization on PPC32 for variables getting moved into the .sdata section will not apply to const variables (which must be in .rodata). This was originally noticed in mm/rodata_test.c when rodata_test_data was not static: c0695034 g O .data 00000004 rodata_test_data After this patch with an updated compiler, this is correctly in .rodata. [1] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82411Reported-by:
Segher Boessenkool <segher@kernel.crashing.org> Signed-off-by:
Kees Cook <keescook@chromium.org> Signed-off-by:
-
- 04 Mar, 2018 3 commits
-
-
Linus Torvalds authored
-
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tipLinus Torvalds authored
Pull x86 fixes from Thomas Gleixner: "A small set of fixes for x86: - Add missing instruction suffixes to assembly code so it can be compiled by newer GAS versions without warnings. - Switch refcount WARN exceptions to UD2 as we did in general - Make the reboot on Intel Edison platforms work - A small documentation update so text and sample command match" * 'x86/urgent' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: Documentation, x86, resctrl: Make text and sample command match x86/platform/intel-mid: Handle Intel Edison reboot correctly x86/asm: Add instruction suffixes to bitops x86/entry/64: Add instruction suffix x86/refcounts: Switch to UD2 for exceptions -
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tipLinus Torvalds authored
Pull x86/pti fixes from Thomas Gleixner: "Three fixes related to melted spectrum: - Sync the cpu_entry_area page table to initial_page_table on 32 bit. Otherwise suspend/resume fails because resume uses initial_page_table and triggers a triple fault when accessing the cpu entry area. - Zero the SPEC_CTL MRS on XEN before suspend to address a shortcoming in the hypervisor. - Fix another switch table detection issue in objtool" * 'x86-pti-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/cpu_entry_area: Sync cpu_entry_area to initial_page_table objtool: Fix another switch table detection issue x86/xen: Zero MSR_IA32_SPEC_CTRL before suspend
-
