- 14 Jan, 2015 4 commits
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Geert Uytterhoeven authored
Add device nodes for the two SDRAM Bus State Controllers. The SBSCs are located in the A4BC0 resp. A4BC1 PM domains, which must not be powered down, else the system will crash. References to the A4BC0 and A4BC1 PM domains will be added later. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Geert Uytterhoeven authored
Add a device node for the DDR3 Bus State Controller (DBSC3). The DBSC3 is located in the A4S PM domain, which must not be powered down, else the system will crash. This has no visible effect for now, as A4S was never turned off anyway because its child PM domain A3SM contains the CPU core. Signed-off-by:
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Geert Uytterhoeven authored
Add device nodes for the two DDR Bus State Controllers (DBSC). The DBSCs are located in the A3BC PM domain, which must not be powered down, else the system will crash. A reference to the A3BC PM domain will be added later. Signed-off-by:
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Geert Uytterhoeven authored
Add DT bindings for Renesas R-Mobile and SH-Mobile memory controllers. Currently memory controller device nodes are used only to reference PM domains, and prevent these PM domains from being powered down, which would crash the system. Signed-off-by:
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- 13 Jan, 2015 5 commits
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Kuninori Morimoto authored
Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by:
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Kuninori Morimoto authored
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Sergei Shtylyov authored
I made a mistake when rebasing Andrey Gusakov's patch adding MLB+ clock to the R8A7791 device tree, inserting <&hp_clk> into the "clocks" property of the MSTP8 node at a wrong position, so that the input clocks for MLB+ and IPMMU-SGX got swapped... Fixes: 7408d306 ("ARM: shmobile: r8a7791: add MLB+ clock") Signed-off-by:
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by:
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Geert Uytterhoeven authored
Add a device node for the System Controller, with subnodes that represent the hardware power area hierarchy. Hook up all devices to their respective PM domains. Add a minimal device node for the Coresight-ETM hardware block, and hook it up to the D4 PM domain, so the R-Mobile System Controller driver can keep the domain powered, until the new Coresight code handles runtime PM. Signed-off-by:
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Geert Uytterhoeven authored
The Renesas R-Mobile System Controller provides a.o. power management support, following the generic PM domain bindings in Documentation/devicetree/bindings/power/power_domain.txt. For now this supports the R-Mobile A1 (r8a7740) only, but it should be sufficiently generic to handle other members of the SH-Mobile/R-Mobile family in the future. Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by:
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- 08 Jan, 2015 1 commit
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Geert Uytterhoeven authored
The FSI2 sound node used the generic compatible property only. Add the SoC-specific one, to make it future proof. Signed-off-by:
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- 23 Dec, 2014 2 commits
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Andrey Gusakov authored
Add MLB+ clock to R8A7791 device tree. Signed-off-by:
Andrey Gusakov <andrey.gusakov@cogentembedded.com> [Sergei: rebased, renamed, added changelog] Signed-off-by:
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Andrey Gusakov authored
Add MLB+ clock to R8A7790 device tree. Signed-off-by:
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- 21 Dec, 2014 28 commits
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Laurent Pinchart authored
The LAN9220 VDDVARIO supply is powered by a 1.8V source, not 3.3V. Fix it in the device tree. Signed-off-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by:
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Ulrich Hecht authored
Makes sure the dtb is built for multiplatform builds. Signed-off-by:
Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Acked-by:
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Ulrich Hecht authored
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Ulrich Hecht authored
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Ulrich Hecht authored
This moves everything to the legacy dts that is missing there in preparation for the switch to multiplatform. Signed-off-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by:
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Ulrich Hecht authored
It's a 9220, not a 9118. Signed-off-by:
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Shinobu Uehara authored
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Shinobu Uehara <shinobu.uehara.xc@renesas.com> [horms: omitted device node; only add clock] Signed-off-by:
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Shinobu Uehara authored
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Koji Matsuoka authored
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Koji Matsuoka <koji.matsuoka.xm@renesas.com> [horms: omitted device nodes and aliases; only add clocks] Signed-off-by:
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Magnus Damm authored
Now when r8a7779 CCF is in place we can hook up the ARM Cortex-A9 TWD timer via DTS. Signed-off-by:
Magnus Damm <damm+renesas@opensource.se> Signed-off-by:
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Magnus Damm authored
Hook up MSTP clocks to SCIF devices on r8a7779 to allow clock gating to work as expected. Signed-off-by:
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Magnus Damm authored
Use R8A7779_CLK_P as parent clock for SCIF devices on r8a7779. With this change in place the SCIF CCF handling matches the legacy clock code. Also, this matches the data sheet. Signed-off-by:
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Hisashi Nakamura authored
Signed-off-by:
Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> [horms: omitted device node and alias; only add clock] [horms: use clock-indicies instead of renesas,clock-indicies] Signed-off-by:
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Hisashi Nakamura authored
In order to change into mode3, CPOL and CPHA bit of SPCMD register of QSPI is changed. Mode3 can avoid intermediate voltage. Signed-off-by:
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Hiroyuki Yokoyama authored
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Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> [horms: resolved conflicts] Signed-off-by:
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Ryo Kataoka authored
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Ryo Kataoka <ryo.kataoka.wt@renesas.com> [horms: resolved conflicts] Signed-off-by:
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Hisashi Nakamura authored
In order to change into mode3, CPOL and CPHA bit of SPCMD register of QSPI is changed. Mode3 can avoid intermediate voltage. Signed-off-by:
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Kazuya Mizuguchi authored
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Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com> [horms: merged per-clock patches] Signed-off-by:
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Geert Uytterhoeven authored
R-Car E2 (r8a7794) contains two Cortex-A7 cores, hence the second interrupt specifier cell for Private Peripheral Interrupts should use "GIC_CPU_MASK_SIMPLE(2)". Signed-off-by:
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Geert Uytterhoeven authored
R-Car M2-W (r8a7791) contains two Cortex-A15 cores, hence the second interrupt specifier cell for Private Peripheral Interrupts should use "GIC_CPU_MASK_SIMPLE(2)". Signed-off-by:
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Simon Horman authored
Update the size and names of flash partitions to match the expectations of the loader which are as follows: "loader"---0x0000_0000-0x0008_0000 [loader program (readonly)] "user" ---0x0008_0000-0x0060_0000 [U-Boot + bootargs + dt + uImage (readonly)] "flash" ---0x0060_0000-0x0400_0000 [filesystem and free (read/write)] ["user"'s assumed breakdown] U-boot (0x0008_0000-0x000c_0000) 256KiB bootargs (0x000c_0000-0x0010_0000) 256KiB Device tree (0x0010_0000-0x0014_0000) 256KiB zImage (0x0014_0000-0x0060_0000) 4.75MiB Signed-off-by:
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Shinobu Uehara authored
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Geert Uytterhoeven authored
With the addition of clock-indices in commit 8e33f91a ("clk: shmobile: clk-mstp: change to using clock-indices"), we can change the DTSes to use the generic property instead of the deprecated vendor-specific property. Signed-off-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by:
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Ben Dooks authored
With the addition of clock-indices in commit 8e33f91a ("clk: shmobile: clk-mstp: change to using clock-indices"), we can change the DTSes to use the generic property instead of the deprecated vendor-specific property. Signed-off-by:
Ben Dooks <ben.dooks@codethink.co.uk> [geert: Extracted r8a7791-specific part, rebased, reworded] Signed-off-by:
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Ben Dooks authored
With the addition of clock-indices in commit 8e33f91a ("clk: shmobile: clk-mstp: change to using clock-indices"), we can change the DTSes to use the generic property instead of the deprecated vendor-specific property. Signed-off-by:
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Geert Uytterhoeven authored
With the addition of clock-indices in commit 8e33f91a ("clk: shmobile: clk-mstp: change to using clock-indices"), we can change the DTSes to use the generic property instead of the deprecated vendor-specific property. Signed-off-by:
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Geert Uytterhoeven authored
With the addition of clock-indices in commit 8e33f91a ("clk: shmobile: clk-mstp: change to using clock-indices"), we can change the DTSes to use the generic property instead of the deprecated vendor-specific property. Signed-off-by:
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Geert Uytterhoeven authored
The address space for the r8a73a4 Bus State Controller covers the first 512 MiB, not the first 2 GiB. Correct the size in the "ranges" property to reflect this, and to no longer overlap with PCI Express Memory. Signed-off-by:
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