- 30 Aug, 2017 40 commits
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yangbo lu authored
eSDHC is not a standard SD host controller. SDHCI_CAPABILITIES_1 register address is 0x44 while it's 0x114 (ESDHC_CAPABILITIES_1) for eSDHC. Signed-off-by:
Yangbo Lu <yangbo.lu@nxp.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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yangbo lu authored
SD controller with SDHCI_QUIRK_NO_HISPD_BIT quirk probably use high speed enable bit for other purpose. So this bit shouldn't be changed for high speed enabling for this type of SD controller. Signed-off-by:
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Michał Mirosław authored
Now that sdhci_set_bus_width() supports 8-bit bus widths based on the MMC_CAP_8_BIT_DATA capability flag, replace the sdhci-s3c version with the generic sdhci version. Signed-off-by:
Michał Mirosław <mirq-linux@rere.qmqm.pl> Acked-by:
Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by:
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Michał Mirosław authored
Now that sdhci_set_bus_width() supports 8-bit bus widths based on the MMC_CAP_8_BIT_DATA capability flag, replace the sdhci-pci version with the generic sdhci version. Signed-off-by:
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Michał Mirosław authored
Now that sdhci_set_bus_width() supports 8-bit bus widths based on the MMC_CAP_8_BIT_DATA capability flag, replace the tegra version with the generic sdhci version. Signed-off-by:
Thierry Reding <treding@nvidia.com> Signed-off-by:
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Michał Mirosław authored
Hosts supporting 8-bit bus are marked accordingly. If MMC_CAP_8_BIT_DATA is not among host capabilities, 8BITBUS bit will never be set and it is not cleared in case some non-SDHCI3 host uses it for something else. Signed-off-by:
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Biju Das authored
Add support for r8a7743/5 SoC. Renesas RZ/G1[ME] (R8A7743/5) SDHI is identical to the R-Car Gen2 family. Signed-off-by:
Biju Das <biju.das@bp.renesas.com> Reviewed-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Acked-by:
Simon Horman <horms+renesas@verge.net.au> Signed-off-by:
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Adrian Hunter authored
CQE needs to be off for the host controller to accept non-CQ commands. Turn off the CQE before sending commands, and ensure it is off in any reset or power management paths, or re-tuning. Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
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Adrian Hunter authored
Add CQE host operations, capabilities, and host members. Signed-off-by:
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Adrian Hunter authored
Most of the information needed to issue requests to a CQE is already in struct mmc_request and struct mmc_data. Add data block address, some flags, and the task id (tag), and allow for cmd being NULL which it is for CQE tasks. Signed-off-by:
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Adrian Hunter authored
mmc_return_hold() / mmc_retune_release() are used around a group of commands to prevent re-tuning between the commands. Re-tuning can still happen before the first command. In some cases, re-tuning must be prevented entirely. Add mmc_retune_hold_now() for that purpose. It is added in preparation for CQE support where it will be used by CQE recovery. Signed-off-by:
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Adrian Hunter authored
Packed commands support was removed but some bits got left behind. Remove them. Signed-off-by:
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Chen-Yu Tsai authored
sunxi_mmc_clk_set_phase expects the actual card clock rate to be passed to it. When the internal divider code was reworked in change ("mmc: sunxi: Support MMC DDR52 transfer mode with new timing mode"), this requirement was missed, and the module clock rate was passed in instead. This broke 8 bit DDR MMC on old controllers, as the module clock rate is double the card clock rate, for which we have no valid delay settings. Fix this by applying the internal divider to the clock rate right after we configure it in hardware. Signed-off-by:Chen-Yu Tsai <wens@csie.org> Signed-off-by:
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Wolfram Sang authored
Make use of the 64 bit sdbuf width on Renesas R-Car Gen3. If the registers are 8 byte apart, the width is also 64 bit. For all others, the width is 32 bit, even if the registers are only 16 bit apart. Signed-off-by:
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Wolfram Sang authored
We don't use this new define yet, but it is helpful to document which versions we know of. Signed-off-by:
Chris Brandt <Chris.Brandt@renesas.com> Reviewed-by:
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Wolfram Sang authored
It is documented, so enable it to follow the recommendation in the docs and also save a few cycles. Signed-off-by:
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Wolfram Sang authored
There is one SDHI instance on Gen2 which does not have the CBSY bit. So, turn CBSY usage into an extra flag and set it accordingly. This has the additional advantage that we can also set it for other incarnations later. Signed-off-by:
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Arvind Yadav authored
usb_device_id are not supposed to change at runtime. All functions working with usb_device_id provided by <linux/usb.h> work with const usb_device_id. So mark the non-const structs as const. Signed-off-by:
Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by:
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Hu Ziji authored
Add Xenon specific system-level suspend and resume support. Especially during resume, re-configure Xenon specific registers since registers setting will be lost in suspend if Xenon is power off. Signed-off-by:
Hu Ziji <huziji@marvell.com> Signed-off-by:
Zhoujie Wu <zjwu@marvell.com> Tested-by:
Jisheng Zhang <jszhang@marvell.com> Acked-by:
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Addy Ke authored
Per the databook of designware mmc controller 2.70a, table 3-2, cmd done interrupt should be fired as soon as the the cmd is sent via cmd line. And the response timeout interrupt should be generated unconditioinally as well if the controller doesn't receive the resp. However that doesn't seem to meet the fact of rockchip specified Soc platforms using dwmmc. We have continuously found the the cmd done or response timeout interrupt missed somehow which took us a long time to understand what was happening. Finally we narrow down the root to the reconstruction of sample circuit for dwmmc IP introduced by rockchip and the buggy design sweeps over all the existing rockchip Socs using dwmmc disastrously. It seems no way to work around this bug without the proper break-out mechanism so that we seek for a parallel pair the same as the handling for missing data response timeout, namely dto timer. Adding this cto timer seems easily to handle this bug but it's hard to restrict the code under the rockchip specified context. So after merging this patch, it sets up the cto timer for all the platforms using dwmmc IP which isn't ideal but at least we don't advertise new quirk here. Fortunately, no obvious performance regression was found by test and the pre-existing similar catch-all timer for sdhci has proved it's an acceptant way to make the code as robust as possible. Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=196321Signed-off-by:
Addy Ke <addy.ke@rock-chips.com> Signed-off-by:
Ziyuan Xu <xzy.xu@rock-chips.com> [shawn.lin: rewrite the code and the commit msg throughout] Signed-off-by:
Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by:
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liwei authored
Add sd card support for hi3660 soc Signed-off-by:
Li Wei <liwei213@huawei.com> Signed-off-by:
Chen Jun <chenjun14@huawei.com> Signed-off-by:
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liwei authored
This commit modifies dw_mci_probe(), it moves reset assertion before drv_data->init(host) Some driver needs to access controller registers in its .init() ops. So, in order to make such access safe, we should do controller reset before .init() being called. Signed-off-by:
Guodong Xu <guodong.xu@linaro.org> Signed-off-by:
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Arvind Yadav authored
clk_prepare_enable() can fail here and we must check its return value. Signed-off-by:
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Arvind Yadav authored
clk_prepare_enable() can fail here and we must check its return value. Signed-off-by:
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Srinivas Kandagatla authored
Programming legacy HOST SDMA Buffer Boundary bits in Block Size Register (0x04) is not supported in Qualcomm sdhci controllers. Writing to this would cause the controller not to transfer last block in case block size is 4 bytes or less. This issue was noticed while testing sdio wlan card on Qcom DB410c board. Signed-off-by:
Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Acked-by:
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Srinivas Kandagatla authored
This patch adds sdma_boundary member to struct sdhci_host to give more flexibility to drivers to control the sdma boundary buffer value and also to fix issue on some sdhci controllers which are broken when HOST SDMA Buffer Boundary is programmed in Block Size Register (0x04) when using ADMA. Qualcomm sdhci controller is one of such type, writing to this bits is un-supported. Default value of sdma_boundary is set to SDHCI_DEFAULT_BOUNDARY_ARG. Signed-off-by:
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Julia Lawall authored
The structure renesas_sdhi_internal_dmac_dma_ops is only passed as the second argument to renesas_sdhi_probe, which is const, so renesas_sdhi_internal_dmac_dma_ops can be const too. Done with the help of Coccinelle. Signed-off-by:
Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by:
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Julia Lawall authored
The sdhci_pltfm_data structure is only passed as the second argument of sdhci_pltfm_init, which is const, so the sdhci_pltfm_data structure can be const as well. Done with the help of Coccinelle. Signed-off-by:
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Julia Lawall authored
The sdhci_pltfm_data structure is only passed as the second argument of sdhci_pltfm_init, which is const, while the sdhci_ops structure is only stored in the ops field of a sdhci_pltfm_data structure, which is also const. Thus both kinds of structures can be const as well. Done with the help of Coccinelle. Signed-off-by:
Michal Simek <michal.simek@xilinx.com> Signed-off-by:
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Julia Lawall authored
The sdhci_pltfm_data structure is only passed as the second argument of sdhci_pltfm_init, which is const, while the sdhci_ops structure is only stored in the ops field of a sdhci_pltfm_data structure, which is also const. Thus both kinds of structures can be const as well. Done with the help of Coccinelle. Signed-off-by:
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Julia Lawall authored
The sdhci_pltfm_data structure is only passed as the second argument of sdhci_pltfm_init, which is const, while the sdhci_ops structure is only stored in the ops field of a sdhci_pltfm_data structure, which is also const. Thus both kinds of structures can be const as well. Done with the help of Coccinelle. Signed-off-by:
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Julia Lawall authored
The sdhci_pltfm_data structure is only passed as the second argument of sdhci_pltfm_init, which is const, so the sdhci_pltfm_data structure can be const as well. Done with the help of Coccinelle. Signed-off-by:
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Shawn Lin authored
Per the SD physical layer simplified specification V4.10, section 4.6.2, CSD version 1.0 SD card should use taac, nsac and r2w_factor for calculating the data access time. But the taac and nsac for SDHC(CSD version 2.0) are always fixed and the software should use the recommended value for timeout. When parsing the CSD, we sanely set them to zero for SDHC(CSD version 2.0), all the calculation for timeout_ns and timeout_clk is zero as well. So what we actually want to limit here is either SDHC case or unreasonable timeout reported by the cards. In principle we should at least be able to remove the bogus check for the mmc_card_blockaddr. Signed-off-by:
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Zhoujie Wu authored
One issue was found on a removable high speed sd card with runtime pm enabled. When SD card is unplugged, it keep printing "Switching to 3.3V signalling voltage failed". And found below sequence triggers the error. mmc_rescan -> mmc_sd_detect -> mmc_power_off -- mmc->ios.vdd is updated to 0. -> mmc_claim_host -> sdhci_runtime_resume_host -> sdhci_start_signal_voltage_switch -> mmc_regulator_set_vqmmc -> mmc_ocrbitnum_to_vdd When mmc_ocrbitnum_to_vdd is called, the mmc->ios.vdd is 0, so it always return -EINVAL. The signal switch will always fail and print out warning. Ignore restoring the I/O state when runtime resume if MMC_POWER_OFF. Signed-off-by:
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Icenowy Zheng authored
The A83T MMC support code introduces the timings mode switch, however such a switch doesn't exist on new SoCs with only new timings mode. Only execute the switch if the SoC really have the timings mode switch, to fix the regression shown on new timings mode only SoCs (A64, H5, etc). Signed-off-by:
Icenowy Zheng <icenowy@aosc.io> Reviewed-by:
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Chen-Yu Tsai authored
Some SoCs do not support clk delays for MMC in the clock control unit. These include the old controllers in A10/A10s/A13/R8, and the new eMMC controller in A64. The config structure for these controllers do not specify clk_delays, but the check for this was replaced in change "mmc: sunxi: Support controllers that can use both old and new timings". This patch adds back the check for clk_delays, and also adds comments for both checks in sunxi_mmc_clk_set_phase(). Signed-off-by:
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Chen-Yu Tsai authored
The third MMC controller (MMC2) on the Allwinner A83T SoC is slightly different. It supports a wider 8-bit bus, has a dedicated controllable reset pin for eMMC, and a "new timing mode" which is supposed to deliver better signals and thus better performance. Add a compatible for this one to use the new timing mode not found in the other controllers. Signed-off-by:
Rob Herring <robh@kernel.org> Acked-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by:
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Chen-Yu Tsai authored
The MMC controller can support DDR52 transfers under the new timing mode. According to the BSP kernel, the module clock has to be double the card clock, regardless of the bus width. The default timings in the hardware can be used. This also reworks the code setting the internal divider, getting rid of a extra conditional. Signed-off-by:
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Chen-Yu Tsai authored
On the SoCs that introduced the new timing mode for MMC controllers, both the old (where the clock delays are set in the CCU) and new (where the clock delays are set in the MMC controller) timing modes are available, and we have to support them both. However there are two bits that control which mode is active. One is in the CCU, the other is in the MMC controller. The settings on both sides must be the same, or nothing will work. The sunxi-ng clock driver provides an API to query and set the active timing mode. At probe time, we try to set the active mode to the "new timing mode". If it succeeds, we can then use the MMC controller in the new mode. If not, we fall back to the old mode. Signed-off-by:
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Chen-Yu Tsai authored
The MMC2 clock supports a new timing mode. When the new mode is active, the output clock rate is halved. This patch sets the feature flag for the new timing mode, and adds a pre-divider based on the mode bit. Signed-off-by:
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