- 07 Nov, 2019 3 commits
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Chris Wilson authored
Before we grab the engine wakeref, tidy up the previous heartbeat request. If we then abort because the engine powerwell is off, we ensure the request is freed as we know we will not have freed it when cancelling the work (as the work is running!). Fixes: 841e8672 ("drm/i915/gt: Only drop heartbeat.systole if the sole owner") References: 058179e7 ("drm/i915/gt: Replace hangcheck by heartbeats") Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by:
Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191106223410.30334-1-chris@chris-wilson.co.uk
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Lucas De Marchi authored
Prefer using intel_encoder and pass the base where needed rather than keeping both encoder and intel_encoder variables around. v2: actually add all changes to the patch Signed-off-by:
Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191106071715.10613-1-lucas.demarchi@intel.com
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James Ausmus authored
Another TGP ID has shown up, so let's add it to avoid South Display breakage on systems that have this ID. Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by:
James Ausmus <james.ausmus@intel.com> Reviewed-by:
José Roberto de Souza <jose.souza@intel.com> Signed-off-by:
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- 06 Nov, 2019 7 commits
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Niranjana Vishwanathapura authored
We don't need rcu read side critical section to call pid_nr(), remove it. Signed-off-by:
Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com> Reviewed-by:
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Chris Wilson authored
When inside the lock, remember to unlock even if you want to leave early. Reported-by:
Dan Carpenter <dan.carpenter@oracle.com> Fixes: a4e7ccda ("drm/i915: Move context management under GEM") Signed-off-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191106144155.25727-1-chris@chris-wilson.co.uk
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Chris Wilson authored
Mika spotted that only using cancel_delayed_work() could mean that we attempted to clear the heartbeat.systole while the worker was still running. Rectify the situation by only touching the systole from outside the worker if we suceeded in cancelling the worker before it could run. The worker is expected to clean up by itself upon idling. Reported-by:
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Matthew Auld authored
We should not be unconditionally calling release_fake_lmem_bar. Signed-off-by:
Matthew Auld <matthew.auld@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by:
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Ville Syrjälä authored
The uapi vs. hw state split introduced a bug in intel_crtc_disable_noatomic() where it's now frobbing an already freed temp crtc state instead of adjusting the crtc state we are really left with. Fix that by making a cleaner separation beteen the two. This causes explosions on any machine that boots up with pipes already running but not hooked up to any encoder (typical behaviour for gen2-4 VBIOS). Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Fixes: 58d124ea ("drm/i915: Complete crtc hw/uapi split, v6.") Signed-off-by:
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
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Chris Wilson authored
If the device does not have an aperture through which we can indirectly access and detile the buffers, simply reject the ioctl. Later we can extend the ioctl to support different modes, but as an extension the user must opt in and explicitly control the mmap type (viz MMAP_OFFSET_IOCTL). Signed-off-by:
Abdiel Janulgue <abdiel.janulgue@linux.intel.com> Reviewed-by:
Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191105145305.14314-1-chris@chris-wilson.co.uk
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Tvrtko Ursulin authored
It sounds like the hardware only needs the DSB object to be in global GTT and not in the mappable region. Signed-off-by:
Animesh Manna <animesh.manna@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191017155810.21654-1-tvrtko.ursulin@linux.intel.com
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- 05 Nov, 2019 5 commits
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Jani Nikula authored
Use intel_dsc_ prefix. No functional changes. Cc: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by:
Manasi Navare <manasi.d.navare@intel.com> Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191104141439.26312-4-jani.nikula@intel.com
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Jani Nikula authored
Split out the DP specific parts, making it easier to add DSI specific configuration. Also move the encoder specific parts towards the end, to allow overriding generic configuration if needed. This also improves clarity by making it clear the encoder independent configuration does not depend on the encoder specific parts. v2: Rebase Cc: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by:
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Jani Nikula authored
Use a simple pointer to the relevant element instead of duplicating the array subscription. No functional changes. Cc: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by:
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Jani Nikula authored
No need for them to be mutable. Cc: Manasi Navare <manasi.d.navare@intel.com> Reviewed-by:
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Jani Nikula authored
Since CNP it's possible for rawclk to have two different values, 19.2 and 24 MHz. If the value indicated by SFUSE_STRAP register is different from the power on default for PCH_RAWCLK_FREQ, we'll end up having a mismatch between the rawclk hardware and software states after suspend/resume. On previous platforms this used to work by accident, because the power on defaults worked just fine. Update the rawclk also on resume. The natural place to do this would be intel_modeset_init_hw(), however VLV/CHV need it done before intel_power_domains_init_hw(). Thus put it there even if it feels slightly out of place. v2: Call intel_update_rawclck() in intel_power_domains_init_hw() for all platforms (Ville). Reported-by:Shawn Lee <shawn.c.lee@intel.com> Cc: Shawn Lee <shawn.c.lee@intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Reviewed-by:
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- 04 Nov, 2019 15 commits
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Lucas De Marchi authored
Just avoid the additional read in case DP_TP_CTL is enabled: read it once and save the value. Signed-off-by:
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Lucas De Marchi authored
For MST on Tiger Lake there are different moments when we need to configure the transcoder clock select. For the first link this is in step 7.a of the spec, before training the link. For additional streams this should be done as part of step 8.b after programming receiver VC Payload ID. Bspec: 49190 Signed-off-by:
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Lucas De Marchi authored
Wrap drm_atomic_get_old_connector_state so we can get the intel_digital_connector_state and make it easier to migrate to intel types. Signed-off-by:
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José Roberto de Souza authored
The same macro as for_each_new_connector_in_state() but it uses intel/i915 types instead of the drm ones. Signed-off-by:
Mika Kahola <mika.kahola@intel.com> Reviewed-by:
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Ville Syrjälä authored
Lots of redundant assignments inside intel_primary_plane_create(). Get rid of them. v2: Rebase due to fp16 landing Signed-off-by:
Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Reviewed-by:
Uma Shankar <uma.shankar@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191031165652.10868-8-ville.syrjala@linux.intel.com
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Ville Syrjälä authored
Let's try to keep the pixel format arrays somewhat sorted: 1. RGB before YUV 2. smaller bpp before larger bpp 3. X before A 4. RGB before BGR Signed-off-by:
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Ville Syrjälä authored
ICL+ again supports alpha blending with 10bpc pixel formats. Expose them. v2: Add all the stuff I missed earlier! Signed-off-by:
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Ville Syrjälä authored
VLV/CHV sprite planes also support the C8 format. Let's expose that. Signed-off-by:
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Ville Syrjälä authored
CHV pipe B sprites gained support for the 10bpc X/ARGB pixel formats. On VLV and CHV pipe A/C these are only supported by the primary plane. Add the require bits to expose the new formats. v2: Reorder the formats for consistency Signed-off-by:
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Ville Syrjälä authored
Currently we expose VLV/CHV alpha blending only on the sprite planes, but the primary planes can do it as well. Let's flip it on. v2: Rebase due to fp16 landing Signed-off-by:
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Ville Syrjälä authored
SNB-BDW support 10:10:10 formats on the sprite planes. Let's expose them. v2: Rebase due to fp16 landing Signed-off-by:
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Chris Wilson authored
Sometimes Icelake forgets to reset the CSB pointers on a GPU reset, leading to it carry on updating the old tail of the buffer. <0>[ 618.138490] i915_sel-5636 3d..1 673425465us : trace_ports: vecs0: submit { 14de2:504, 0:0 } <0>[ 618.138490] i915_sel-5636 3.... 673425493us : intel_engine_reset: vecs0 flags=100 <0>[ 618.138490] i915_sel-5636 3.... 673425493us : execlists_reset_prepare: vecs0: depth<-0 <0>[ 618.138490] i915_sel-5636 3.... 673425493us : intel_engine_stop_cs: vecs0 <0>[ 618.138490] i915_sel-5636 3.... 673425523us : __intel_gt_reset: engine_mask=40 <0>[ 618.138490] i915_sel-5636 3.... 673425568us : execlists_reset: vecs0 <0>[ 618.138490] i915_sel-5636 3d..1 673425568us : process_csb: vecs0 cs-irq head=1, tail=2 <0>[ 618.138490] i915_sel-5636 3d..1 673425568us : process_csb: vecs0 csb[2]: status=0x00000001:0x40000000 <0>[ 618.138490] i915_sel-5636 3d..1 673425569us : trace_ports: vecs0: promote { 14de2:504*, 0:0 } <0>[ 618.138490] i915_sel-5636 3d..1 673425570us : __i915_request_reset: vecs0 rq=14de2:504, guilty? yes <0>[ 618.138490] i915_sel-5636 3d..1 673425571us : __execlists_reset: vecs0 replay {head:2de0, tail:2e48} <0>[ 618.138490] i915_sel-5636 3d..1 673425572us : __i915_request_unsubmit: vecs0 fence 14de2:504, current 503 <0>[ 618.138490] i915_sel-5636 3.... 673435544us : intel_engine_cancel_stop_cs: vecs0 <0>[ 618.138490] i915_sel-5636 3.... 673435544us : process_csb: vecs0 cs-irq head=11, tail=11 <0>[ 618.138490] i915_sel-5636 3d..1 673435545us : __i915_request_submit: vecs0 fence 14de2:504, current 503 <0>[ 618.138490] i915_sel-5636 3d..1 673435546us : __execlists_submission_tasklet: vecs0: queue_priority_hint:-2147483648, submit:yes <0>[ 618.138490] i915_sel-5636 3d..1 673435548us : trace_ports: vecs0: submit { 14de2:504*, 0:0 } <0>[ 618.138490] i915_sel-5636 3.... 673435549us : execlists_reset_finish: vecs0: depth->0 <0>[ 618.138490] ksoftirq-21 2..s. 673435592us : process_csb: vecs0 cs-irq head=11, tail=3 <0>[ 618.138490] ksoftirq-21 2..s. 673435593us : process_csb: vecs0 csb[0]: status=0x00000001:0x40000000 <0>[ 618.138490] ksoftirq-21 2..s. 673435594us : trace_ports: vecs0: promote { 14de2:504*, 0:0 } <0>[ 618.138490] ksoftirq-21 2..s. 673435596us : process_csb: vecs0 csb[1]: status=0x00000018:0x40000040 <0>[ 618.138490] ksoftirq-21 2..s. 673435597us : trace_ports: vecs0: completed { 14de2:504*, 0:0 } <0>[ 618.138490] ksoftirq-21 2..s. 673435612us : process_csb: process_csb:2188 GEM_BUG_ON(!i915_request_completed(*execlists->active) && !reset_in_progress(execlists)) After the reset, we do another clflush before checking the CSB to be sure we see whatever was left in the CSB prior to the reset. So it is unlikely to be an incoherent view of the CSB, and more likely that Icelake didn't reset its pointers. References: 582a6f90 ("drm/i915/execlists: Add a paranoid flush of the CSB pointers upon reset") Signed-off-by: -
Jani Nikula authored
Add another for_each style macro to the pile of custom looping macros. Reviewed-by:
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Chris Wilson authored
Since the execlists_active() is no longer protected by the engine->active.lock, we need to protect the request pointer with RCU to prevent it being freed as we evaluate whether or not we need to preempt. Fixes: df403069 ("drm/i915/execlists: Lift process_csb() out of the irq-off spinlock") Fixes: 13ed13a4 ("drm/i915: Don't set queue_priority_hint if we don't kick the submission") Signed-off-by:
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Chris Wilson authored
The counter is removed from the pm wakeref count, but it remains intact so that we can restore it upon resume. Ergo inside suspend, it may have a value. Signed-off-by:
Andi Shyti <andi.shyti@intel.com> Reviewed-by:
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- 02 Nov, 2019 3 commits
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Chris Wilson authored
Filter out warnings for the kernel context that is used to flush inactive contexts, as they do no not pose a risk. Signed-off-by:
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Chris Wilson authored
Check that the context's ring register state still matches our expectations prior to execution. Signed-off-by:
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Chris Wilson authored
Flushing the outer i915_active is not enough, as we need the barrier to be applied across all the active dma_fence callbacks. So we must serialise with each outstanding fence. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=112096 References: f79520bb ("drm/i915/selftests: Synchronize checking active status with retirement") Signed-off-by:
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- 01 Nov, 2019 7 commits
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Chris Wilson authored
Avoid drivers/gpu/drm/i915/i915_perf.c:2442:85: warning: dubious: x | !y simply by inverting the predicate and reversing the ternary. v2: Move the long lines into their own function so there is no confusion on operator precedence. Signed-off-by:
Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191101192116.12647-1-chris@chris-wilson.co.uk
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Chris Wilson authored
Call suspend_prepare first so that we don't leave GuC so confused. Signed-off-by:
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Chris Wilson authored
Currently we shutdown rc6 during i915_gem_resume() but this is called during the preparation phase (i915_drm_prepare) for all suspend paths, but we only want to shutdown rc6 for S3+. Move the actual shutdown to i915_gem_suspend_late(). We then need to differentiate between suspend targets, to distinguish S0 (s2idle) where the device is kept awake but needs to be in a low power mode (the same as runtime suspend) from the device suspend levels where we lose control of HW and so must disable any HW access to dangling memory. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111909 Fixes: c1132367 ("drm/i915: Extract GT render sleep (rc6) management") Testcase: igt/gem_exec_suspend/power-S0 Signed-off-by:
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Chris Wilson authored
We already track the debugfs user_forcewake on the GT, so it is natural to pull the suspend/resume handling under gt/ as well. Signed-off-by:
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Chris Wilson authored
As we already do reload the kernel context in intel_gt_resume, repeating that action inside i915_gem_resume() as well is redundant. Signed-off-by:
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Chris Wilson authored
Assume all responsibility for operating on the HW to sanitize the GT state upon load/resume in intel_gt_sanitize() itself. Signed-off-by:
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Chris Wilson authored
Our timelines are currently contained within an intel_gt, and we only need to perform list/spinlock initialisation, so we can pull the intel_timelines_init() into our intel_gt_init_early(). Signed-off-by:
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