- 14 Jul, 2017 40 commits
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Christian König authored
No functional change, just cleanup. v2: rebased, keep gart name. Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Alex Deucher authored
Rather than checking the CONGIG_MEMSIZE register as that may not be reliable on some APUs. v2: The scratch register is only used on CIK+ Reviewed-by:
Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by:
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Alex Deucher authored
Call nbio init registers on hw_init to set up any nbio registers that need initialization at hw init time. Acked-by:
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Alex Deucher authored
Used for nbio registers that need to be initialized. Currently only used for a golden setting that got missed on some boards. Acked-by:
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Evan Quan authored
Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
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Evan Quan authored
- v2: rename param 'en' as 'lock' Signed-off-by:
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Evan Quan authored
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Evan Quan authored
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Evan Quan authored
- v2: added missing spinlock init Signed-off-by:
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Evan Quan authored
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Christian König authored
Use the TTM values instead of the hardware config here. Signed-off-by:
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Christian König authored
We can finally remove this now. v2: remove now unused max_size variable as well. Signed-off-by:
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Christian König authored
No need to map BOs to GTT on eviction and intermediate transfers any more. Signed-off-by:
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Christian König authored
This way we don't need to map the full BO at a time any more. v2: use fixed windows for src/dst Signed-off-by:
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Christian König authored
This allows us to write the mapped PTEs into an IB instead of the table directly. v2: fix build with debugfs enabled, remove unused assignment Signed-off-by:
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Christian König authored
We want to use them as remap address space. Signed-off-by:
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Colin Ian King authored
The arrays pctl0_data and pctl1_data do not need to be in global scope, so them both static. Cleans up sparse warnings: symbol 'pctl0_data' was not declared. Should it be static? symbol 'pctl1_data' was not declared. Should it be static? Signed-off-by:
Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Alex Deucher authored
Get it from the system info table. Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Acked-by:
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Alex Deucher authored
Implement support using the new atomfirmware system info table. Reviewed-by:
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Alex Deucher authored
Not all vbios images seem to set the version appropriately. Switch the check based on asic type instead. Reviewed-by:
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Alex Xie authored
Signed-off-by:
Alex Xie <AlexBin.Xie@amd.com> Reviewed-by:
Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Christian König<christian.koenig@amd.com> Signed-off-by:
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Rex Zhu authored
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Rex Zhu <Rex.Zhu@amd.com> Reviewed-by:
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Rex Zhu authored
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Rex Zhu authored
1. simplify avfs state switch. 2. delete save/restore VFT table functions as not support by fiji. 3. implement thermal_avfs_enable funciton. Signed-off-by:
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Rex Zhu authored
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Evan Quan authored
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Huang Rui authored
In previous case, driver can't enable psp via the kernel parameter for raven. We should open this path and set it as direct by default till psp firmware loading is workable. Signed-off-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
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Huang Rui authored
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Huang Rui authored
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Huang Rui authored
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Shaoyun Liu authored
nbio hdp flush routine are called within atomic context. Avoid use KIQ when write to the HDP_MEM_COHERENCY_FLUSH_CNTL register since this register has its own VF copy Signed-off-by:
Shaoyun Liu <Shaoyun.Liu@amd.com> Reviewed-by:
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Shaoyun Liu authored
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Monk Liu authored
for SR-IOV, we must keep the pipeline-sync in the protection of COND_EXEC, otherwise the command consumed by CPG is not consistent when world switch triggerd, e.g.: world switch hit and the IB frame is skipped so the fence won't signal, thus CP will jump to the next DMAframe's pipeline-sync command, and it will make CP hang foever. after pipelin-sync moved into COND_EXEC the consistency can be guaranteed Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Reviewed-by:
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Rex Zhu authored
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Rex Zhu authored
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Rex Zhu authored
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Rex Zhu authored
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Evan Quan authored
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Evan Quan authored
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Ken Wang authored
Certain MC registers need a delay after writing them to properly update in the init sequence. Signed-off-by:
Ken Wang <Ken.Wang@amd.com> Reviewed-by:
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