- 02 Jun, 2017 11 commits
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Phil Elwell authored
Fractional clock dividers generate accurate average frequencies but with jitter, particularly when the integer divisor is small. Introduce a new metric of clock accuracy to penalise clocks with a good average but worse jitter compared to clocks with an average which is no better but with lower jitter. The metric is the ideal rate minus the worse deviation from that ideal using the nearest integer divisors. Use this metric for parent selection for clocks requiring low jitter (currently just PCM). Signed-off-by:
Phil Elwell <phil@raspberrypi.org> Reviewed-by:
Eric Anholt <eric@anholt.net> Acked-by:
Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by:
Stephen Boyd <sboyd@codeaurora.org>
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Phil Elwell authored
Restrict clock sources for the PCM peripheral to the oscillator and PLLD_PER because other source may have varying rates or be switched off. Prevent other sources from being selected by replacing their names in the list of potential parents with dummy entries (entry index is significant). Signed-off-by:
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Phil Elwell authored
If a clock has the prediv flag set, both the integer and fractional parts must be scaled when calculating the resulting frequency. Signed-off-by:
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Stephen Boyd authored
* clk-bulk-get: clk: add managed version of clk_bulk_get clk: add clk_bulk_get accessories
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Dong Aisheng authored
This patch introduces the managed version of clk_bulk_get. Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Russell King <linux@arm.linux.org.uk> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net> Cc: Viresh Kumar <viresh.kumar@linaro.org> Cc: Mark Brown <broonie@kernel.org> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Anson Huang <anson.huang@nxp.com> Cc: Robin Gong <yibin.gong@nxp.com> Cc: Bai Ping <ping.bai@nxp.com> Cc: Leonard Crestez <leonard.crestez@nxp.com> Cc: Octavian Purdila <octavian.purdila@nxp.com> Signed-off-by:
Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by:
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Dong Aisheng authored
These helper function allows drivers to get several clk consumers in one operation. If any of the clk cannot be acquired then any clks that were got will be put before returning to the caller. This can relieve the driver owners' life who needs to handle many clocks, as well as each clock error reporting. Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Russell King <linux@arm.linux.org.uk> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net> Cc: Viresh Kumar <viresh.kumar@linaro.org> Cc: Mark Brown <broonie@kernel.org> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Anson Huang <anson.huang@nxp.com> Cc: Robin Gong <yibin.gong@nxp.com> Cc: Bai Ping <ping.bai@nxp.com> Cc: Leonard Crestez <leonard.crestez@nxp.com> Cc: Octavian Purdila <octavian.purdila@nxp.com> Signed-off-by:
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Stephen Boyd authored
These can be marked as const * const. Cc: Neil Armstrong <narmstrong@baylibre.com> Cc: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: -
git://github.com/BayLibre/clk-mesonStephen Boyd authored
Pull Amlogic clock driver updates from Jerome Brunet: * Expose more i2s and spdif output clocks * Expose EE uart and SPICC gate clocks * Remove cpu_clk from to gxbb * Mark clk81 as critical on gxbb * Add CEC EE clocks * tag 'meson-clk-for-4.13' of git://github.com/BayLibre/clk-meson: clk: meson-gxbb: Add EE 32K Clock for CEC clk: gxbb: remove CLK_IGNORE_UNUSED from clk81 clk: meson: meson8b: mark clk81 as critical clk: meson: gxbb: remove the "cpu_clk" from the GXBB and GXL driver clk: meson-gxbb: un-export the CPU clock clk: meson-gxbb: expose UART clocks clk: meson-gxbb: expose SPICC gate clk: meson-gxbb: expose spdif master clock clk: meson-gxbb: expose i2s master clock clk: meson-gxbb: expose spdif clock gates
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Arvind Yadav authored
Undo preparation of a clock source, if palmas_clks_init_configure is not successful. Signed-off-by:
Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by:
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Geert Uytterhoeven authored
When CONFIG_ON=n, dummies are provided for of_clk_get() and of_clk_get_by_name(), but not for of_clk_get_from_provider(). Provide a dummy for the latter, to improve the ability to do compile-testing. This requires removing the existing dummy in the Lantiq clock code. Fixes: 766e6a4e ("clk: add DT clock binding support") Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Acked-by:
Thomas Langer <thomas.langer@intel.com> Signed-off-by:
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Michael Turquette authored
Merge tag 'clk-renesas-for-v4.13-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next clk: renesas: Updates for v4.13 - Add more module clocks for R-Car H3 ES2.0 and M3-W, - Add CPG/MSSR drivers for all supported R-Car Gen2 SoCs, enabling support for module resets, which are not supported by the existing driver, - Rework Kconfig and Makefile logic, - Small fixes and cleanups.
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- 01 Jun, 2017 13 commits
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Bryan O'Donoghue authored
When failing to set a clock the printout emitted is incorrect. "u32 rate" is formatted as %d and should be %u whereas "unsigned long clk_set_rate()" is formatted as %ld and should be %lu as per Documentation/printk-formats.txt. Fixes: 2885c3b2 ("clk: Show correct information when fail to set clock rate") Signed-off-by:
Bryan O'Donoghue <pure.logic@nexus-software.ie> Signed-off-by:
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Sudeep Holla authored
The frequencies above the maximum value of signed integer(i.e. 2^31 -1) will overflow with the current code. This patch fixes the return type of __scpi_dvfs_round_rate from 'int' to 'unsigned long'. Fixes: cd52c2a4 ("clk: add support for clocks provided by SCP(System Control Processor)") Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by:
Sudeep Holla <sudeep.holla@arm.com> Signed-off-by:
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Scott Wood authored
ls1012a has separate input root clocks for core PLLs versus the platform PLL, with the latter described as sysclk in the hw docs. If a second input clock, named "coreclk", is present, this clock will be used for the core PLLs. Signed-off-by:
Scott Wood <oss@buserror.net> Signed-off-by:
Tang Yuantian <andy.tang@nxp.com> Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Scott Wood authored
ls1012a has separate input root clocks for core PLLs versus the platform PLL, with the latter described as sysclk in the hw docs. Update the qoriq-clock binding to allow a second input clock, named "coreclk". If present, this clock will be used for the core PLLs. Signed-off-by:
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Alexandre Belloni authored
clk_generated_startup is called after clk_hw_register. So the first call to get_parent will not have the correct value (i.e. 0) and because this is cached, it may never be updated. Signed-off-by:
Alexandre Belloni <alexandre.belloni@free-electrons.com> Fixes: df70aeef ("clk: at91: add generated clock driver") Signed-off-by:
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Fabio Estevam authored
According to the MX7D Reference Manual the powerdown bit of CCM_ANALOG_PLL_DDRn register is bit 20, so fix it accordingly. Signed-off-by:
Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by:
Stefan Agner <stefan@agner.ch> Signed-off-by:
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Ralph Sennhauser authored
The Linksys WRT3200ACM CPU is clocked at 1866MHz. Add 1866MHz to the list of supported CPU frequencies. Also update multiplier and divisor for the l2clk and ddrclk. Noticed by the following warning: [ 0.000000] Selected CPU frequency (16) unsupported Signed-off-by:
Ralph Sennhauser <ralph.sennhauser@gmail.com> Reviewed-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by:
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Michael Turquette authored
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Gregory CLEMENT authored
As for cp110, the initial intent when the binding of the ap806 system controller was to have one flat node. The idea being that what is currently a clock-only driver in drivers would become a MFD driver, exposing the clock, GPIO and pinctrl functionality. However, after taking a step back, this would lead to a messy binding. Indeed, a single node would be a GPIO controller, clock controller, pinmux controller, and more. This patch adopts a more classical solution of a top-level syscon node with sub-nodes for the individual devices. The main benefit will be to have each functional block associated to its own sub-node where we can put its own properties. The introduction of the Armada 7K/8K is still in the early stage so the plan is to remove the old binding. However, we don't want to break the device tree compatibility for the few devices already in the field. For this we still keep the support of the legacy compatible string with a big warning in the kernel about updating the device tree. Acked-by:
Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/cc8c8c40fa4c4e71133033358992ec38e5aa2be5.1496239589.git-series.gregory.clement@free-electrons.com
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Gregory CLEMENT authored
As it was done for the cp110, this patch modifies the way the clock names are created. The name of each clock is now created by using its physical address as a prefix (as it was done for the platform device names). Thanks to this we have an automatic way to compute a unique name. Reviewed-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by:
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Gregory CLEMENT authored
Instead of using &pdev->dev all over the place, introduce a pointer variable for it. Signed-off-by:
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Gregory CLEMENT authored
This patch updates the documentation according to the changes made in the patch "clk: mvebu: ap806: introduce a new binding" Acked-by:
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Gregory CLEMENT authored
This patch updates the documentation according to the change made in the patch "clk: mvebu: ap806: do not depend anymore of the *-clock-output-names": the clock names are no more part of the binding. Acked-by:
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- 29 May, 2017 10 commits
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Neil Armstrong authored
On Amlogic GX SoCs, there is two CEC controllers : - An Amlogic CEC custom in the AO domain - The Synopsys HDMI-TX Controller in the EE domain Each of these controllers needs a 32.768KHz clock, but there is two paths : - In the EE domain, the "32k_clk" this patchs is adding - In the AO domain, with a more complex dual divider more precise setup The AO 32K clock support will be pushed later in the corresponding gxbb-aoclk driver when the AE CEC driver is ready. The EE 32k_clk must be pushed earlier since mainline support for CEC in the Synopsys HDMI-TX controller is nearby. Signed-off-by:
Neil Armstrong <narmstrong@baylibre.com> [Rebased patch on top of last changes] Signed-off-by:
Jerome Brunet <jbrunet@baylibre.com>
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Jerome Brunet authored
clk81 already has CLK_IS_CRITICAL so CLK_IGNORE_UNUSED is not necessary Signed-off-by:
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Martin Blumenstingl authored
Disabling clk81 results in an immediate freeze of the whole system. This can happen "accidentally" when the last child-clock of clk81 is disabled (in this case the common clock framework also disables clk81, even if it was only enabled indirectly before). Signed-off-by:
Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by:
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Martin Blumenstingl authored
It seems that the "cpu_clk" was carried over from the meson8b clock controller driver. On Meson GX (GXBB/GXL/GXM) the registers which are used by the cpu_clk have a different purpose (in other words: they don't control the CPU clock anymore). HHI_SYS_CPU_CLK_CNTL1 bits 31:24 are reserved according to the public S905 datasheet, while bit 23 is the "A53_trace_clk_DIS" gate (which according to the datasheet should only be used in case a silicon bug is discovered) and bits 22:20 are a divider (A53_trace_clk). The meson clk-cpu code however expects that bits 28:20 are reserved for a divider (according to the public S805 datasheet this "SCALE_DIV: This value represents an N+1 divider of the input clock."). The CPU clock on Meson GX SoCs is provided by the SCPI DVFS clock driver instead. Two examples from a Meson GXL S905X SoC: - vcpu (SCPI DVFS clock 0) rate: 1000000000 / cpu_clk rate: 708000000 - vcpu (SCPI DVFS clock 0) rate: 1512000000 / cpu_clk rate: 708000000 Unfortunately the CLKID_CPUCLK was already exported (but is currently not used) to DT. Due to the removal of this clock definition there is now a hole in the clk_hw_onecell_data (which is not a problem because this case is already handled in gxbb_clkc_probe). Signed-off-by:
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Martin Blumenstingl authored
The CPU clock defined in the Meson GX clock driver is actually a left-over from the Meson8b clock controller. Un-export the clock so we can remove it from the driver. Signed-off-by:
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Helmut Klein authored
Expose the clock ids of the three none AO uarts to the dt-bindings Acked-by:
Helmut Klein <hgkr.klein@gmail.com> Signed-off-by:
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Neil Armstrong authored
Expose the SPICC gate clock to enable the SPICC controller. Acked-by:
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Jerome Brunet authored
Expose the spdif master clock and the mux to select the appropriate spdif clock parent depending on the data source. Acked-by:
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Jerome Brunet authored
Expose cts_amclk in the device tree bindings Acked-by:
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Jerome Brunet authored
Expose the clock gates required for the spdif output Acked-by:
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- 25 May, 2017 2 commits
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git://github.com/baylibre/clk-mesonMichael Turquette authored
KConfig fix: - clk: meson: gxbb: fix build error without RESET_CONTROLLER
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Boris Brezillon authored
AHB BIST gate is actually controlled with bit 7. This bug was detected while trying to use the NAND controller which is using the DMA engine to transfer data to the NAND. Since the ahb_bist_clk gate bit conflicts with the ahb_dma_clk gate bit, the core was disabling the DMA engine clock as part of its 'disable unused clks' procedure, which was causing all DMA transfers to fail after this point. Fixes: 5e737617 ("clk: sunxi-ng: Add sun5i CCU driver") Cc: stable@vger.kernel.org Reported-by:
Angus Ainslie <angus@akkea.ca> Signed-off-by:
Boris Brezillon <boris.brezillon@free-electrons.com> Tested-by:
Chen-Yu Tsai <wens@csie.org> Signed-off-by:
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- 24 May, 2017 4 commits
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Geert Uytterhoeven authored
Add a new R-Car E2 Clock Pulse Generator / Module Standby and Software Reset driver, using the CPG/MSSR driver core. This will enable support for module resets, which are not supported by the existing driver. The old driver can still be used through a Kconfig option, to preserve backward compatibility with old DTBs. Signed-off-by: -
Geert Uytterhoeven authored
Add a new R-Car V2H Clock Pulse Generator / Module Standby and Software Reset driver, using the CPG/MSSR driver core. This will enable support for module resets, which are not supported by the existing driver. The old driver can still be used through a Kconfig option, to preserve backward compatibility with old DTBs. Signed-off-by: -
Geert Uytterhoeven authored
Add a new R-Car M2-W/N Clock Pulse Generator / Module Standby and Software Reset driver, using the CPG/MSSR driver core. This will enable support for module resets, which are not supported by the existing driver. The old driver can still be used through a Kconfig option, to preserve backward compatibility with old DTBs. Signed-off-by: -
Geert Uytterhoeven authored
Add a new R-Car H2 Clock Pulse Generator / Module Standby and Software Reset driver, using the CPG/MSSR driver core. This will enable support for module resets, which are not supported by the existing driver. The old driver can still be used through a Kconfig option, to preserve backward compatibility with old DTBs. Signed-off-by:
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