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  1. 12 Mar, 2007 6 commits
    • Eric W. Biederman's avatar
      [PATCH] msi: Safer state caching. · 392ee1e6
      Eric W. Biederman authored 
      There are two ways pci_save_state and pci_restore_state are used.  As
helper functions during suspend/resume, and as helper functions around
a hardware reset event.  When used as helper functions around a hardware
reset event there is no reason to believe the calls will be paired, nor
is there a good reason to believe that if we restore the msi state from
before the reset that it will match the current msi state.  Since arch
code may change the msi message without going through the driver, drivers
currently do not have enough information to even know when to call
pci_save_state to ensure they will have msi state in sync with the other
kernel irq reception data structures.

It turns out the solution is straight forward, cache the state in the
existing msi data structures (not the magic pci saved things) and
have the msi code update the cached state each time we write to the hardware.
This means we never need to read the hardware to figure out what the hardware
state should be.

By modifying the caching in this manner we get to remove our save_state
routines and only need to provide restore_state routines.

The only fields that were at all tricky to regenerate were the msi and msi-x
control registers and the way we regenerate them currently is a bit dependent
upon assumptions on how we use the allow msi registers to be configured and used
making the code a little bit brittle.  If we ever change what cases we allow
or how we configure the msi bits we can address the fragility then.
Signed-off-by: default avatarEric W. Biederman <ebiederm@xmission.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
Acked-by: default avatarAuke Kok <auke-jan.h.kok@intel.com>
Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
      392ee1e6
    • Linus Torvalds's avatar
      Merge master.kernel.org:/home/rmk/linux-2.6-arm · 529284a0
      Linus Torvalds authored 
      * master.kernel.org:/home/rmk/linux-2.6-arm:
  [ARM] 4263/1: fix IXP4XX_NPE[ABC]_BASE_VIRT address
  [ARM] 4256/1: i.MX/MX1 SDHC fix/workaround of SD card recognition problems
  [ARM] 4255/1: i.MX/MX1 Correct MPU PLL reference clock value.
  [ARM] 4254/1: i.MX/MX1 CPU Frequency scaling honor boot loader set BCLK_DIV.
  [ARM] 4251/1: Fix sharpsl_pm dependency
  [ARM] 4250/1: Fix locomo backlight conversion error/compile failure
  [ARM] 4249/1: Fix tosa compile failure
  [ARM] 4248/1: lh7a40x: fix missing definitions for get_irqnr_preamble
  [ARM] 4247/1: Fix long name for cc9p9360dev
  ARM: OMAP: Fix OMAP2 dss2 so clk_set_parent works
  ARM: OMAP: Fix missing workqueue include in board-h2.c
  ARM: OMAP: Include missing header
      529284a0
    • Milan Svoboda's avatar
      [ARM] 4263/1: fix IXP4XX_NPE[ABC]_BASE_VIRT address · 1dee7908
      Milan Svoboda authored 
      This fixs address defines for IXP4XX_NPE[ABC]_BASE_VIRT.
They are defined as (IXP4XX_PERIPHERAL_BASE_PHYS + 0x[678]000) now,
but they should be defined as (IXP4XX_PERIPHERAL_BASE_VIRT + 0x[678]000). Note PHYS vs VIRT in IXP4XX_PERIPHERAL_BASE...
Signed-off-by: default avatarMilan Svoboda <msvoboda@ra.rockwell.com>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      1dee7908
    • Pavel Pisa's avatar
      [ARM] 4256/1: i.MX/MX1 SDHC fix/workaround of SD card recognition problems · 2cb3320b
      Pavel Pisa authored 
      The SDHC controllers cannot process shorter transfers.
They has to be handled as longer ones, but it such case CRC
error is evaluated. There was a case in the code still,
where this error is not ignored as it should to be process
these transfers.
Signed-off-by: default avatarPavel Pisa <pisa@cmp.felk.cvut.cz>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      2cb3320b
    • Pavel Pisa's avatar
      [ARM] 4255/1: i.MX/MX1 Correct MPU PLL reference clock value. · b3c6b76f
      Pavel Pisa authored 
      Only System PLL clock source is selectable by CSCR_SYSTEM_SEL
bit. MPU PLL is driven by 512*CLK32 for each case.
Signed-off-by: default avatarPavel Pisa <pisa@cmp.felk.cvut.cz>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      b3c6b76f
    • Pavel Pisa's avatar
      [ARM] 4254/1: i.MX/MX1 CPU Frequency scaling honor boot loader set BCLK_DIV. · 83b84c4e
      Pavel Pisa authored 
      The minimal bus clock prescaler should be kept at value
selected by the board / boot loader designer.
Switching frequency above startup limit could
lead to the external memory/devices misbehave.
Signed-off-by: default avatarPavel Pisa <pisa@cmp.felk.cvut.cz>
Signed-off-by: default avatarRussell King <rmk+kernel@arm.linux.org.uk>
      83b84c4e
  3. 10 Mar, 2007 34 commits
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