- 24 Nov, 2014 40 commits
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Huacai Chen authored
Machtypes of Loongson-3 machines become more and more, but there are only small differences among different machtypes. Keeping a large table of machtypes is very ugly and hard to extend. We found that the major machtype differences are UARTs information (number of UARTs, UART IRQs, UART clocks, etc.), platform devices (EC, temperature sensors, fan controllers, etc.) and some workarounds (because of some CPU bugs or mainboard bugs). In this patch we improve the UEFI-like (LEFI) interface to make all Loongson-3 machines use a same machtype "generic-loongson-machine". Signed-off-by:
Huacai Chen <chenhc@lemote.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/8324/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Huacai Chen authored
By offering Logical->Physical core id mapping, so as to reserve some physical cores via mask. This allow booting from any core when core-0 has problems. Since the maximun cores supported by Loongson-3 is 16, 32-bit cpu_startup_core_id can be split to 16-bit cpu_startup_core_id and 16-bit reserved_cores_mask for compatibility. Signed-off-by:
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Huacai Chen authored
The width of HT-bus is only 40-bit, but Loongson-3 has 48-bit physical address. This implies only node-0's memory is DMAable because high bits (Node ID) will lost. Fortunately, by configuring address windows in firmware, we can extract 2bit Node ID (bit 44~47, only bit 44~45 used now) from Loongson-3's 48-bit address space and embed it into 40-bit (bit 37~38). Every NUMA node can do DMA now (however, maximum memory of each node is reduced to 2^37 = 128GB). Signed-off-by:
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Isamu Mogi authored
Signed-off-by:
Isamu Mogi <isamu@leafytree.jp> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8292/Signed-off-by:
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Isamu Mogi authored
Also include asm/mmu_context.h for ASID_MASK. Signed-off-by:
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Ralf Baechle authored
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Rafał Miłecki authored
Initializaion with memory allocator available will be much simpler, this will allow cleanup in the bcma code. Signed-off-by:
Rafał Miłecki <zajec5@gmail.com> Acked-by:
Hauke Mehrtens <hauke@hauke-m.de> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8234/Signed-off-by:
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Rafał Miłecki authored
This is some general cleanup as well as preparing sprom.c to become a standalone driver. We will need this for bcm53xx ARM arch support. Signed-off-by:
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Rafał Miłecki authored
This drops ssb/bcma dependency and will allow us to make it a standalone driver. Signed-off-by:
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Rafał Miłecki authored
This makes NVRAM code less bcm47xx/ssb specific allowing it to become a standalone driver in the future. A similar patch for bcma will follow when it's ready. Signed-off-by:
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Rafał Miłecki authored
We should be using ioremap_nocache helper which handles remaps in a smarter way. Signed-off-by:
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Andrew Bresticker authored
Now that the MIPS GIC irqchip lives in drivers/irqchip/, move its header over to include/linux/irqchip/. Signed-off-by:
Andrew Bresticker <abrestic@chromium.org> Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8129/Signed-off-by:
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Andrew Bresticker authored
Get rid of the ugly GICREAD/GICWRITE/GICBIS macros and use proper iomem accessors instead. Since the GIC registers are not directly accessed outside of the GIC driver any more, make gic_base static and move all the GIC register manipulation macros out of gic.h, converting them to static inline functions. Signed-off-by:
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Andrew Bresticker authored
Stop using the REG macros from gic.h and instead use proper iomem accessors. Signed-off-by:
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Andrew Bresticker authored
Stop using the REG macros from gic.h and instead use proper iomem accessors. Signed-off-by:
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Andrew Bresticker authored
Export the function gic_get_count_width to read the width of the GIC global counter from GIC_SH_CONFIG. Update the GIC clocksource driver to use this new function. Signed-off-by:
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Andrew Bresticker authored
Instead of reading the GIC registers directly, use the interface the GIC driver already exposes for reading the global timer. Also get rid of the unnecessary #ifdefs. Signed-off-by:
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Andrew Bresticker authored
The generic plat_irq_dispatch provided in irq_cpu.c is sufficient for dispatching interrupts on SEAD-3 in legacy and vectored interrupt modes. Signed-off-by:
Qais Yousef <qais.yousef@imgtec.com> Tested-by:
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Andrew Bresticker authored
The generic plat_irq_dispatch provided in irq_cpu.c is sufficient for dispatching interrupts on Malta in legacy and vectored interrupt modes. Signed-off-by:
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Andrew Bresticker authored
Now that all GIC interrupt routing and handling logic is in the GIC driver itself, un-export variables/functions which are no longer used outside the GIC driver. This also allows us to remove gic_compare_int and combine gic_get_int_mask with gic_get_int since these interfaces are no longer used. Signed-off-by:
Jason Cooper <jason@lakedaemon.net> Reviewed-by:
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Andrew Bresticker authored
The MIPS GIC supports 7 local interrupts, 2 of which are the GIC local watchdog and count/compare timer. The remainder are CPU interrupts which may optionally be re-routed through the GIC. GIC hardware IRQs 0-6 are now used for local interrupts while hardware IRQs 7+ are used for external (shared) interrupts. Note that the 5 CPU interrupts may not be re-routable through the GIC. In that case mapping will fail and the vectors reported in C0_IntCtl should be used instead. gic_get_c0_compare_int() and gic_get_c0_perfcount_int() will return the correct IRQ number to use for the C0 timer and perfcounter interrupts based on the routability of those interrupts through the GIC. A separate irq_chip, with callbacks that mask/unmask the local interrupt on all CPUs, is used for the C0 timer and performance counter interrupts since all other platforms do not use the percpu IRQ API for those interrupts. Malta, SEAD-3, and the GIC clockevent driver have been updated to use local interrupts and the R4K clockevent driver has been updated to poll for C0 timer interrupts through the GIC when the GIC is present. Signed-off-by:
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Andrew Bresticker authored
GIC edge-triggered interrupts must be acknowledged by clearing the edge detector via a write to GIC_SH_WEDGE. Create a separate edge-triggered irq_chip with the appropriate irq_ack() callback. This also allows us to get rid of gic_irq_flags. Signed-off-by:
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Andrew Bresticker authored
Instead of requiring platforms to define the correct GIC_NUM_INTRS, use the value reported in GIC_SH_CONFIG. Signed-off-by:
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Andrew Bresticker authored
Now that the GIC properly uses IRQ domains, kill off the per-platform routing tables that were used to make the GIC appear transparent. This includes: - removing the mapping tables and the support for applying them, - moving GIC IPI support to the GIC driver, - properly routing the i8259 through the GIC on Malta, and - updating IRQ assignments on SEAD-3 when the GIC is present. Platforms no longer will pass an interrupt mapping table to gic_init. Instead, they will pass the CPU interrupt vector (2 - 7) that they expect the GIC to route interrupts to. Note that in EIC mode this value is ignored and all GIC interrupts are routed to EIC vector 1. Signed-off-by:
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Andrew Bresticker authored
Use a simple IRQ domain for the MIPS GIC. Remove the gic_platform_init callback as it's no longer necessary for it to set the irqchip. Signed-off-by:
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Andrew Bresticker authored
If the online CPU check in gic_set_affinity() fails, return a proper errno value instead of -1. Signed-off-by:
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Andrew Bresticker authored
Implement an irq_set_type callback for the GIC which is used to set the polarity and trigger type of GIC interrupts. Signed-off-by:
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Andrew Bresticker authored
There's no need for platforms to have their own GIC irq_ack/irq_eoi callbacks. irq_ack need only clear the GIC's edge detector on edge-triggered interrupts and there's no need at all for irq_eoi. Also get rid of the mask_ack callback since it's not necessary either. Signed-off-by:
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Andrew Bresticker authored
Move GIC irqchip support to drivers/irqchip/ and rename the Kconfig option from IRQ_GIC to MIPS_GIC to avoid confusion with the ARM GIC. Signed-off-by:
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Andrew Bresticker authored
Define a generic MIPS_GIC_IRQ_BASE which should be suitable for all current boards in <mach-generic/irq.h>. Signed-off-by:
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Andrew Bresticker authored
The GIC on Malta boards supports a total of 47 interrupts (40 shared and 7 local) and is assigned a base of 24. This overlaps with the MSC01 interrupt assignments which have a base of 64, so move the MSC01 interrupt base back a bit to give the GIC some room. Signed-off-by:
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Andrew Bresticker authored
In preparation for GIC IRQ domain support, assign a GIC IRQ base that does not overlap with the CPU IRQs. Note that this breaks SEAD-3 when the GIC is in EIC mode, though I'm not convinced it was working before either. It will be fixed in the following patches. Signed-off-by:
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Andrew Bresticker authored
It's a duplicate of sead3-platform.c and is not even compiled. Remove it before we start fixing up IRQ assignments. Signed-off-by:
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Andrew Bresticker authored
Nothing calls gic_{enable,disable}_interrupt() any more. Signed-off-by: -
Andrew Bresticker authored
Currently interrupt vectors 2 and 5 are left disabled on secondary CPUs. Since systems using CPS must also have a GIC, which is responsible for routing all external interrupts and can map them to any hardware interrupt vector, enable the remaining vectors. The two software interrupt vectors are left disabled since they are not used with CPS. Signed-off-by:
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Andrew Bresticker authored
The hardware perf event driver and oprofile interpret the global cp0_perfcount_irq differently: in the hardware perf event driver it is an offset from MIPS_CPU_IRQ_BASE and in oprofile it is the actual IRQ number. This still works most of the time since MIPS_CPU_IRQ_BASE is usually 0, but is clearly wrong. Since the performance counter interrupt may vary from platform to platform like the C0 timer interrupt, add the optional get_c0_perfcount_int hook which returns the IRQ number of the performance counter. The hook should return < 0 if the performance counter interrupt is shared with the timer. If the hook is not present, the CPU vector reported in C0_IntCtl (cp0_perfcount_irq) is used. Signed-off-by:
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Andrew Bresticker authored
Create a legacy IRQ domain for the 16 i8259 interrupts. Signed-off-by:
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Andrew Bresticker authored
When mapping an interrupt in the CPU IRQ domain, set the vint handler for that interrupt if the CPU uses vectored interrupt handling. Signed-off-by:
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Andrew Bresticker authored
For platforms which boot with device-tree or have correctly chained all external interrupt controllers, a generic plat_irq_dispatch() can be used. Implement a plat_irq_dispatch() which simply handles all the pending interrupts as reported by C0_Cause. Signed-off-by:
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Andrew Bresticker authored
mips_cpu_intc_init() is used for DT-based initialization of the CPU IRQ domain. Give it a more appropriate name. Signed-off-by:
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